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feat: 增加CRC-16校验(顺便添加了缺少的厂家设备驱动)

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feat: 增加第三方模块 lwrb
feat: 增加麦轮逆解部分
feat: 增加LOG输出格式
This commit is contained in:
bmy
2024-04-22 11:34:39 +08:00
parent af1b9dc867
commit 838c8bb81e
44 changed files with 15100 additions and 516 deletions
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201
libraries/drivers/inc/at32f403a_407_acc.h Normal file
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/**
**************************************************************************
* @file at32f403a_407_acc.h
* @brief at32f403a_407 acc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F403A_407_ACC_H
#define __AT32F403A_407_ACC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f403a_407.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @addtogroup ACC
* @{
*/
/** @defgroup ACC_exported_constants
* @{
*/
#define ACC_CAL_HICKCAL ((uint16_t)0x0000) /*!< acc hick calibration */
#define ACC_CAL_HICKTRIM ((uint16_t)0x0002) /*!< acc hick trim */
#define ACC_RSLOST_FLAG ((uint16_t)0x0002) /*!< acc reference signal lost error flag */
#define ACC_CALRDY_FLAG ((uint16_t)0x0001) /*!< acc internal high-speed clock calibration ready error flag */
#define ACC_CALRDYIEN_INT ((uint16_t)0x0020) /*!< acc internal high-speed clock calibration ready interrupt enable */
#define ACC_EIEN_INT ((uint16_t)0x0010) /*!< acc reference signal lost interrupt enable */
/**
* @}
*/
/** @defgroup ACC_exported_types
* @{
*/
/**
* @brief type define acc register all
*/
typedef struct
{
/**
* @brief acc sts register, offset:0x00
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t calrdy : 1; /* [0] */
__IO uint32_t rslost : 1; /* [1] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} sts_bit;
};
/**
* @brief acc ctrl1 register, offset:0x04
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t calon : 1; /* [0] */
__IO uint32_t entrim : 1; /* [1] */
__IO uint32_t reserved1 : 2; /* [3:2] */
__IO uint32_t eien : 1; /* [4] */
__IO uint32_t calrdyien : 1; /* [5] */
__IO uint32_t reserved2 : 2; /* [7:6] */
__IO uint32_t step : 4; /* [11:8] */
__IO uint32_t reserved3 : 20;/* [31:12] */
} ctrl1_bit;
};
/**
* @brief acc ctrl2 register, offset:0x08
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t hickcal : 8; /* [7:0] */
__IO uint32_t hicktrim : 6; /* [13:8] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} ctrl2_bit;
};
/**
* @brief acc acc_c1 register, offset:0x0C
*/
union
{
__IO uint32_t c1;
struct
{
__IO uint32_t c1 : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} c1_bit;
};
/**
* @brief acc acc_c2 register, offset:0x10
*/
union
{
__IO uint32_t c2;
struct
{
__IO uint32_t c2 : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} c2_bit;
};
/**
* @brief acc acc_c3 register, offset:0x14
*/
union
{
__IO uint32_t c3;
struct
{
__IO uint32_t c3 : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} c3_bit;
};
} acc_type;
/**
* @}
*/
#define ACC ((acc_type *) ACC_BASE)
/** @defgroup ACC_exported_functions
* @{
*/
void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state);
void acc_step_set(uint8_t step_value);
void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state);
uint8_t acc_hicktrim_get(void);
uint8_t acc_hickcal_get(void);
void acc_write_c1(uint16_t acc_c1_value);
void acc_write_c2(uint16_t acc_c2_value);
void acc_write_c3(uint16_t acc_c3_value);
uint16_t acc_read_c1(void);
uint16_t acc_read_c2(void);
uint16_t acc_read_c3(void);
flag_status acc_flag_get(uint16_t acc_flag);
flag_status acc_interrupt_flag_get(uint16_t acc_flag);
void acc_flag_clear(uint16_t acc_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

788
libraries/drivers/inc/at32f403a_407_bpr.h Normal file
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/**
**************************************************************************
* @file at32f403a_407_bpr.h
* @brief at32f403a_407 bpr header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F403A_407_BPR_H
#define __AT32F403A_407_BPR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f403a_407.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @addtogroup BPR
* @{
*/
/** @defgroup BPR_flags_definition
* @brief bpr flag
* @{
*/
#define BPR_TAMPER_INTERRUPT_FLAG ((uint32_t)0x00000001) /*!< bpr tamper interrupt flag */
#define BPR_TAMPER_EVENT_FLAG ((uint32_t)0x00000002) /*!< bpr tamper event flag */
/**
* @}
*/
/** @defgroup BPR_exported_types
* @{
*/
/**
* @brief battery powered register data type
*/
typedef enum
{
BPR_DATA1 = 0x04, /*!< bpr data register 1 */
BPR_DATA2 = 0x08, /*!< bpr data register 2 */
BPR_DATA3 = 0x0C, /*!< bpr data register 3 */
BPR_DATA4 = 0x10, /*!< bpr data register 4 */
BPR_DATA5 = 0x14, /*!< bpr data register 5 */
BPR_DATA6 = 0x18, /*!< bpr data register 6 */
BPR_DATA7 = 0x1C, /*!< bpr data register 7 */
BPR_DATA8 = 0x20, /*!< bpr data register 8 */
BPR_DATA9 = 0x24, /*!< bpr data register 9 */
BPR_DATA10 = 0x28, /*!< bpr data register 10 */
BPR_DATA11 = 0x40, /*!< bpr data register 11 */
BPR_DATA12 = 0x44, /*!< bpr data register 12 */
BPR_DATA13 = 0x48, /*!< bpr data register 13 */
BPR_DATA14 = 0x4C, /*!< bpr data register 14 */
BPR_DATA15 = 0x50, /*!< bpr data register 15 */
BPR_DATA16 = 0x54, /*!< bpr data register 16 */
BPR_DATA17 = 0x58, /*!< bpr data register 17 */
BPR_DATA18 = 0x5C, /*!< bpr data register 18 */
BPR_DATA19 = 0x60, /*!< bpr data register 19 */
BPR_DATA20 = 0x64, /*!< bpr data register 20 */
BPR_DATA21 = 0x68, /*!< bpr data register 21 */
BPR_DATA22 = 0x6C, /*!< bpr data register 22 */
BPR_DATA23 = 0x70, /*!< bpr data register 23 */
BPR_DATA24 = 0x74, /*!< bpr data register 24 */
BPR_DATA25 = 0x78, /*!< bpr data register 25 */
BPR_DATA26 = 0x7C, /*!< bpr data register 26 */
BPR_DATA27 = 0x80, /*!< bpr data register 27 */
BPR_DATA28 = 0x84, /*!< bpr data register 28 */
BPR_DATA29 = 0x88, /*!< bpr data register 29 */
BPR_DATA30 = 0x8C, /*!< bpr data register 30 */
BPR_DATA31 = 0x90, /*!< bpr data register 31 */
BPR_DATA32 = 0x94, /*!< bpr data register 32 */
BPR_DATA33 = 0x98, /*!< bpr data register 33 */
BPR_DATA34 = 0x9C, /*!< bpr data register 34 */
BPR_DATA35 = 0xA0, /*!< bpr data register 35 */
BPR_DATA36 = 0xA4, /*!< bpr data register 36 */
BPR_DATA37 = 0xA8, /*!< bpr data register 37 */
BPR_DATA38 = 0xAC, /*!< bpr data register 38 */
BPR_DATA39 = 0xB0, /*!< bpr data register 39 */
BPR_DATA40 = 0xB4, /*!< bpr data register 40 */
BPR_DATA41 = 0xB8, /*!< bpr data register 41 */
BPR_DATA42 = 0xBC /*!< bpr data register 42 */
} bpr_data_type;
/**
* @brief bpr rtc output type
*/
typedef enum
{
BPR_RTC_OUTPUT_NONE = 0x000, /*!< output disable */
BPR_RTC_OUTPUT_CLOCK_CAL_BEFORE = 0x080, /*!< output clock before calibration */
BPR_RTC_OUTPUT_ALARM = 0x100, /*!< output alarm event with pluse mode */
BPR_RTC_OUTPUT_SECOND = 0x300, /*!< output second event with pluse mode */
BPR_RTC_OUTPUT_CLOCK_CAL_AFTER = 0x480, /*!< output clock after calibration */
BPR_RTC_OUTPUT_ALARM_TOGGLE = 0x900, /*!< output alarm event with toggle mode */
BPR_RTC_OUTPUT_SECOND_TOGGLE = 0xB00 /*!< output second event with toggle mode */
} bpr_rtc_output_type;
/**
* @brief tamper pin active level type
*/
typedef enum
{
BPR_TAMPER_PIN_ACTIVE_HIGH = 0x00, /*!< tamper pin input active level is high */
BPR_TAMPER_PIN_ACTIVE_LOW = 0x01 /*!< tamper pin input active level is low */
} bpr_tamper_pin_active_level_type;
/**
* @brief type define bpr register all
*/
typedef struct
{
/**
* @brief reserved, offset:0x00
*/
__IO uint32_t reserved1;
/**
* @brief bpr dt1 register, offset:0x04
*/
union
{
__IO uint32_t dt1;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt1_bit;
};
/**
* @brief bpr dt2 register, offset:0x08
*/
union
{
__IO uint32_t dt2;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt2_bit;
};
/**
* @brief bpr dt3 register, offset:0x0C
*/
union
{
__IO uint32_t dt3;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt3_bit;
};
/**
* @brief bpr dt4 register, offset:0x10
*/
union
{
__IO uint32_t dt4;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt4_bit;
};
/**
* @brief bpr dt5 register, offset:0x14
*/
union
{
__IO uint32_t dt5;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt5_bit;
};
/**
* @brief bpr dt6 register, offset:0x18
*/
union
{
__IO uint32_t dt6;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt6_bit;
};
/**
* @brief bpr dt7 register, offset:0x1C
*/
union
{
__IO uint32_t dt7;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt7_bit;
};
/**
* @brief bpr dt8 register, offset:0x20
*/
union
{
__IO uint32_t dt8;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt8_bit;
};
/**
* @brief bpr dt9 register, offset:0x24
*/
union
{
__IO uint32_t dt9;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt9_bit;
};
/**
* @brief bpr dt10 register, offset:0x28
*/
union
{
__IO uint32_t dt10;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt10_bit;
};
/**
* @brief bpr rtccal register, offset:0x2C
*/
union
{
__IO uint32_t rtccal;
struct
{
__IO uint32_t calval : 7; /* [6:0] */
__IO uint32_t calout : 1; /* [7] */
__IO uint32_t outen : 1; /* [8] */
__IO uint32_t outsel : 1; /* [9] */
__IO uint32_t ccos : 1; /* [10] */
__IO uint32_t outm : 1; /* [11] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} rtccal_bit;
};
/**
* @brief bpr ctrl register, offset:0x30
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t tpen : 1; /* [0] */
__IO uint32_t tpp : 1; /* [1] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} ctrl_bit;
};
/**
* @brief bpr ctrlsts register, offset:0x34
*/
union
{
__IO uint32_t ctrlsts;
struct
{
__IO uint32_t tpefclr : 1;/* [0] */
__IO uint32_t tpifclr : 1;/* [1] */
__IO uint32_t tpien : 1;/* [2] */
__IO uint32_t reserved1 : 5;/* [7:3] */
__IO uint32_t tpef : 1;/* [8] */
__IO uint32_t tpif : 1;/* [9] */
__IO uint32_t reserved2 : 22;/* [31:10] */
} ctrlsts_bit;
};
/**
* @brief reserved, offset:0x38
*/
__IO uint32_t reserved2;
/**
* @brief reserved, offset:0x3C
*/
__IO uint32_t reserved3;
/**
* @brief bpr dt11 register, offset:0x40
*/
union
{
__IO uint32_t dt11;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt11_bit;
};
/**
* @brief bpr dt12 register, offset:0x44
*/
union
{
__IO uint32_t dt12;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt12_bit;
};
/**
* @brief bpr dt13 register, offset:0x48
*/
union
{
__IO uint32_t dt13;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt13_bit;
};
/**
* @brief bpr dt14 register, offset:0x4C
*/
union
{
__IO uint32_t dt14;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt14_bit;
};
/**
* @brief bpr dt15 register, offset:0x50
*/
union
{
__IO uint32_t dt15;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt15_bit;
};
/**
* @brief bpr dt16 register, offset:0x54
*/
union
{
__IO uint32_t dt16;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt16_bit;
};
/**
* @brief bpr dt17 register, offset:0x58
*/
union
{
__IO uint32_t dt17;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt17_bit;
};
/**
* @brief bpr dt18 register, offset:0x5C
*/
union
{
__IO uint32_t dt18;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt18_bit;
};
/**
* @brief bpr dt19 register, offset:0x60
*/
union
{
__IO uint32_t dt19;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt19_bit;
};
/**
* @brief bpr dt20 register, offset:0x64
*/
union
{
__IO uint32_t dt20;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt20_bit;
};
/**
* @brief bpr dt21 register, offset:0x68
*/
union
{
__IO uint32_t dt21;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt21_bit;
};
/**
* @brief bpr dt22 register, offset:6C
*/
union
{
__IO uint32_t dt22;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt22_bit;
};
/**
* @brief bpr dt23 register, offset:0x70
*/
union
{
__IO uint32_t dt23;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt23_bit;
};
/**
* @brief bpr dt24 register, offset:0x74
*/
union
{
__IO uint32_t dt24;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt24_bit;
};
/**
* @brief bpr dt25 register, offset:0x78
*/
union
{
__IO uint32_t dt25;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt25_bit;
};
/**
* @brief bpr dt26 register, offset:0x7C
*/
union
{
__IO uint32_t dt26;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt26_bit;
};
/**
* @brief bpr dt27 register, offset:0x80
*/
union
{
__IO uint32_t dt27;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt27_bit;
};
/**
* @brief bpr dt28 register, offset:0x84
*/
union
{
__IO uint32_t dt28;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt28_bit;
};
/**
* @brief bpr dt29 register, offset:0x88
*/
union
{
__IO uint32_t dt29;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt29_bit;
};
/**
* @brief bpr dt30 register, offset:0x8C
*/
union
{
__IO uint32_t dt30;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt30_bit;
};
/**
* @brief bpr dt31 register, offset:0x90
*/
union
{
__IO uint32_t dt31;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt31_bit;
};
/**
* @brief bpr dt32 register, offset:0x94
*/
union
{
__IO uint32_t dt32;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt32_bit;
};
/**
* @brief bpr dt33 register, offset:0x98
*/
union
{
__IO uint32_t dt33;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt33_bit;
};
/**
* @brief bpr dt34 register, offset:0x9C
*/
union
{
__IO uint32_t dt34;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt34_bit;
};
/**
* @brief bpr dt35 register, offset:0xA0
*/
union
{
__IO uint32_t dt35;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt35_bit;
};
/**
* @brief bpr dt36 register, offset:0xA4
*/
union
{
__IO uint32_t dt36;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt36_bit;
};
/**
* @brief bpr dt37 register, offset:0xA8
*/
union
{
__IO uint32_t dt37;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt37_bit;
};
/**
* @brief bpr dt38 register, offset:0xAC
*/
union
{
__IO uint32_t dt38;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt38_bit;
};
/**
* @brief bpr dt39 register, offset:0xB0
*/
union
{
__IO uint32_t dt39;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt39_bit;
};
/**
* @brief bpr dt40 register, offset:0xB4
*/
union
{
__IO uint32_t dt40;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt40_bit;
};
/**
* @brief bpr dt41 register, offset:0xB8
*/
union
{
__IO uint32_t dt41;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt41_bit;
};
/**
* @brief bpr dt42 register, offset:0xBC
*/
union
{
__IO uint32_t dt42;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} dt42_bit;
};
} bpr_type;
/**
* @}
*/
#define BPR ((bpr_type *) BPR_BASE)
/** @defgroup BPR_exported_functions
* @{
*/
void bpr_reset(void);
flag_status bpr_flag_get(uint32_t flag);
flag_status bpr_interrupt_flag_get(uint32_t flag);
void bpr_flag_clear(uint32_t flag);
void bpr_interrupt_enable(confirm_state new_state);
uint16_t bpr_data_read(bpr_data_type bpr_data);
void bpr_data_write(bpr_data_type bpr_data, uint16_t data_value);
void bpr_rtc_output_select(bpr_rtc_output_type output_source);
void bpr_rtc_clock_calibration_value_set(uint8_t calibration_value);
void bpr_tamper_pin_enable(confirm_state new_state);
void bpr_tamper_pin_active_level_set(bpr_tamper_pin_active_level_type active_level);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f403a_407_crc.h
* @brief at32f403a_407 crc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F403A_407_CRC_H
#define __AT32F403A_407_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f403a_407.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_exported_types
* @{
*/
/**
* @brief crc reverse input data
*/
typedef enum
{
CRC_REVERSE_INPUT_NO_AFFECTE = 0x00, /*!< input data no reverse */
CRC_REVERSE_INPUT_BY_BYTE = 0x01, /*!< input data reverse by byte */
CRC_REVERSE_INPUT_BY_HALFWORD = 0x02, /*!< input data reverse by half word */
CRC_REVERSE_INPUT_BY_WORD = 0x03 /*!< input data reverse by word */
} crc_reverse_input_type;
/**
* @brief crc reverse output data
*/
typedef enum
{
CRC_REVERSE_OUTPUT_NO_AFFECTE = 0x00, /*!< output data no reverse */
CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
} crc_reverse_output_type;
/**
* @brief crc polynomial size
*/
typedef enum
{
CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */
CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */
CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */
CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */
} crc_poly_size_type;
/**
* @brief type define crc register all
*/
typedef struct
{
/**
* @brief crc dt register, offset:0x00
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 32; /* [31:0] */
} dt_bit;
};
/**
* @brief crc cdt register, offset:0x04
*/
union
{
__IO uint32_t cdt;
struct
{
__IO uint32_t cdt : 8 ; /* [7:0] */
__IO uint32_t reserved1 : 24 ;/* [31:8] */
} cdt_bit;
};
/**
* @brief crc ctrl register, offset:0x08
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t rst : 1 ; /* [0] */
__IO uint32_t reserved1 : 2 ; /* [2:1] */
__IO uint32_t poly_size : 2 ; /* [4:3] */
__IO uint32_t revid : 2 ; /* [6:5] */
__IO uint32_t revod : 1 ; /* [7] */
__IO uint32_t reserved2 : 24 ;/* [31:8] */
} ctrl_bit;
};
/**
* @brief crm reserved1 register, offset:0x0C
*/
__IO uint32_t reserved1;
/**
* @brief crc idt register, offset:0x10
*/
union
{
__IO uint32_t idt;
struct
{
__IO uint32_t idt : 32; /* [31:0] */
} idt_bit;
};
/**
* @brief crc polynomial register, offset:0x14
*/
union
{
__IO uint32_t poly;
struct
{
__IO uint32_t poly : 32; /* [31:0] */
} poly_bit;
};
} crc_type;
/**
* @}
*/
#define CRC ((crc_type *) CRC_BASE)
/** @defgroup CRC_exported_functions
* @{
*/
void crc_data_reset(void);
uint32_t crc_one_word_calculate(uint32_t data);
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
uint32_t crc_data_get(void);
void crc_common_data_set(uint8_t cdt_value);
uint8_t crc_common_data_get(void);
void crc_init_data_set(uint32_t value);
void crc_reverse_input_data_set(crc_reverse_input_type value);
void crc_reverse_output_data_set(crc_reverse_output_type value);
void crc_poly_value_set(uint32_t value);
uint32_t crc_poly_value_get(void);
void crc_poly_size_set(crc_poly_size_type size);
crc_poly_size_type crc_poly_size_get(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f403a_407_dac.h
* @brief at32f403a_407 dac header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F403A_407_DAC_H
#define __AT32F403A_407_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f403a_407.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @addtogroup DAC
* @{
*/
#define DAC1_D1DMAUDRF ((uint32_t)(0x00002000))
#define DAC2_D2DMAUDRF ((uint32_t)(0x20000000))
/** @defgroup DAC_exported_types
* @{
*/
/**
* @brief dac select type
*/
typedef enum
{
DAC1_SELECT = 0x01, /*!< dac1 select */
DAC2_SELECT = 0x02 /*!< dac2 select */
} dac_select_type;
/**
* @brief dac trigger type
*/
typedef enum
{
DAC_TMR6_TRGOUT_EVENT = 0x00, /*!< dac trigger selection:timer6 trgout event */
DAC_TMR8_TRGOUT_EVENT = 0x01, /*!< dac trigger selection:timer8 trgout event */
DAC_TMR7_TRGOUT_EVENT = 0x02, /*!< dac trigger selection:timer7 trgout event */
DAC_TMR5_TRGOUT_EVENT = 0x03, /*!< dac trigger selection:timer5 trgout event */
DAC_TMR2_TRGOUT_EVENT = 0x04, /*!< dac trigger selection:timer2 trgout event */
DAC_TMR4_TRGOUT_EVENT = 0x05, /*!< dac trigger selection:timer4 trgout event */
DAC_EXTERNAL_INTERRUPT_LINE_9 = 0x06, /*!< dac trigger selection:external line9 */
DAC_SOFTWARE_TRIGGER = 0x07 /*!< dac trigger selection:software trigger */
} dac_trigger_type;
/**
* @brief dac wave type
*/
typedef enum
{
DAC_WAVE_GENERATE_NONE = 0x00, /*!< dac wave generation disabled */
DAC_WAVE_GENERATE_NOISE = 0x01, /*!< dac noise wave generation enabled */
DAC_WAVE_GENERATE_TRIANGLE = 0x02 /*!< dac triangle wave generation enabled */
} dac_wave_type;
/**
* @brief dac mask amplitude type
*/
typedef enum
{
DAC_LSFR_BIT0_AMPLITUDE_1 = 0x00, /*!< unmask bit0/ triangle amplitude equal to 1 */
DAC_LSFR_BIT10_AMPLITUDE_3 = 0x01, /*!< unmask bit[1:0]/ triangle amplitude equal to 3 */
DAC_LSFR_BIT20_AMPLITUDE_7 = 0x02, /*!< unmask bit[2:0]/ triangle amplitude equal to 7 */
DAC_LSFR_BIT30_AMPLITUDE_15 = 0x03, /*!< unmask bit[3:0]/ triangle amplitude equal to 15 */
DAC_LSFR_BIT40_AMPLITUDE_31 = 0x04, /*!< unmask bit[4:0]/ triangle amplitude equal to 31 */
DAC_LSFR_BIT50_AMPLITUDE_63 = 0x05, /*!< unmask bit[5:0]/ triangle amplitude equal to 63 */
DAC_LSFR_BIT60_AMPLITUDE_127 = 0x06, /*!< unmask bit[6:0]/ triangle amplitude equal to 127 */
DAC_LSFR_BIT70_AMPLITUDE_255 = 0x07, /*!< unmask bit[7:0]/ triangle amplitude equal to 255 */
DAC_LSFR_BIT80_AMPLITUDE_511 = 0x08, /*!< unmask bit[8:0]/ triangle amplitude equal to 511 */
DAC_LSFR_BIT90_AMPLITUDE_1023 = 0x09, /*!< unmask bit[9:0]/ triangle amplitude equal to 1023 */
DAC_LSFR_BITA0_AMPLITUDE_2047 = 0x0A, /*!< unmask bit[10:0]/ triangle amplitude equal to 2047 */
DAC_LSFR_BITB0_AMPLITUDE_4095 = 0x0B /*!< unmask bit[11:0]/ triangle amplitude equal to 4095 */
} dac_mask_amplitude_type;
/**
* @brief dac1 aligned data type
*/
typedef enum
{
DAC1_12BIT_RIGHT = 0x40007408, /*!< dac1 12-bit data right-aligned */
DAC1_12BIT_LEFT = 0x4000740C, /*!< dac1 12-bit data left-aligned */
DAC1_8BIT_RIGHT = 0x40007410 /*!< dac1 8-bit data right-aligned */
} dac1_aligned_data_type;
/**
* @brief dac2 aligned data type
*/
typedef enum
{
DAC2_12BIT_RIGHT = 0x40007414, /*!< dac2 12-bit data right-aligned */
DAC2_12BIT_LEFT = 0x40007418, /*!< dac2 12-bit data left-aligned */
DAC2_8BIT_RIGHT = 0x4000741C /*!< dac2 8-bit data right-aligned */
} dac2_aligned_data_type;
/**
* @brief dac dual data type
*/
typedef enum
{
DAC_DUAL_12BIT_RIGHT = 0x40007420, /*!<double dac 12-bit data right-aligned */
DAC_DUAL_12BIT_LEFT = 0x40007424, /*!<double dac 12-bit data left-aligned */
DAC_DUAL_8BIT_RIGHT = 0x40007428 /*!<double dac 8-bit data right-aligned */
} dac_dual_data_type;
/**
* @brief type define dac register all
*/
typedef struct
{
/**
* @brief dac ctrl register, offset:0x00
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t d1en : 1; /* [0] */
__IO uint32_t d1obdis : 1; /* [1] */
__IO uint32_t d1trgen : 1; /* [2] */
__IO uint32_t d1trgsel : 3; /* [5:3] */
__IO uint32_t d1nm : 2; /* [7:6] */
__IO uint32_t d1nbsel : 4; /* [11:8] */
__IO uint32_t d1dmaen : 1; /* [12] */
__IO uint32_t reserved1 : 3; /* [15:13] */
__IO uint32_t d2en : 1; /* [16] */
__IO uint32_t d2obdis : 1; /* [17] */
__IO uint32_t d2trgen : 1; /* [18] */
__IO uint32_t d2trgsel : 3; /* [21:19] */
__IO uint32_t d2nm : 2; /* [23:22] */
__IO uint32_t d2nbsel : 4; /* [27:24] */
__IO uint32_t d2dmaen : 1; /* [28] */
__IO uint32_t reserved2 : 3; /* [31:29] */
} ctrl_bit;
};
/**
* @brief dac swtrg register, offset:0x04
*/
union
{
__IO uint32_t swtrg;
struct
{
__IO uint32_t d1swtrg : 1; /* [0] */
__IO uint32_t d2swtrg : 1; /* [1] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} swtrg_bit;
};
/**
* @brief dac d1dth12r register, offset:0x08
*/
union
{
__IO uint32_t d1dth12r;
struct
{
__IO uint32_t d1dt12r : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:2] */
} d1dth12r_bit;
};
/**
* @brief dac d1dth12l register, offset:0x0C
*/
union
{
__IO uint32_t d1dth12l;
struct
{
__IO uint32_t d1dt12l : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:2] */
} d1dth12l_bit;
};
/**
* @brief dac d1dth8r register, offset:0x10
*/
union
{
__IO uint32_t d1dth8r;
struct
{
__IO uint32_t d1dt8r : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} d1dth8r_bit;
};
/**
* @brief dac d2dth12r register, offset:0x14
*/
union
{
__IO uint32_t d2dth12r;
struct
{
__IO uint32_t d2dt12r : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:2] */
} d2dth12r_bit;
};
/**
* @brief dac d2dth12l register, offset:0x18
*/
union
{
__IO uint32_t d2dth12l;
struct
{
__IO uint32_t d2dt12l : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:2] */
} d2dth12l_bit;
};
/**
* @brief dac d2dth8r register, offset:0x1C
*/
union
{
__IO uint32_t d2dth8r;
struct
{
__IO uint32_t d2dt8r : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} d2dth8r_bit;
};
/**
* @brief dac ddth12r register, offset:0x20
*/
union
{
__IO uint32_t ddth12r;
struct
{
__IO uint32_t dd1dt12r : 12;/* [11:0] */
__IO uint32_t reserved1 : 4; /* [15:12] */
__IO uint32_t dd2dt12r : 12;/* [27:16] */
__IO uint32_t reserved2 : 4; /* [31:28] */
} ddth12r_bit;
};
/**
* @brief dac ddth12l register, offset:0x24
*/
union
{
__IO uint32_t ddth12l;
struct
{
__IO uint32_t reserved1 : 4; /* [3:0] */
__IO uint32_t dd1dt12l : 12;/* [15:4] */
__IO uint32_t reserved2 : 4; /* [19:16] */
__IO uint32_t dd2dt12l : 12;/* [31:20] */
} ddth12l_bit;
};
/**
* @brief dac ddth8r register, offset:0x28
*/
union
{
__IO uint32_t ddth8r;
struct
{
__IO uint32_t dd1dt8r : 8; /* [7:0] */
__IO uint32_t dd2dt8r : 8; /* [15:8] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} ddth8r_bit;
};
/**
* @brief dac d1odt register, offset:0x2c
*/
union
{
__IO uint32_t d1odt;
struct
{
__IO uint32_t d1odt : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} d1odt_bit;
};
/**
* @brief dac d2odt register, offset:0x30
*/
union
{
__IO uint32_t d2odt;
struct
{
__IO uint32_t d2odt : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} d2odt_bit;
};
} dac_type;
/**
* @}
*/
#define DAC ((dac_type *) DAC_BASE)
/** @defgroup DAC_exported_functions
* @{
*/
void dac_reset(void);
void dac_enable(dac_select_type dac_select, confirm_state new_state);
void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state);
void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state);
void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_source);
void dac_software_trigger_generate(dac_select_type dac_select);
void dac_dual_software_trigger_generate(void);
void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave);
void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude);
void dac_dma_enable(dac_select_type dac_select, confirm_state new_state);
uint16_t dac_data_output_get(dac_select_type dac_select);
void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data);
void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data);
void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f403a_407_dma.h
* @brief at32f403a_407 dma header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F403A_407_DMA_H
#define __AT32F403A_407_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f403a_407.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/** @defgroup DMA_interrupts_definition
* @brief dma interrupt
* @{
*/
#define DMA_FDT_INT ((uint32_t)0x00000002) /*!< dma full data transfer interrupt */
#define DMA_HDT_INT ((uint32_t)0x00000004) /*!< dma half data transfer interrupt */
#define DMA_DTERR_INT ((uint32_t)0x00000008) /*!< dma errorr interrupt */
/**
* @}
*/
/** @defgroup DMA_flexible_channel
* @{
*/
#define FLEX_CHANNEL1 ((uint8_t)0x01) /*!< dma flexible channel1 */
#define FLEX_CHANNEL2 ((uint8_t)0x02) /*!< dma flexible channel2 */
#define FLEX_CHANNEL3 ((uint8_t)0x03) /*!< dma flexible channel3 */
#define FLEX_CHANNEL4 ((uint8_t)0x04) /*!< dma flexible channel4 */
#define FLEX_CHANNEL5 ((uint8_t)0x05) /*!< dma flexible channel5 */
#define FLEX_CHANNEL6 ((uint8_t)0x06) /*!< dma flexible channel6 */
#define FLEX_CHANNEL7 ((uint8_t)0x07) /*!< dma flexible channel7 */
/**
* @}
*/
/** @defgroup DMA_flags_definition
* @brief dma flag
* @{
*/
#define DMA1_GL1_FLAG ((uint32_t)0x00000001) /*!< dma1 channel1 global flag */
#define DMA1_FDT1_FLAG ((uint32_t)0x00000002) /*!< dma1 channel1 full data transfer flag */
#define DMA1_HDT1_FLAG ((uint32_t)0x00000004) /*!< dma1 channel1 half data transfer flag */
#define DMA1_DTERR1_FLAG ((uint32_t)0x00000008) /*!< dma1 channel1 error flag */
#define DMA1_GL2_FLAG ((uint32_t)0x00000010) /*!< dma1 channel2 global flag */
#define DMA1_FDT2_FLAG ((uint32_t)0x00000020) /*!< dma1 channel2 full data transfer flag */
#define DMA1_HDT2_FLAG ((uint32_t)0x00000040) /*!< dma1 channel2 half data transfer flag */
#define DMA1_DTERR2_FLAG ((uint32_t)0x00000080) /*!< dma1 channel2 error flag */
#define DMA1_GL3_FLAG ((uint32_t)0x00000100) /*!< dma1 channel3 global flag */
#define DMA1_FDT3_FLAG ((uint32_t)0x00000200) /*!< dma1 channel3 full data transfer flag */
#define DMA1_HDT3_FLAG ((uint32_t)0x00000400) /*!< dma1 channel3 half data transfer flag */
#define DMA1_DTERR3_FLAG ((uint32_t)0x00000800) /*!< dma1 channel3 error flag */
#define DMA1_GL4_FLAG ((uint32_t)0x00001000) /*!< dma1 channel4 global flag */
#define DMA1_FDT4_FLAG ((uint32_t)0x00002000) /*!< dma1 channel4 full data transfer flag */
#define DMA1_HDT4_FLAG ((uint32_t)0x00004000) /*!< dma1 channel4 half data transfer flag */
#define DMA1_DTERR4_FLAG ((uint32_t)0x00008000) /*!< dma1 channel4 error flag */
#define DMA1_GL5_FLAG ((uint32_t)0x00010000) /*!< dma1 channel5 global flag */
#define DMA1_FDT5_FLAG ((uint32_t)0x00020000) /*!< dma1 channel5 full data transfer flag */
#define DMA1_HDT5_FLAG ((uint32_t)0x00040000) /*!< dma1 channel5 half data transfer flag */
#define DMA1_DTERR5_FLAG ((uint32_t)0x00080000) /*!< dma1 channel5 error flag */
#define DMA1_GL6_FLAG ((uint32_t)0x00100000) /*!< dma1 channel6 global flag */
#define DMA1_FDT6_FLAG ((uint32_t)0x00200000) /*!< dma1 channel6 full data transfer flag */
#define DMA1_HDT6_FLAG ((uint32_t)0x00400000) /*!< dma1 channel6 half data transfer flag */
#define DMA1_DTERR6_FLAG ((uint32_t)0x00800000) /*!< dma1 channel6 error flag */
#define DMA1_GL7_FLAG ((uint32_t)0x01000000) /*!< dma1 channel7 global flag */
#define DMA1_FDT7_FLAG ((uint32_t)0x02000000) /*!< dma1 channel7 full data transfer flag */
#define DMA1_HDT7_FLAG ((uint32_t)0x04000000) /*!< dma1 channel7 half data transfer flag */
#define DMA1_DTERR7_FLAG ((uint32_t)0x08000000) /*!< dma1 channel7 error flag */
#define DMA2_GL1_FLAG ((uint32_t)0x10000001) /*!< dma2 channel1 global flag */
#define DMA2_FDT1_FLAG ((uint32_t)0x10000002) /*!< dma2 channel1 full data transfer flag */
#define DMA2_HDT1_FLAG ((uint32_t)0x10000004) /*!< dma2 channel1 half data transfer flag */
#define DMA2_DTERR1_FLAG ((uint32_t)0x10000008) /*!< dma2 channel1 error flag */
#define DMA2_GL2_FLAG ((uint32_t)0x10000010) /*!< dma2 channel2 global flag */
#define DMA2_FDT2_FLAG ((uint32_t)0x10000020) /*!< dma2 channel2 full data transfer flag */
#define DMA2_HDT2_FLAG ((uint32_t)0x10000040) /*!< dma2 channel2 half data transfer flag */
#define DMA2_DTERR2_FLAG ((uint32_t)0x10000080) /*!< dma2 channel2 error flag */
#define DMA2_GL3_FLAG ((uint32_t)0x10000100) /*!< dma2 channel3 global flag */
#define DMA2_FDT3_FLAG ((uint32_t)0x10000200) /*!< dma2 channel3 full data transfer flag */
#define DMA2_HDT3_FLAG ((uint32_t)0x10000400) /*!< dma2 channel3 half data transfer flag */
#define DMA2_DTERR3_FLAG ((uint32_t)0x10000800) /*!< dma2 channel3 error flag */
#define DMA2_GL4_FLAG ((uint32_t)0x10001000) /*!< dma2 channel4 global flag */
#define DMA2_FDT4_FLAG ((uint32_t)0x10002000) /*!< dma2 channel4 full data transfer flag */
#define DMA2_HDT4_FLAG ((uint32_t)0x10004000) /*!< dma2 channel4 half data transfer flag */
#define DMA2_DTERR4_FLAG ((uint32_t)0x10008000) /*!< dma2 channel4 error flag */
#define DMA2_GL5_FLAG ((uint32_t)0x10010000) /*!< dma2 channel5 global flag */
#define DMA2_FDT5_FLAG ((uint32_t)0x10020000) /*!< dma2 channel5 full data transfer flag */
#define DMA2_HDT5_FLAG ((uint32_t)0x10040000) /*!< dma2 channel5 half data transfer flag */
#define DMA2_DTERR5_FLAG ((uint32_t)0x10080000) /*!< dma2 channel5 error flag */
#define DMA2_GL6_FLAG ((uint32_t)0x10100000) /*!< dma2 channel6 global flag */
#define DMA2_FDT6_FLAG ((uint32_t)0x10200000) /*!< dma2 channel6 full data transfer flag */
#define DMA2_HDT6_FLAG ((uint32_t)0x10400000) /*!< dma2 channel6 half data transfer flag */
#define DMA2_DTERR6_FLAG ((uint32_t)0x10800000) /*!< dma2 channel6 error flag */
#define DMA2_GL7_FLAG ((uint32_t)0x11000000) /*!< dma2 channel7 global flag */
#define DMA2_FDT7_FLAG ((uint32_t)0x12000000) /*!< dma2 channel7 full data transfer flag */
#define DMA2_HDT7_FLAG ((uint32_t)0x14000000) /*!< dma2 channel7 half data transfer flag */
#define DMA2_DTERR7_FLAG ((uint32_t)0x18000000) /*!< dma2 channel7 error flag */
/**
* @}
*/
/** @defgroup DMA_exported_types
* @{
*/
/**
* @brief dma flexible request type
*/
typedef enum
{
DMA_FLEXIBLE_ADC1 = 0x01, /*!< adc1 flexible request id */
DMA_FLEXIBLE_ADC3 = 0x03, /*!< adc3 flexible request id */
DMA_FLEXIBLE_DAC1 = 0x05, /*!< dac1 flexible request id */
DMA_FLEXIBLE_DAC2 = 0x06, /*!< dac2 flexible request id */
DMA_FLEXIBLE_SPI1_RX = 0x09, /*!< spi1_rx flexible request id */
DMA_FLEXIBLE_SPI1_TX = 0x0A, /*!< spi1_tx flexible request id */
DMA_FLEXIBLE_SPI2_RX = 0x0B, /*!< spi2_rx flexible request id */
DMA_FLEXIBLE_SPI2_TX = 0x0C, /*!< spi2_tx flexible request id */
DMA_FLEXIBLE_SPI3_RX = 0x0D, /*!< spi3_rx flexible request id */
DMA_FLEXIBLE_SPI3_TX = 0x0E, /*!< spi3_tx flexible request id */
DMA_FLEXIBLE_SPI4_RX = 0x0F, /*!< spi4_rx flexible request id */
DMA_FLEXIBLE_SPI4_TX = 0x10, /*!< spi4_tx flexible request id */
DMA_FLEXIBLE_I2S2EXT_RX = 0x11, /*!< i2s2ext_rx flexible request id */
DMA_FLEXIBLE_I2S2EXT_TX = 0x12, /*!< i2s2ext_tx flexible request id */
DMA_FLEXIBLE_I2S3EXT_RX = 0x13, /*!< i2s3ext_rx flexible request id */
DMA_FLEXIBLE_I2S3EXT_TX = 0x14, /*!< i2s3ext_tx flexible request id */
DMA_FLEXIBLE_UART1_RX = 0x19, /*!< uart1_rx flexible request id */
DMA_FLEXIBLE_UART1_TX = 0x1A, /*!< uart1_tx flexible request id */
DMA_FLEXIBLE_UART2_RX = 0x1B, /*!< uart2_rx flexible request id */
DMA_FLEXIBLE_UART2_TX = 0x1C, /*!< uart2_tx flexible request id */
DMA_FLEXIBLE_UART3_RX = 0x1D, /*!< uart3_rx flexible request id */
DMA_FLEXIBLE_UART3_TX = 0x1E, /*!< uart3_tx flexible request id */
DMA_FLEXIBLE_UART4_RX = 0x1F, /*!< uart4_rx flexible request id */
DMA_FLEXIBLE_UART4_TX = 0x20, /*!< uart4_tx flexible request id */
DMA_FLEXIBLE_UART5_RX = 0x21, /*!< uart5_rx flexible request id */
DMA_FLEXIBLE_UART5_TX = 0x22, /*!< uart5_tx flexible request id */
DMA_FLEXIBLE_UART6_RX = 0x23, /*!< uart6_rx flexible request id */
DMA_FLEXIBLE_UART6_TX = 0x24, /*!< uart6_tx flexible request id */
DMA_FLEXIBLE_UART7_RX = 0x25, /*!< uart7_rx flexible request id */
DMA_FLEXIBLE_UART7_TX = 0x26, /*!< uart7_tx flexible request id */
DMA_FLEXIBLE_UART8_RX = 0x27, /*!< uart8_rx flexible request id */
DMA_FLEXIBLE_UART8_TX = 0x28, /*!< uart8_tx flexible request id */
DMA_FLEXIBLE_I2C1_RX = 0x29, /*!< i2c1_rx flexible request id */
DMA_FLEXIBLE_I2C1_TX = 0x2A, /*!< i2c1_tx flexible request id */
DMA_FLEXIBLE_I2C2_RX = 0x2B, /*!< i2c2_rx flexible request id */
DMA_FLEXIBLE_I2C2_TX = 0x2C, /*!< i2c2_tx flexible request id */
DMA_FLEXIBLE_I2C3_RX = 0x2D, /*!< i2c3_rx flexible request id */
DMA_FLEXIBLE_I2C3_TX = 0x2E, /*!< i2c3_tx flexible request id */
DMA_FLEXIBLE_SDIO1 = 0x31, /*!< sdio1 flexible request id */
DMA_FLEXIBLE_SDIO2 = 0x32, /*!< sdio2 flexible request id */
DMA_FLEXIBLE_TMR1_TRIG = 0x35, /*!< tmr1_trig flexible request id */
DMA_FLEXIBLE_TMR1_HALL = 0x36, /*!< tmr1_hall flexible request id */
DMA_FLEXIBLE_TMR1_OVERFLOW = 0x37, /*!< tmr1_overflow flexible request id */
DMA_FLEXIBLE_TMR1_CH1 = 0x38, /*!< tmr1_ch1 flexible request id */
DMA_FLEXIBLE_TMR1_CH2 = 0x39, /*!< tmr1_ch2 flexible request id */
DMA_FLEXIBLE_TMR1_CH3 = 0x3A, /*!< tmr1_ch3 flexible request id */
DMA_FLEXIBLE_TMR1_CH4 = 0x3B, /*!< tmr1_ch4 flexible request id */
DMA_FLEXIBLE_TMR2_TRIG = 0x3D, /*!< tmr2_trig flexible request id */
DMA_FLEXIBLE_TMR2_OVERFLOW = 0x3F, /*!< tmr2_overflow flexible request id */
DMA_FLEXIBLE_TMR2_CH1 = 0x40, /*!< tmr2_ch1 flexible request id */
DMA_FLEXIBLE_TMR2_CH2 = 0x41, /*!< tmr2_ch2 flexible request id */
DMA_FLEXIBLE_TMR2_CH3 = 0x42, /*!< tmr2_ch3 flexible request id */
DMA_FLEXIBLE_TMR2_CH4 = 0x43, /*!< tmr2_ch4 flexible request id */
DMA_FLEXIBLE_TMR3_TRIG = 0x45, /*!< tmr3_trig flexible request id */
DMA_FLEXIBLE_TMR3_OVERFLOW = 0x47, /*!< tmr3_overflow flexible request id */
DMA_FLEXIBLE_TMR3_CH1 = 0x48, /*!< tmr3_ch1 flexible request id */
DMA_FLEXIBLE_TMR3_CH2 = 0x49, /*!< tmr3_ch2 flexible request id */
DMA_FLEXIBLE_TMR3_CH3 = 0x4A, /*!< tmr3_ch3 flexible request id */
DMA_FLEXIBLE_TMR3_CH4 = 0x4B, /*!< tmr3_ch4 flexible request id */
DMA_FLEXIBLE_TMR4_TRIG = 0x4D, /*!< tmr4_trig flexible request id */
DMA_FLEXIBLE_TMR4_OVERFLOW = 0x4F, /*!< tmr4_overflow flexible request id */
DMA_FLEXIBLE_TMR4_CH1 = 0x50, /*!< tmr4_ch1 flexible request id */
DMA_FLEXIBLE_TMR4_CH2 = 0x51, /*!< tmr4_ch2 flexible request id */
DMA_FLEXIBLE_TMR4_CH3 = 0x52, /*!< tmr4_ch3 flexible request id */
DMA_FLEXIBLE_TMR4_CH4 = 0x53, /*!< tmr4_ch4 flexible request id */
DMA_FLEXIBLE_TMR5_TRIG = 0x55, /*!< tmr5_trig flexible request id */
DMA_FLEXIBLE_TMR5_OVERFLOW = 0x57, /*!< tmr5_overflow flexible request id */
DMA_FLEXIBLE_TMR5_CH1 = 0x58, /*!< tmr5_ch1 flexible request id */
DMA_FLEXIBLE_TMR5_CH2 = 0x59, /*!< tmr5_ch2 flexible request id */
DMA_FLEXIBLE_TMR5_CH3 = 0x5A, /*!< tmr5_ch3 flexible request id */
DMA_FLEXIBLE_TMR5_CH4 = 0x5B, /*!< tmr5_ch4 flexible request id */
DMA_FLEXIBLE_TMR6_OVERFLOW = 0x5F, /*!< tmr6_overflow flexible request id */
DMA_FLEXIBLE_TMR7_OVERFLOW = 0x67, /*!< tmr7_overflow flexible request id */
DMA_FLEXIBLE_TMR8_TRIG = 0x6D, /*!< tmr8_trig flexible request id */
DMA_FLEXIBLE_TMR8_HALL = 0x6E, /*!< tmr8_hall flexible request id */
DMA_FLEXIBLE_TMR8_OVERFLOW = 0x6F, /*!< tmr8_overflow flexible request id */
DMA_FLEXIBLE_TMR8_CH1 = 0x70, /*!< tmr8_ch1 flexible request id */
DMA_FLEXIBLE_TMR8_CH2 = 0x71, /*!< tmr8_ch2 flexible request id */
DMA_FLEXIBLE_TMR8_CH3 = 0x72, /*!< tmr8_ch3 flexible request id */
DMA_FLEXIBLE_TMR8_CH4 = 0x73 /*!< tmr8_ch4 flexible request id */
} dma_flexible_request_type;
/**
* @brief dma direction type
*/
typedef enum
{
DMA_DIR_PERIPHERAL_TO_MEMORY = 0x0000, /*!< dma data transfer direction:peripheral to memory */
DMA_DIR_MEMORY_TO_PERIPHERAL = 0x0010, /*!< dma data transfer direction:memory to peripheral */
DMA_DIR_MEMORY_TO_MEMORY = 0x4000 /*!< dma data transfer direction:memory to memory */
} dma_dir_type;
/**
* @brief dma peripheral incremented type
*/
typedef enum
{
DMA_PERIPHERAL_INC_DISABLE = 0x00, /*!< dma peripheral increment mode disable */
DMA_PERIPHERAL_INC_ENABLE = 0x01 /*!< dma peripheral increment mode enable */
} dma_peripheral_inc_type;
/**
* @brief dma memory incremented type
*/
typedef enum
{
DMA_MEMORY_INC_DISABLE = 0x00, /*!< dma memory increment mode disable */
DMA_MEMORY_INC_ENABLE = 0x01 /*!< dma memory increment mode enable */
} dma_memory_inc_type;
/**
* @brief dma peripheral data size type
*/
typedef enum
{
DMA_PERIPHERAL_DATA_WIDTH_BYTE = 0x00, /*!< dma peripheral databus width 8bit */
DMA_PERIPHERAL_DATA_WIDTH_HALFWORD = 0x01, /*!< dma peripheral databus width 16bit */
DMA_PERIPHERAL_DATA_WIDTH_WORD = 0x02 /*!< dma peripheral databus width 32bit */
} dma_peripheral_data_size_type;
/**
* @brief dma memory data size type
*/
typedef enum
{
DMA_MEMORY_DATA_WIDTH_BYTE = 0x00, /*!< dma memory databus width 8bit */
DMA_MEMORY_DATA_WIDTH_HALFWORD = 0x01, /*!< dma memory databus width 16bit */
DMA_MEMORY_DATA_WIDTH_WORD = 0x02 /*!< dma memory databus width 32bit */
} dma_memory_data_size_type;
/**
* @brief dma priority level type
*/
typedef enum
{
DMA_PRIORITY_LOW = 0x00, /*!< dma channel priority: low */
DMA_PRIORITY_MEDIUM = 0x01, /*!< dma channel priority: mediue */
DMA_PRIORITY_HIGH = 0x02, /*!< dma channel priority: high */
DMA_PRIORITY_VERY_HIGH = 0x03 /*!< dma channel priority: very high */
} dma_priority_level_type;
/**
* @brief dma init type
*/
typedef struct
{
uint32_t peripheral_base_addr; /*!< base addrress for peripheral */
uint32_t memory_base_addr; /*!< base addrress for memory */
dma_dir_type direction; /*!< dma transmit direction, peripheral as source or as destnation */
uint16_t buffer_size; /*!< counter to transfer */
confirm_state peripheral_inc_enable; /*!< periphera address increment after one transmit */
confirm_state memory_inc_enable; /*!< memory address increment after one transmit */
dma_peripheral_data_size_type peripheral_data_width; /*!< peripheral data width for transmit */
dma_memory_data_size_type memory_data_width; /*!< memory data width for transmit */
confirm_state loop_mode_enable; /*!< when circular mode enable, buffer size will reload if count to 0 */
dma_priority_level_type priority; /*!< dma priority can choose from very high, high, dedium or low */
} dma_init_type;
/**
* @brief type define dma register
*/
typedef struct
{
/**
* @brief dma sts register, offset:0x00
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t gf1 : 1; /* [0] */
__IO uint32_t fdtf1 : 1; /* [1] */
__IO uint32_t hdtf1 : 1; /* [2] */
__IO uint32_t dterrf1 : 1; /* [3] */
__IO uint32_t gf2 : 1; /* [4] */
__IO uint32_t fdtf2 : 1; /* [5] */
__IO uint32_t hdtf2 : 1; /* [6] */
__IO uint32_t dterrf2 : 1; /* [7] */
__IO uint32_t gf3 : 1; /* [8] */
__IO uint32_t fdtf3 : 1; /* [9] */
__IO uint32_t hdtf3 : 1; /* [10] */
__IO uint32_t dterrf3 : 1; /* [11] */
__IO uint32_t gf4 : 1; /* [12] */
__IO uint32_t fdtf4 : 1; /* [13] */
__IO uint32_t hdtf4 : 1; /* [14] */
__IO uint32_t dterrf4 : 1; /* [15] */
__IO uint32_t gf5 : 1; /* [16] */
__IO uint32_t fdtf5 : 1; /* [17] */
__IO uint32_t hdtf5 : 1; /* [18] */
__IO uint32_t dterrf5 : 1; /* [19] */
__IO uint32_t gf6 : 1; /* [20] */
__IO uint32_t fdtf6 : 1; /* [21] */
__IO uint32_t hdtf6 : 1; /* [22] */
__IO uint32_t dterrf6 : 1; /* [23] */
__IO uint32_t gf7 : 1; /* [24] */
__IO uint32_t fdtf7 : 1; /* [25] */
__IO uint32_t hdtf7 : 1; /* [26] */
__IO uint32_t dterrf7 : 1; /* [27] */
__IO uint32_t reserved1 : 4; /* [31:28] */
} sts_bit;
};
/**
* @brief dma clr register, offset:0x04
*/
union
{
__IO uint32_t clr;
struct
{
__IO uint32_t gfc1 : 1; /* [0] */
__IO uint32_t fdtfc1 : 1; /* [1] */
__IO uint32_t hdtfc1 : 1; /* [2] */
__IO uint32_t dterrfc1 : 1; /* [3] */
__IO uint32_t gfc2 : 1; /* [4] */
__IO uint32_t fdtfc2 : 1; /* [5] */
__IO uint32_t hdtfc2 : 1; /* [6] */
__IO uint32_t dterrfc2 : 1; /* [7] */
__IO uint32_t gfc3 : 1; /* [8] */
__IO uint32_t fdtfc3 : 1; /* [9] */
__IO uint32_t hdtfc3 : 1; /* [10] */
__IO uint32_t dterrfc3 : 1; /* [11] */
__IO uint32_t gfc4 : 1; /* [12] */
__IO uint32_t fdtfc4 : 1; /* [13] */
__IO uint32_t hdtfc4 : 1; /* [14] */
__IO uint32_t dterrfc4 : 1; /* [15] */
__IO uint32_t gfc5 : 1; /* [16] */
__IO uint32_t fdtfc5 : 1; /* [17] */
__IO uint32_t hdtfc5 : 1; /* [18] */
__IO uint32_t dterrfc5 : 1; /* [19] */
__IO uint32_t gfc6 : 1; /* [20] */
__IO uint32_t fdtfc6 : 1; /* [21] */
__IO uint32_t hdtfc6 : 1; /* [22] */
__IO uint32_t dterrfc6 : 1; /* [23] */
__IO uint32_t gfc7 : 1; /* [24] */
__IO uint32_t fdtfc7 : 1; /* [25] */
__IO uint32_t hdtfc7 : 1; /* [26] */
__IO uint32_t dterrfc7 : 1; /* [27] */
__IO uint32_t reserved1 : 4; /* [31:28] */
} clr_bit;
};
/**
* @brief reserved, offset:0x08~0x9C
*/
__IO uint32_t reserved1[38];
/**
* @brief dma src_sel0 register, offset:0xA0
*/
union
{
__IO uint32_t src_sel0;
struct
{
__IO uint32_t ch1_src : 8; /* [7:0] */
__IO uint32_t ch2_src : 8; /* [15:8] */
__IO uint32_t ch3_src : 8; /* [23:16] */
__IO uint32_t ch4_src : 8; /* [31:24] */
} src_sel0_bit;
};
/**
* @brief dma src_sel1 register, offset:0xA4
*/
union
{
__IO uint32_t src_sel1;
struct
{
__IO uint32_t ch5_src : 8; /* [7:0] */
__IO uint32_t ch6_src : 8; /* [15:8] */
__IO uint32_t ch7_src : 8; /* [23:16] */
__IO uint32_t dma_flex_en : 1; /* [24] */
__IO uint32_t reserved1 : 7; /* [31:25] */
} src_sel1_bit;
};
} dma_type;
/**
* @brief type define dma channel register all
*/
typedef struct
{
/**
* @brief dma ctrl register, offset:0x08+20*(x-1) x=1...7
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t chen : 1; /* [0] */
__IO uint32_t fdtien : 1; /* [1] */
__IO uint32_t hdtien : 1; /* [2] */
__IO uint32_t dterrien : 1; /* [3] */
__IO uint32_t dtd : 1; /* [4] */
__IO uint32_t lm : 1; /* [5] */
__IO uint32_t pincm : 1; /* [6] */
__IO uint32_t mincm : 1; /* [7] */
__IO uint32_t pwidth : 2; /* [9:8] */
__IO uint32_t mwidth : 2; /* [11:10] */
__IO uint32_t chpl : 2; /* [13:12] */
__IO uint32_t m2m : 1; /* [14] */
__IO uint32_t reserved1 : 17;/* [31:15] */
} ctrl_bit;
};
/**
* @brief dma dtcnt register, offset:0x0C+20*(x-1) x=1...7
*/
union
{
__IO uint32_t dtcnt;
struct
{
__IO uint32_t cnt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} dtcnt_bit;
};
/**
* @brief dma cpba register, offset:0x10+20*(x-1) x=1...7
*/
union
{
__IO uint32_t paddr;
struct
{
__IO uint32_t paddr : 32;/* [31:0] */
} paddr_bit;
};
/**
* @brief dma cmba register, offset:0x14+20*(x-1) x=1...7
*/
union
{
__IO uint32_t maddr;
struct
{
__IO uint32_t maddr : 32;/* [31:0] */
} maddr_bit;
};
} dma_channel_type;
/**
* @}
*/
#define DMA1 ((dma_type *) DMA1_BASE)
#define DMA1_CHANNEL1 ((dma_channel_type *) DMA1_CHANNEL1_BASE)
#define DMA1_CHANNEL2 ((dma_channel_type *) DMA1_CHANNEL2_BASE)
#define DMA1_CHANNEL3 ((dma_channel_type *) DMA1_CHANNEL3_BASE)
#define DMA1_CHANNEL4 ((dma_channel_type *) DMA1_CHANNEL4_BASE)
#define DMA1_CHANNEL5 ((dma_channel_type *) DMA1_CHANNEL5_BASE)
#define DMA1_CHANNEL6 ((dma_channel_type *) DMA1_CHANNEL6_BASE)
#define DMA1_CHANNEL7 ((dma_channel_type *) DMA1_CHANNEL7_BASE)
#define DMA2 ((dma_type *) DMA2_BASE)
#define DMA2_CHANNEL1 ((dma_channel_type *) DMA2_CHANNEL1_BASE)
#define DMA2_CHANNEL2 ((dma_channel_type *) DMA2_CHANNEL2_BASE)
#define DMA2_CHANNEL3 ((dma_channel_type *) DMA2_CHANNEL3_BASE)
#define DMA2_CHANNEL4 ((dma_channel_type *) DMA2_CHANNEL4_BASE)
#define DMA2_CHANNEL5 ((dma_channel_type *) DMA2_CHANNEL5_BASE)
#define DMA2_CHANNEL6 ((dma_channel_type *) DMA2_CHANNEL6_BASE)
#define DMA2_CHANNEL7 ((dma_channel_type *) DMA2_CHANNEL7_BASE)
/** @defgroup DMA_exported_functions
* @{
*/
void dma_reset(dma_channel_type* dmax_channely);
void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number);
uint16_t dma_data_number_get(dma_channel_type* dmax_channely);
void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state);
void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state);
void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request);
flag_status dma_flag_get(uint32_t dmax_flag);
flag_status dma_interrupt_flag_get(uint32_t dmax_flag);
void dma_flag_clear(uint32_t dmax_flag);
void dma_default_para_init(dma_init_type* dma_init_struct);
void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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libraries/drivers/inc/at32f403a_407_emac.h Normal file
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libraries/drivers/inc/at32f403a_407_rtc.h Normal file
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/**
**************************************************************************
* @file at32f403a_407_rtc.h
* @brief at32f403a_407 rtc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F403A_407_RTC_H
#define __AT32F403A_407_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f403a_407.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @addtogroup RTC
* @{
*/
/** @defgroup RTC_interrupts_definition
* @brief rtc interrupt
* @{
*/
#define RTC_TS_INT ((uint16_t)0x0001) /*!< rtc time second interrupt */
#define RTC_TA_INT ((uint16_t)0x0002) /*!< rtc time alarm interrupt */
#define RTC_OVF_INT ((uint16_t)0x0004) /*!< rtc overflow interrupt */
/**
* @}
*/
/** @defgroup RTC_flags_definition
* @brief rtc flag
* @{
*/
#define RTC_TS_FLAG ((uint16_t)0x0001) /*!< rtc time second flag */
#define RTC_TA_FLAG ((uint16_t)0x0002) /*!< rtc time alarm flag */
#define RTC_OVF_FLAG ((uint16_t)0x0004) /*!< rtc overflow flag */
#define RTC_UPDF_FLAG ((uint16_t)0x0008) /*!< rtc update finish flag */
#define RTC_CFGF_FLAG ((uint16_t)0x0020) /*!< rtc configuration finish flag */
/**
* @}
*/
/** @defgroup RTC_exported_types
* @{
*/
/**
* @brief type define rtc register all
*/
typedef struct
{
/**
* @brief rtc ctrlh register, offset:0x00
*/
union
{
__IO uint32_t ctrlh;
struct
{
__IO uint32_t tsien : 1; /* [0] */
__IO uint32_t taien : 1; /* [1] */
__IO uint32_t ovfien : 1; /* [2] */
__IO uint32_t reserved1 : 29;/* [31:3] */
} ctrlh_bit;
};
/**
* @brief rtc ctrll register, offset:0x04
*/
union
{
__IO uint32_t ctrll;
struct
{
__IO uint32_t tsf : 1; /* [0] */
__IO uint32_t taf : 1; /* [1] */
__IO uint32_t ovff : 1; /* [2] */
__IO uint32_t updf : 1; /* [3] */
__IO uint32_t cfgen : 1; /* [4] */
__IO uint32_t cfgf : 1; /* [5] */
__IO uint32_t reserved1 : 26;/* [31:6] */
} ctrll_bit;
};
/**
* @brief rtc divh register, offset:0x08
*/
union
{
__IO uint32_t divh;
struct
{
__IO uint32_t div : 4; /* [3:0] */
__IO uint32_t reserved1 : 28;/* [31:4] */
} divh_bit;
};
/**
* @brief rtc divl register, offset:0x0C
*/
union
{
__IO uint32_t divl;
struct
{
__IO uint32_t div : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} divl_bit;
};
/**
* @brief rtc divcnth register, offset:0x10
*/
union
{
__IO uint32_t divcnth;
struct
{
__IO uint32_t divcnt : 4; /* [3:0] */
__IO uint32_t reserved1 : 28;/* [31:15] */
} divcnth_bit;
};
/**
* @brief rtc divcntl register, offset:0x14
*/
union
{
__IO uint32_t divcntl;
struct
{
__IO uint32_t divcnt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} divcntl_bit;
};
/**
* @brief rtc cnth register, offset:0x18
*/
union
{
__IO uint32_t cnth;
struct
{
__IO uint32_t cnt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} cnth_bit;
};
/**
* @brief rtc cntl register, offset:0x1C
*/
union
{
__IO uint32_t cntl;
struct
{
__IO uint32_t cnt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} cntl_bit;
};
/**
* @brief rtc tah register, offset:0x20
*/
union
{
__IO uint32_t tah;
struct
{
__IO uint32_t ta : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} tah_bit;
};
/**
* @brief rtc tal register, offset:0x24
*/
union
{
__IO uint32_t tal;
struct
{
__IO uint32_t ta : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:15] */
} tal_bit;
};
} rtc_type;
/**
* @}
*/
#define RTC ((rtc_type *) RTC_BASE)
/** @defgroup RTC_exported_functions
* @{
*/
void rtc_counter_set(uint32_t counter_value);
uint32_t rtc_counter_get(void);
void rtc_divider_set(uint32_t div_value);
uint32_t rtc_divider_get(void);
void rtc_alarm_set(uint32_t alarm_value);
void rtc_interrupt_enable(uint16_t source, confirm_state new_state);
flag_status rtc_flag_get(uint16_t flag);
flag_status rtc_interrupt_flag_get(uint16_t flag);
void rtc_flag_clear(uint16_t flag);
void rtc_wait_config_finish(void);
void rtc_wait_update_finish(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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libraries/drivers/inc/at32f403a_407_sdio.h Normal file
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@@ -0,0 +1,626 @@
/**
**************************************************************************
* @file at32f403a_407_sdio.h
* @brief at32f403a_407 sdio header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F403A_407_SDIO_H
#define __AT32F403A_407_SDIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f403a_407.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @addtogroup SDIO
* @{
*/
/** @defgroup SDIO_interrupts_definition
* @brief sdio interrupt
* @{
*/
#define SDIO_CMDFAIL_INT ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
#define SDIO_DTFAIL_INT ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
#define SDIO_CMDTIMEOUT_INT ((uint32_t)0x00000004) /*!< command response timerout interrupt */
#define SDIO_DTTIMEOUT_INT ((uint32_t)0x00000008) /*!< data timeout interrupt */
#define SDIO_TXERRU_INT ((uint32_t)0x00000010) /*!< transmit underrun error interrupt */
#define SDIO_RXERRO_INT ((uint32_t)0x00000020) /*!< received overrun error interrupt */
#define SDIO_CMDRSPCMPL_INT ((uint32_t)0x00000040) /*!< command response received interrupt */
#define SDIO_CMDCMPL_INT ((uint32_t)0x00000080) /*!< command sent interrupt */
#define SDIO_DTCMP_INT ((uint32_t)0x00000100) /*!< data sent interrupt */
#define SDIO_SBITERR_INT ((uint32_t)0x00000200) /*!< start bit not detected on data bus interrupt */
#define SDIO_DTBLKCMPL_INT ((uint32_t)0x00000400) /*!< data block sent/received interrupt */
#define SDIO_DOCMD_INT ((uint32_t)0x00000800) /*!< command transfer in progress interrupt */
#define SDIO_DOTX_INT ((uint32_t)0x00001000) /*!< data transmit in progress interrupt */
#define SDIO_DORX_INT ((uint32_t)0x00002000) /*!< data receive in progress interrupt */
#define SDIO_TXBUFH_INT ((uint32_t)0x00004000) /*!< transmit buf half empty interrupt */
#define SDIO_RXBUFH_INT ((uint32_t)0x00008000) /*!< receive buf half full interrupt */
#define SDIO_TXBUFF_INT ((uint32_t)0x00010000) /*!< transmit buf full interrupt */
#define SDIO_RXBUFF_INT ((uint32_t)0x00020000) /*!< receive buf full interrupt */
#define SDIO_TXBUFE_INT ((uint32_t)0x00040000) /*!< transmit buf empty interrupt */
#define SDIO_RXBUFE_INT ((uint32_t)0x00080000) /*!< receive buf empty interrupt */
#define SDIO_TXBUF_INT ((uint32_t)0x00100000) /*!< data available in transmit interrupt */
#define SDIO_RXBUF_INT ((uint32_t)0x00200000) /*!< data available in receive interrupt */
#define SDIO_SDIOIF_INT ((uint32_t)0x00400000) /*!< sdio interface received interrupt */
/**
* @}
*/
/** @defgroup SDIO_flags_definition
* @brief sdio flag
* @{
*/
#define SDIO_CMDFAIL_FLAG ((uint32_t)0x00000001) /*!< command response received check failed flag */
#define SDIO_DTFAIL_FLAG ((uint32_t)0x00000002) /*!< data block sent/received check failed flag */
#define SDIO_CMDTIMEOUT_FLAG ((uint32_t)0x00000004) /*!< command response timerout flag */
#define SDIO_DTTIMEOUT_FLAG ((uint32_t)0x00000008) /*!< data timeout flag */
#define SDIO_TXERRU_FLAG ((uint32_t)0x00000010) /*!< transmit underrun error flag */
#define SDIO_RXERRO_FLAG ((uint32_t)0x00000020) /*!< received overrun error flag */
#define SDIO_CMDRSPCMPL_FLAG ((uint32_t)0x00000040) /*!< command response received flag */
#define SDIO_CMDCMPL_FLAG ((uint32_t)0x00000080) /*!< command sent flag */
#define SDIO_DTCMPL_FLAG ((uint32_t)0x00000100) /*!< data sent flag */
#define SDIO_SBITERR_FLAG ((uint32_t)0x00000200) /*!< start bit not detected on data bus flag */
#define SDIO_DTBLKCMPL_FLAG ((uint32_t)0x00000400) /*!< data block sent/received flag */
#define SDIO_DOCMD_FLAG ((uint32_t)0x00000800) /*!< command transfer in progress flag */
#define SDIO_DOTX_FLAG ((uint32_t)0x00001000) /*!< data transmit in progress flag */
#define SDIO_DORX_FLAG ((uint32_t)0x00002000) /*!< data receive in progress flag */
#define SDIO_TXBUFH_FLAG ((uint32_t)0x00004000) /*!< transmit buf half empty flag */
#define SDIO_RXBUFH_FLAG ((uint32_t)0x00008000) /*!< receive buf half full flag */
#define SDIO_TXBUFF_FLAG ((uint32_t)0x00010000) /*!< transmit buf full flag */
#define SDIO_RXBUFF_FLAG ((uint32_t)0x00020000) /*!< receive buf full flag */
#define SDIO_TXBUFE_FLAG ((uint32_t)0x00040000) /*!< transmit buf empty flag */
#define SDIO_RXBUFE_FLAG ((uint32_t)0x00080000) /*!< receive buf empty flag */
#define SDIO_TXBUF_FLAG ((uint32_t)0x00100000) /*!< data available in transmit flag */
#define SDIO_RXBUF_FLAG ((uint32_t)0x00200000) /*!< data available in receive flag */
#define SDIO_SDIOIF_FLAG ((uint32_t)0x00400000) /*!< sdio interface received flag */
/**
* @}
*/
/** @defgroup SDIO_exported_types
* @{
*/
/**
* @brief sdio power state
*/
typedef enum
{
SDIO_POWER_OFF = 0x00, /*!< power-off, clock to card is stopped */
SDIO_POWER_ON = 0x03 /*!< power-on, the card is clocked */
} sdio_power_state_type;
/**
* @brief sdio edge phase
*/
typedef enum
{
SDIO_CLOCK_EDGE_RISING = 0x00, /*!< sdio bus clock generated on the rising edge of the master clock */
SDIO_CLOCK_EDGE_FALLING = 0x01 /*!< sdio bus clock generated on the falling edge of the master clock */
} sdio_edge_phase_type;
/**
* @brief sdio bus width
*/
typedef enum
{
SDIO_BUS_WIDTH_D1 = 0x00, /*!< sdio wide bus select 1-bit */
SDIO_BUS_WIDTH_D4 = 0x01, /*!< sdio wide bus select 4-bit */
SDIO_BUS_WIDTH_D8 = 0x02 /*!< sdio wide bus select 8-bit */
} sdio_bus_width_type;
/**
* @brief sdio response type
*/
typedef enum
{
SDIO_RESPONSE_NO = 0x00, /*!< no response */
SDIO_RESPONSE_SHORT = 0x01, /*!< short response */
SDIO_RESPONSE_LONG = 0x03 /*!< long response */
} sdio_reponse_type;
/**
* @brief sdio wait type
*/
typedef enum
{
SDIO_WAIT_FOR_NO = 0x00, /*!< no wait */
SDIO_WAIT_FOR_INT = 0x01, /*!< wait interrupt request */
SDIO_WAIT_FOR_PEND = 0x02 /*!< wait end of transfer */
} sdio_wait_type;
/**
* @brief sdio response register index
*/
typedef enum
{
SDIO_RSP1_INDEX = 0x00, /*!< response index 1, corresponding to sdio_rsp register 1 */
SDIO_RSP2_INDEX = 0x01, /*!< response index 2, corresponding to sdio_rsp register 2 */
SDIO_RSP3_INDEX = 0x02, /*!< response index 3, corresponding to sdio_rsp register 3 */
SDIO_RSP4_INDEX = 0x03 /*!< response index 4, corresponding to sdio_rsp register 4 */
} sdio_rsp_index_type;
/**
* @brief sdio data block size
*/
typedef enum
{
SDIO_DATA_BLOCK_SIZE_1B = 0x00, /*!< data block size 1 byte */
SDIO_DATA_BLOCK_SIZE_2B = 0x01, /*!< data block size 2 bytes */
SDIO_DATA_BLOCK_SIZE_4B = 0x02, /*!< data block size 4 bytes */
SDIO_DATA_BLOCK_SIZE_8B = 0x03, /*!< data block size 8 bytes */
SDIO_DATA_BLOCK_SIZE_16B = 0x04, /*!< data block size 16 bytes */
SDIO_DATA_BLOCK_SIZE_32B = 0x05, /*!< data block size 32 bytes */
SDIO_DATA_BLOCK_SIZE_64B = 0x06, /*!< data block size 64 bytes */
SDIO_DATA_BLOCK_SIZE_128B = 0x07, /*!< data block size 128 bytes */
SDIO_DATA_BLOCK_SIZE_256B = 0x08, /*!< data block size 256 bytes */
SDIO_DATA_BLOCK_SIZE_512B = 0x09, /*!< data block size 512 bytes */
SDIO_DATA_BLOCK_SIZE_1024B = 0x0A, /*!< data block size 1024 bytes */
SDIO_DATA_BLOCK_SIZE_2048B = 0x0B, /*!< data block size 2048 bytes */
SDIO_DATA_BLOCK_SIZE_4096B = 0x0C, /*!< data block size 4096 bytes */
SDIO_DATA_BLOCK_SIZE_8192B = 0x0D, /*!< data block size 8192 bytes */
SDIO_DATA_BLOCK_SIZE_16384B = 0x0E /*!< data block size 16384 bytes */
} sdio_block_size_type;
/**
* @brief sdio data transfer mode
*/
typedef enum
{
SDIO_DATA_BLOCK_TRANSFER = 0x00, /*!< the sdio block transfer mode */
SDIO_DATA_STREAM_TRANSFER = 0x01 /*!< the sdio stream transfer mode */
} sdio_transfer_mode_type;
/**
* @brief sdio data transfer direction
*/
typedef enum
{
SDIO_DATA_TRANSFER_TO_CARD = 0x00, /*!< the sdio controller write */
SDIO_DATA_TRANSFER_TO_CONTROLLER = 0x01 /*!< the sdio controller read */
} sdio_transfer_direction_type;
/**
* @brief sdio read wait mode
*/
typedef enum
{
SDIO_READ_WAIT_CONTROLLED_BY_D2 = 0x00, /*!< the sdio read wait on data2 line */
SDIO_READ_WAIT_CONTROLLED_BY_CK = 0x01 /*!< the sdio read wait on clock line */
} sdio_read_wait_mode_type;
/**
* @brief sdio command structure
*/
typedef struct
{
uint32_t argument; /*!< the sdio command argument is sent to a card as part of command message */
uint8_t cmd_index; /*!< the sdio command index */
sdio_reponse_type rsp_type; /*!< the sdio response type */
sdio_wait_type wait_type; /*!< the sdio wait for interrupt request is enabled or disable */
} sdio_command_struct_type;
/**
* @brief sdio data structure
*/
typedef struct
{
uint32_t timeout; /*!< the sdio data timeout period in car bus clock periods */
uint32_t data_length; /*!< the sdio data length */
sdio_block_size_type block_size; /*!< the sdio data block size of block transfer mode */
sdio_transfer_mode_type transfer_mode; /*!< the sdio transfer mode, block or stream */
sdio_transfer_direction_type transfer_direction; /*!< the sdio data transfer direction */
} sdio_data_struct_type;
/**
* @brief type define sdio register all
*/
typedef struct
{
/**
* @brief sdio pwrctrl register, offset:0x00
*/
union
{
__IO uint32_t pwrctrl;
struct
{
__IO uint32_t ps : 2; /* [1:0] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} pwrctrl_bit;
};
/**
* @brief sdio clkctrl register, offset:0x04
*/
union
{
__IO uint32_t clkctrl;
struct
{
__IO uint32_t clkdiv_l : 8; /* [7:0] */
__IO uint32_t clkoen : 1; /* [8] */
__IO uint32_t pwrsven : 1; /* [9] */
__IO uint32_t bypsen : 1; /* [10] */
__IO uint32_t busws : 2; /* [12:11] */
__IO uint32_t clkegs : 1; /* [13] */
__IO uint32_t hfcen : 1; /* [14] */
__IO uint32_t clkdiv_h : 2; /* [16:15] */
__IO uint32_t reserved1 : 15;/* [31:17] */
} clkctrl_bit;
};
/**
* @brief sdio argu register, offset:0x08
*/
union
{
__IO uint32_t argu;
struct
{
__IO uint32_t argu : 32;/* [31:0] */
} argu_bit;
};
/**
* @brief sdio cmdctrl register, offset:0x0C
*/
union
{
__IO uint32_t cmdctrl;
struct
{
__IO uint32_t cmdidx : 6; /* [5:0] */
__IO uint32_t rspwt : 2; /* [7:6] */
__IO uint32_t intwt : 1; /* [8] */
__IO uint32_t pndwt : 1; /* [9] */
__IO uint32_t ccsmen : 1; /* [10] */
__IO uint32_t iosusp : 1; /* [11] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} cmdctrl_bit;
};
/**
* @brief sdio rspcmd register, offset:0x10
*/
union
{
__IO uint32_t rspcmd;
struct
{
__IO uint32_t rspcmd : 6; /* [5:0] */
__IO uint32_t reserved1 : 26;/* [31:6] */
} rspcmd_bit;
};
/**
* @brief sdio rsp1 register, offset:0x14
*/
union
{
__IO uint32_t rsp1;
struct
{
__IO uint32_t cardsts1 : 32;/* [31:0] */
} rsp1_bit;
};
/**
* @brief sdio rsp2 register, offset:0x18
*/
union
{
__IO uint32_t rsp2;
struct
{
__IO uint32_t cardsts2 : 32;/* [31:0] */
} rsp2_bit;
};
/**
* @brief sdio rsp3 register, offset:0x1C
*/
union
{
__IO uint32_t rsp3;
struct
{
__IO uint32_t cardsts3 : 32;/* [31:0] */
} rsp3_bit;
};
/**
* @brief sdio rsp4 register, offset:0x20
*/
union
{
__IO uint32_t rsp4;
struct
{
__IO uint32_t cardsts4 : 32;/* [31:0] */
} rsp4_bit;
};
/**
* @brief sdio dttmr register, offset:0x24
*/
union
{
__IO uint32_t dttmr;
struct
{
__IO uint32_t timeout : 32;/* [31:0] */
} dttmr_bit;
};
/**
* @brief sdio dtlen register, offset:0x28
*/
union
{
__IO uint32_t dtlen;
struct
{
__IO uint32_t dtlen : 25;/* [24:0] */
__IO uint32_t reserved1 : 7; /* [31:25] */
} dtlen_bit;
};
/**
* @brief sdio dtctrl register, offset:0x2C
*/
union
{
__IO uint32_t dtctrl;
struct
{
__IO uint32_t tfren : 1; /* [0] */
__IO uint32_t tfrdir : 1; /* [1] */
__IO uint32_t tfrmode : 1; /* [2] */
__IO uint32_t dmaen : 1; /* [3] */
__IO uint32_t blksize : 4; /* [7:4] */
__IO uint32_t rdwtstart : 1; /* [8] */
__IO uint32_t rdwtstop : 1; /* [9] */
__IO uint32_t rdwtmode : 1; /* [10] */
__IO uint32_t ioen : 1; /* [11] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} dtctrl_bit;
};
/**
* @brief sdio dtcnt register, offset:0x30
*/
union
{
__IO uint32_t dtcnt;
struct
{
__IO uint32_t cnt : 25;/* [24:0] */
__IO uint32_t reserved1 : 7; /* [31:25] */
} dtcnt_bit;
};
/**
* @brief sdio sts register, offset:0x34
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t cmdfail : 1; /* [0] */
__IO uint32_t dtfail : 1; /* [1] */
__IO uint32_t cmdtimeout : 1; /* [2] */
__IO uint32_t dttimeout : 1; /* [3] */
__IO uint32_t txerru : 1; /* [4] */
__IO uint32_t rxerro : 1; /* [5] */
__IO uint32_t cmdrspcmpl : 1; /* [6] */
__IO uint32_t cmdcmpl : 1; /* [7] */
__IO uint32_t dtcmpl : 1; /* [8] */
__IO uint32_t sbiterr : 1; /* [9] */
__IO uint32_t dtblkcmpl : 1; /* [10] */
__IO uint32_t docmd : 1; /* [11] */
__IO uint32_t dotx : 1; /* [12] */
__IO uint32_t dorx : 1; /* [13] */
__IO uint32_t txbufh : 1; /* [14] */
__IO uint32_t rxbufh : 1; /* [15] */
__IO uint32_t txbuff : 1; /* [16] */
__IO uint32_t rxbuff : 1; /* [17] */
__IO uint32_t txbufe : 1; /* [18] */
__IO uint32_t rxbufe : 1; /* [19] */
__IO uint32_t txbuf : 1; /* [20] */
__IO uint32_t rxbuf : 1; /* [21] */
__IO uint32_t ioif : 1; /* [22] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} sts_bit;
};
/**
* @brief sdio intclr register, offset:0x38
*/
union
{
__IO uint32_t intclr;
struct
{
__IO uint32_t cmdfail : 1; /* [0] */
__IO uint32_t dtfail : 1; /* [1] */
__IO uint32_t cmdtimeout : 1; /* [2] */
__IO uint32_t dttimeout : 1; /* [3] */
__IO uint32_t txerru : 1; /* [4] */
__IO uint32_t rxerro : 1; /* [5] */
__IO uint32_t cmdrspcmpl : 1; /* [6] */
__IO uint32_t cmdcmpl : 1; /* [7] */
__IO uint32_t dtcmpl : 1; /* [8] */
__IO uint32_t sbiterr : 1; /* [9] */
__IO uint32_t dtblkcmpl : 1; /* [10] */
__IO uint32_t reserved1 : 11;/* [21:11] */
__IO uint32_t ioif : 1; /* [22] */
__IO uint32_t reserved2 : 9; /* [31:23] */
} intclr_bit;
};
/**
* @brief sdio inten register, offset:0x3C
*/
union
{
__IO uint32_t inten;
struct
{
__IO uint32_t cmdfailien : 1; /* [0] */
__IO uint32_t dtfailien : 1; /* [1] */
__IO uint32_t cmdtimeoutien : 1; /* [2] */
__IO uint32_t dttimeoutien : 1; /* [3] */
__IO uint32_t txerruien : 1; /* [4] */
__IO uint32_t rxerroien : 1; /* [5] */
__IO uint32_t cmdrspcmplien : 1; /* [6] */
__IO uint32_t cmdcmplien : 1; /* [7] */
__IO uint32_t dtcmplien : 1; /* [8] */
__IO uint32_t sbiterrien : 1; /* [9] */
__IO uint32_t dtblkcmplien : 1; /* [10] */
__IO uint32_t docmdien : 1; /* [11] */
__IO uint32_t dotxien : 1; /* [12] */
__IO uint32_t dorxien : 1; /* [13] */
__IO uint32_t txbufhien : 1; /* [14] */
__IO uint32_t rxbufhien : 1; /* [15] */
__IO uint32_t txbuffien : 1; /* [16] */
__IO uint32_t rxbuffien : 1; /* [17] */
__IO uint32_t txbufeien : 1; /* [18] */
__IO uint32_t rxbufeien : 1; /* [19] */
__IO uint32_t txbufien : 1; /* [20] */
__IO uint32_t rxbufien : 1; /* [21] */
__IO uint32_t ioifien : 1; /* [22] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} inten_bit;
};
/**
* @brief sdio reserved1 register, offset:0x40~0x44
*/
__IO uint32_t reserved1[2];
/**
* @brief sdio bufcnt register, offset:0x48
*/
union
{
__IO uint32_t bufcnt;
struct
{
__IO uint32_t cnt : 24;/* [23:0] */
__IO uint32_t reserved1 : 8; /* [31:24] */
} bufcnt_bit;
};
/**
* @brief sdio reserved2 register, offset:0x4C~0x7C
*/
__IO uint32_t reserved2[13];
/**
* @brief sdio buf register, offset:0x80
*/
union
{
__IO uint32_t buf;
struct
{
__IO uint32_t dt : 32;/* [31:0] */
} buf_bit;
};
} sdio_type;
/**
* @}
*/
#if defined (AT32F403ARx) || defined (AT32F403AVx) || defined (AT32F407Rx) || \
defined (AT32F407Vx)
#define SDIO1 ((sdio_type *) SDIO1_BASE)
#endif
#define SDIO2 ((sdio_type *) SDIO2_BASE)
/** @defgroup SDIO_exported_functions
* @{
*/
void sdio_reset(sdio_type *sdio_x);
void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x);
void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state);
flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag);
void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
uint8_t sdio_command_response_get(sdio_type *sdio_x);
uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
uint32_t sdio_data_counter_get(sdio_type *sdio_x);
uint32_t sdio_data_read(sdio_type *sdio_x);
uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
void sdio_data_write(sdio_type *sdio_x, uint32_t data);
void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f403a_407_spi.h
* @brief at32f403a_407 spi header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F403A_407_SPI_H
#define __AT32F403A_407_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f403a_407.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/**
* @defgroup SPI_I2S_flags_definition
* @brief spi i2s flag
* @{
*/
#define SPI_I2S_RDBF_FLAG 0x0001 /*!< spi or i2s receive data buffer full flag */
#define SPI_I2S_TDBE_FLAG 0x0002 /*!< spi or i2s transmit data buffer empty flag */
#define I2S_ACS_FLAG 0x0004 /*!< i2s audio channel state flag */
#define I2S_TUERR_FLAG 0x0008 /*!< i2s transmitter underload error flag */
#define SPI_CCERR_FLAG 0x0010 /*!< spi crc calculation error flag */
#define SPI_MMERR_FLAG 0x0020 /*!< spi master mode error flag */
#define SPI_I2S_ROERR_FLAG 0x0040 /*!< spi or i2s receiver overflow error flag */
#define SPI_I2S_BF_FLAG 0x0080 /*!< spi or i2s busy flag */
/**
* @}
*/
/**
* @defgroup SPI_I2S_interrupts_definition
* @brief spi i2s interrupt
* @{
*/
#define SPI_I2S_ERROR_INT 0x0020 /*!< error interrupt */
#define SPI_I2S_RDBF_INT 0x0040 /*!< receive data buffer full interrupt */
#define SPI_I2S_TDBE_INT 0x0080 /*!< transmit data buffer empty interrupt */
/**
* @}
*/
/** @defgroup SPI_exported_types
* @{
*/
/**
* @brief spi frame bit num type
*/
typedef enum
{
SPI_FRAME_8BIT = 0x00, /*!< 8-bit data frame format */
SPI_FRAME_16BIT = 0x01 /*!< 16-bit data frame format */
} spi_frame_bit_num_type;
/**
* @brief spi master/slave mode type
*/
typedef enum
{
SPI_MODE_SLAVE = 0x00, /*!< select as slave mode */
SPI_MODE_MASTER = 0x01 /*!< select as master mode */
} spi_master_slave_mode_type;
/**
* @brief spi clock polarity (clkpol) type
*/
typedef enum
{
SPI_CLOCK_POLARITY_LOW = 0x00, /*!< sck keeps low at idle state */
SPI_CLOCK_POLARITY_HIGH = 0x01 /*!< sck keeps high at idle state */
} spi_clock_polarity_type;
/**
* @brief spi clock phase (clkpha) type
*/
typedef enum
{
SPI_CLOCK_PHASE_1EDGE = 0x00, /*!< data capture start from the first clock edge */
SPI_CLOCK_PHASE_2EDGE = 0x01 /*!< data capture start from the second clock edge */
} spi_clock_phase_type;
/**
* @brief spi cs mode type
*/
typedef enum
{
SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is hardware mode */
SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is software mode */
} spi_cs_mode_type;
/**
* @brief spi master clock frequency division type
*/
typedef enum
{
SPI_MCLK_DIV_2 = 0x00, /*!< master clock frequency division 2 */
SPI_MCLK_DIV_4 = 0x01, /*!< master clock frequency division 4 */
SPI_MCLK_DIV_8 = 0x02, /*!< master clock frequency division 8 */
SPI_MCLK_DIV_16 = 0x03, /*!< master clock frequency division 16 */
SPI_MCLK_DIV_32 = 0x04, /*!< master clock frequency division 32 */
SPI_MCLK_DIV_64 = 0x05, /*!< master clock frequency division 64 */
SPI_MCLK_DIV_128 = 0x06, /*!< master clock frequency division 128 */
SPI_MCLK_DIV_256 = 0x07, /*!< master clock frequency division 256 */
SPI_MCLK_DIV_512 = 0x08, /*!< master clock frequency division 512 */
SPI_MCLK_DIV_1024 = 0x09 /*!< master clock frequency division 1024 */
} spi_mclk_freq_div_type;
/**
* @brief spi transmit first bit (lsb/msb) type
*/
typedef enum
{
SPI_FIRST_BIT_MSB = 0x00, /*!< the frame format is msb first */
SPI_FIRST_BIT_LSB = 0x01 /*!< the frame format is lsb first */
} spi_first_bit_type;
/**
* @brief spi transmission mode type
*/
typedef enum
{
SPI_TRANSMIT_FULL_DUPLEX = 0x00, /*!< dual line unidirectional full-duplex mode(slben = 0 and ora = 0) */
SPI_TRANSMIT_SIMPLEX_RX = 0x01, /*!< dual line unidirectional simplex receive-only mode(slben = 0 and ora = 1) */
SPI_TRANSMIT_HALF_DUPLEX_RX = 0x02, /*!< single line bidirectional half duplex mode-receiving(slben = 1 and slbtd = 0) */
SPI_TRANSMIT_HALF_DUPLEX_TX = 0x03 /*!< single line bidirectional half duplex mode-transmitting(slben = 1 and slbtd = 1) */
} spi_transmission_mode_type;
/**
* @brief spi crc direction type
*/
typedef enum
{
SPI_CRC_RX = 0x0014, /*!< crc direction is rx */
SPI_CRC_TX = 0x0018 /*!< crc direction is tx */
} spi_crc_direction_type;
/**
* @brief spi single line bidirectional direction type
*/
typedef enum
{
SPI_HALF_DUPLEX_DIRECTION_RX = 0x00, /*!< single line bidirectional half duplex mode direction: receive(slbtd = 0) */
SPI_HALF_DUPLEX_DIRECTION_TX = 0x01 /*!< single line bidirectional half duplex mode direction: transmit(slbtd = 1) */
} spi_half_duplex_direction_type;
/**
* @brief spi software cs internal level type
*/
typedef enum
{
SPI_SWCS_INTERNAL_LEVEL_LOW = 0x00, /*!< internal level low */
SPI_SWCS_INTERNAL_LEVEL_HIGHT = 0x01 /*!< internal level high */
} spi_software_cs_level_type;
/**
* @brief i2s audio protocol type
*/
typedef enum
{
I2S_AUDIO_PROTOCOL_PHILLIPS = 0x00, /*!< i2s philip standard */
I2S_AUDIO_PROTOCOL_MSB = 0x01, /*!< msb-justified standard */
I2S_AUDIO_PROTOCOL_LSB = 0x02, /*!< lsb-justified standard */
I2S_AUDIO_PROTOCOL_PCM_SHORT = 0x03, /*!< pcm standard-short frame */
I2S_AUDIO_PROTOCOL_PCM_LONG = 0x04 /*!< pcm standard-long frame */
} i2s_audio_protocol_type;
/**
* @brief i2s audio frequency type
*/
typedef enum
{
I2S_AUDIO_FREQUENCY_DEFAULT = 2, /*!< i2s audio sampling frequency default */
I2S_AUDIO_FREQUENCY_8K = 8000, /*!< i2s audio sampling frequency 8k */
I2S_AUDIO_FREQUENCY_11_025K = 11025, /*!< i2s audio sampling frequency 11.025k */
I2S_AUDIO_FREQUENCY_16K = 16000, /*!< i2s audio sampling frequency 16k */
I2S_AUDIO_FREQUENCY_22_05K = 22050, /*!< i2s audio sampling frequency 22.05k */
I2S_AUDIO_FREQUENCY_32K = 32000, /*!< i2s audio sampling frequency 32k */
I2S_AUDIO_FREQUENCY_44_1K = 44100, /*!< i2s audio sampling frequency 44.1k */
I2S_AUDIO_FREQUENCY_48K = 48000, /*!< i2s audio sampling frequency 48k */
I2S_AUDIO_FREQUENCY_96K = 96000, /*!< i2s audio sampling frequency 96k */
I2S_AUDIO_FREQUENCY_192K = 192000 /*!< i2s audio sampling frequency 192k */
} i2s_audio_sampling_freq_type;
/**
* @brief i2s data bit num and channel bit num type
*/
typedef enum
{
I2S_DATA_16BIT_CHANNEL_16BIT = 0x01, /*!< 16-bit data packed in 16-bit channel frame */
I2S_DATA_16BIT_CHANNEL_32BIT = 0x02, /*!< 16-bit data packed in 32-bit channel frame */
I2S_DATA_24BIT_CHANNEL_32BIT = 0x03, /*!< 24-bit data packed in 32-bit channel frame */
I2S_DATA_32BIT_CHANNEL_32BIT = 0x04 /*!< 32-bit data packed in 32-bit channel frame */
} i2s_data_channel_format_type;
/**
* @brief i2s operation mode type
*/
typedef enum
{
I2S_MODE_SLAVE_TX = 0x00, /*!< slave transmission mode */
I2S_MODE_SLAVE_RX = 0x01, /*!< slave reception mode */
I2S_MODE_MASTER_TX = 0x02, /*!< master transmission mode */
I2S_MODE_MASTER_RX = 0x03 /*!< master reception mode */
} i2s_operation_mode_type;
/**
* @brief i2s clock polarity type
*/
typedef enum
{
I2S_CLOCK_POLARITY_LOW = 0x00, /*!< i2s clock steady state is low level */
I2S_CLOCK_POLARITY_HIGH = 0x01 /*!< i2s clock steady state is high level */
} i2s_clock_polarity_type;
/**
* @brief spi init type
*/
typedef struct
{
spi_transmission_mode_type transmission_mode; /*!< transmission mode selection */
spi_master_slave_mode_type master_slave_mode; /*!< master or slave mode selection */
spi_mclk_freq_div_type mclk_freq_division; /*!< master clock frequency division selection */
spi_first_bit_type first_bit_transmission;/*!< transmit lsb or msb selection */
spi_frame_bit_num_type frame_bit_num; /*!< frame bit num 8 or 16 bit selection */
spi_clock_polarity_type clock_polarity; /*!< clock polarity selection */
spi_clock_phase_type clock_phase; /*!< clock phase selection */
spi_cs_mode_type cs_mode_selection; /*!< hardware or software cs mode selection */
} spi_init_type;
/**
* @brief i2s init type
*/
typedef struct
{
i2s_operation_mode_type operation_mode; /*!< operation mode selection */
i2s_audio_protocol_type audio_protocol; /*!< audio protocol selection */
i2s_audio_sampling_freq_type audio_sampling_freq; /*!< audio frequency selection */
i2s_data_channel_format_type data_channel_format; /*!< data bit num and channel bit num selection */
i2s_clock_polarity_type clock_polarity; /*!< clock polarity selection */
confirm_state mclk_output_enable; /*!< mclk_output selection */
} i2s_init_type;
/**
* @brief type define spi register all
*/
typedef struct
{
/**
* @brief spi ctrl1 register, offset:0x00
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t clkpha : 1; /* [0] */
__IO uint32_t clkpol : 1; /* [1] */
__IO uint32_t msten : 1; /* [2] */
__IO uint32_t mdiv_l : 3; /* [5:3] */
__IO uint32_t spien : 1; /* [6] */
__IO uint32_t ltf : 1; /* [7] */
__IO uint32_t swcsil : 1; /* [8] */
__IO uint32_t swcsen : 1; /* [9] */
__IO uint32_t ora : 1; /* [10] */
__IO uint32_t fbn : 1; /* [11] */
__IO uint32_t ntc : 1; /* [12] */
__IO uint32_t ccen : 1; /* [13] */
__IO uint32_t slbtd : 1; /* [14] */
__IO uint32_t slben : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} ctrl1_bit;
};
/**
* @brief spi ctrl2 register, offset:0x04
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t dmaren : 1; /* [0] */
__IO uint32_t dmaten : 1; /* [1] */
__IO uint32_t hwcsoe : 1; /* [2] */
__IO uint32_t reserved1 : 2; /* [4:3] */
__IO uint32_t errie : 1; /* [5] */
__IO uint32_t rdbfie : 1; /* [6] */
__IO uint32_t tdbeie : 1; /* [7] */
__IO uint32_t mdiv_h : 1; /* [8] */
__IO uint32_t reserved2 : 23;/* [31:9] */
} ctrl2_bit;
};
/**
* @brief spi sts register, offset:0x08
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t rdbf : 1; /* [0] */
__IO uint32_t tdbe : 1; /* [1] */
__IO uint32_t acs : 1; /* [2] */
__IO uint32_t tuerr : 1; /* [3] */
__IO uint32_t ccerr : 1; /* [4] */
__IO uint32_t mmerr : 1; /* [5] */
__IO uint32_t roerr : 1; /* [6] */
__IO uint32_t bf : 1; /* [7] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} sts_bit;
};
/**
* @brief spi dt register, offset:0x0C
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} dt_bit;
};
/**
* @brief spi cpoly register, offset:0x10
*/
union
{
__IO uint32_t cpoly;
struct
{
__IO uint32_t cpoly : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cpoly_bit;
};
/**
* @brief spi rcrc register, offset:0x14
*/
union
{
__IO uint32_t rcrc;
struct
{
__IO uint32_t rcrc : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} rcrc_bit;
};
/**
* @brief spi tcrc register, offset:0x18
*/
union
{
__IO uint32_t tcrc;
struct
{
__IO uint32_t tcrc : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} tcrc_bit;
};
/**
* @brief spi i2sctrl register, offset:0x1C
*/
union
{
__IO uint32_t i2sctrl;
struct
{
__IO uint32_t i2scbn : 1; /* [0] */
__IO uint32_t i2sdbn : 2; /* [2:1] */
__IO uint32_t i2sclkpol : 1; /* [3] */
__IO uint32_t stdsel : 2; /* [5:4] */
__IO uint32_t reserved1 : 1; /* [6] */
__IO uint32_t pcmfssel : 1; /* [7] */
__IO uint32_t opersel : 2; /* [9:8] */
__IO uint32_t i2sen : 1; /* [10] */
__IO uint32_t i2smsel : 1; /* [11] */
__IO uint32_t reserved2 : 20;/* [31:12] */
} i2sctrl_bit;
};
/**
* @brief spi i2sclk register, offset:0x20
*/
union
{
__IO uint32_t i2sclk;
struct
{
__IO uint32_t i2sdiv_l : 8; /* [7:0] */
__IO uint32_t i2sodd : 1; /* [8] */
__IO uint32_t i2smclkoe : 1; /* [9] */
__IO uint32_t i2sdiv_h : 2; /* [11:10] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} i2sclk_bit;
};
} spi_type;
/**
* @}
*/
#define SPI1 ((spi_type *) SPI1_BASE)
#define SPI2 ((spi_type *) SPI2_BASE)
#define SPI3 ((spi_type *) SPI3_BASE)
#define SPI4 ((spi_type *) SPI4_BASE)
#define I2S2EXT ((spi_type *) I2S2EXT_BASE)
#define I2S3EXT ((spi_type *) I2S3EXT_BASE)
/** @defgroup SPI_exported_functions
* @{
*/
void spi_i2s_reset(spi_type *spi_x);
void spi_default_para_init(spi_init_type* spi_init_struct);
void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
void spi_crc_next_transmit(spi_type* spi_x);
void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
uint16_t spi_crc_polynomial_get(spi_type* spi_x);
void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
void spi_enable(spi_type* spi_x, confirm_state new_state);
void i2s_default_para_init(i2s_init_type* i2s_init_struct);
void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
void i2s_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
uint16_t spi_i2s_data_receive(spi_type* spi_x);
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f403a_407_usb.h
* @brief at32f403a_407 usb header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @addtogroup USB
* @{
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F403A_407_USB_H
#define __AT32F403A_407_USB_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f403a_407.h"
/** @defgroup USB_interrupts_definition
* @brief usb interrupt mask
* @{
*/
#define USB_LSOF_INT ((uint32_t)0x00000100) /*!< usb lost sof interrupt */
#define USB_SOF_INT ((uint32_t)0x00000200) /*!< usb sof interrupt */
#define USB_RST_INT ((uint32_t)0x00000400) /*!< usb reset interrupt */
#define USB_SP_INT ((uint32_t)0x00000800) /*!< usb suspend interrupt */
#define USB_WK_INT ((uint32_t)0x00001000) /*!< usb wakeup interrupt */
#define USB_BE_INT ((uint32_t)0x00002000) /*!< usb bus error interrupt */
#define USB_UCFOR_INT ((uint32_t)0x00004000) /*!< usb core fifo overrun interrupt */
#define USB_TC_INT ((uint32_t)0x00008000) /*!< usb transmission completed interrupt */
/**
* @}
*/
/** @defgroup USB_interrupt_flags_definition
* @brief usb interrupt flag
* @{
*/
#define USB_EPT_NUM_FLAG ((uint32_t)0x0000000F) /*!< usb endpoint number */
#define USB_INOUT_FLAG ((uint32_t)0x00000010) /*!< usb in/out transcation flag */
#define USB_LSOF_FLAG ((uint32_t)0x00000100) /*!< usb lost sof flag */
#define USB_SOF_FLAG ((uint32_t)0x00000200) /*!< usb sof flag */
#define USB_RST_FLAG ((uint32_t)0x00000400) /*!< usb reset flag */
#define USB_SP_FLAG ((uint32_t)0x00000800) /*!< usb suspend flag */
#define USB_WK_FLAG ((uint32_t)0x00001000) /*!< usb wakeup flag */
#define USB_BE_FLAG ((uint32_t)0x00002000) /*!< usb bus error flag */
#define USB_UCFOR_FLAG ((uint32_t)0x00004000) /*!< usb core fifo overrun flag */
#define USB_TC_FLAG ((uint32_t)0x00008000) /*!< usb transmission completed flag */
/**
* @}
*/
/** @defgroup USB_endpoint_register_bit_definition
* @brief usb endpoint register bit define
* @{
*/
#define USB_EPTADDR ((uint32_t)0x0000000F) /*!< usb endpoint address */
#define USB_TXSTS ((uint32_t)0x00000030) /*!< usb tx status */
#define USB_TXDTS ((uint32_t)0x00000040) /*!< usb tx data toggle synchronization */
#define USB_TXTC ((uint32_t)0x00000080) /*!< usb tx transcation completed */
#define USB_EXF ((uint32_t)0x00000100) /*!< usb endpoint extend funtion */
#define USB_TRANS_TYPE ((uint32_t)0x00000600) /*!< usb transfer type */
#define USB_SETUPTC ((uint32_t)0x00000800) /*!< usb setup transcation completed */
#define USB_RXSTS ((uint32_t)0x00003000) /*!< usb rx status */
#define USB_RXDTS ((uint32_t)0x00004000) /*!< usb rx data toggle synchronization */
#define USB_RXTC ((uint32_t)0x00008000) /*!< usb rx transcation completed */
#define USB_EPT_BIT_MASK (uint32_t)(USB_TXTC | USB_SETUPTC | USB_EPTADDR | USB_EXF | USB_RXTC | USB_TRANS_TYPE) /*!< usb bit mask */
#define USB_TX_MASK (USB_TXSTS | USB_EPT_BIT_MASK) /*!< usb tx mask */
#define USB_RX_MASK (USB_RXSTS | USB_EPT_BIT_MASK) /*!< usb rx mask */
/**
* @}
*/
/** @defgroup USB_endpoint_tx_and_rx_status_definition
* @brief usb endpoint tx and rx status
* @{
*/
#define USB_TX_DISABLE ((uint32_t)0x00000000) /*!< usb tx status disable */
#define USB_TX_STALL ((uint32_t)0x00000010) /*!< usb tx status stall */
#define USB_TX_NAK ((uint32_t)0x00000020) /*!< usb tx status nak */
#define USB_TX_VALID ((uint32_t)0x00000030) /*!< usb tx status valid */
#define USB_TXDTS0 ((uint32_t)0x00000010) /*!< usb tx data toggle bit 0 */
#define USB_TXDTS1 ((uint32_t)0x00000020) /*!< usb tx data toggle bit 1 */
#define USB_RX_DISABLE ((uint32_t)0x00000000) /*!< usb rx status disable */
#define USB_RX_STALL ((uint32_t)0x00001000) /*!< usb rx status stall */
#define USB_RX_NAK ((uint32_t)0x00002000) /*!< usb rx status nak */
#define USB_RX_VALID ((uint32_t)0x00003000) /*!< usb rx status valid */
#define USB_RXDTS0 ((uint32_t)0x00001000) /*!< usb rx data toggle bit 0 */
#define USB_RXDTS1 ((uint32_t)0x00002000) /*!< usb rx data toggle bit 1 */
/**
* @}
*/
/** @defgroup USB_device_endpoint_register_type_definition
* @brief usb device endpoint register type define
* @{
*/
#define USB_EPT_CONTROL ((uint32_t)0x00000200) /*!< usb endpoint transfer type control */
#define USB_EPT_BULK ((uint32_t)0x00000000) /*!< usb endpoint transfer type bulk */
#define USB_EPT_INT ((uint32_t)0x00000600) /*!< usb endpoint transfer type interrupt */
#define USB_EPT_ISO ((uint32_t)0x00000400) /*!< usb endpoint transfer type iso */
/**
* @}
*/
/** @defgroup USB_buffer_table_default_offset_address_definition
* @brief usb buffer table default offset address
* @{
*/
#define USB_BUFFER_TABLE_ADDRESS 0x0000 /*!< usb buffer table address */
/**
* @}
*/
/** @defgroup USB_packet_buffer_start_address_definition
* @brief usb packet buffer start address
* @{
*/
#define USB_PACKET_BUFFER_ADDRESS 0x40006000 /*!< usb buffer address */
#define USB_PACKET_BUFFER_ADDRESS_EX 0x40007800 /*!< usb buffer extend address */
/**
* @}
*/
/** @defgroup USB_exported_enum_types
* @{
*/
/**
* @brief usb endpoint number define
*/
typedef enum
{
USB_EPT0 = 0x00, /*!< usb endpoint 0 */
USB_EPT1 = 0x01, /*!< usb endpoint 1 */
USB_EPT2 = 0x02, /*!< usb endpoint 2 */
USB_EPT3 = 0x03, /*!< usb endpoint 3 */
USB_EPT4 = 0x04, /*!< usb endpoint 4 */
USB_EPT5 = 0x05, /*!< usb endpoint 5 */
USB_EPT6 = 0x06, /*!< usb endpoint 6 */
USB_EPT7 = 0x07 /*!< usb endpoint 7 */
} usb_ept_number_type;
/**
* @brief usb endpoint max num define
*/
#ifndef USB_EPT_MAX_NUM
#define USB_EPT_MAX_NUM 8 /*!< usb device support endpoint number */
#endif
/**
* @brief endpoint transfer type define
*/
typedef enum
{
EPT_CONTROL_TYPE = 0x00, /*!< usb transfer type control */
EPT_ISO_TYPE = 0x01, /*!< usb transfer type iso */
EPT_BULK_TYPE = 0x02, /*!< usb transfer type bulk */
EPT_INT_TYPE = 0x03 /*!< usb transfer type interrupt */
}ept_trans_type;
/**
* @brief endpoint endpoint direction define
*/
typedef enum
{
EPT_IN = 0x00, /*!< usb endpoint direction in */
EPT_OUT = 0x01 /*!< usb endpoint direction out */
}ept_inout_type;
/**
* @brief data transfer direction
*/
typedef enum
{
DATA_TRANS_OUT = 0x00, /*!< usb data transfer direction out */
DATA_TRANS_IN = 0x01 /*!< usb data transfer direction in */
}data_trans_dir;
/**
* @brief usb clock select
*/
typedef enum
{
USB_CLK_HICK,
USB_CLK_HEXT
}usb_clk48_s;
/**
* @}
*/
/** @defgroup USB_macro_definition
* @{
*/
/**
* @brief set usb endpoint tx status
* @param ept_num: endpoint number
* @param new_sts: the new tx status of this endpoint number
* @retval none
*/
#define USB_SET_TXSTS(ept_num, new_sts) { \
register uint16_t epsts = (USB->ept[ept_num]) & USB_TX_MASK; \
if((new_sts & USB_TXDTS0) != 0) \
epsts ^= USB_TXDTS0; \
if((new_sts & USB_TXDTS1) != 0) \
epsts ^= USB_TXDTS1; \
USB->ept[ept_num] = epsts | USB_RXTC | USB_TXTC; \
}
/**
* @brief set usb endpoint rx status
* @param ept_num: endpoint number
* @param new_sts: the new rx status of this endpoint number
* @retval none
*/
#define USB_SET_RXSTS(ept_num, new_sts) { \
register uint16_t epsts = (USB->ept[ept_num]) & USB_RX_MASK; \
if((new_sts & USB_RXDTS0) != 0) \
epsts ^= USB_RXDTS0; \
if((new_sts & USB_RXDTS1) != 0) \
epsts ^= USB_RXDTS1; \
USB->ept[ept_num] = epsts | USB_RXTC | USB_TXTC; \
}
/**
* @brief get usb endpoint tx/rx length address
* @param eptn: endpoint number
* @retval the length address of tx/rx
*/
#define GET_TX_LEN_ADDR(eptn) (uint32_t *)((USB->buftbl + eptn * 8 + 2) * 2 + g_usb_packet_address)
#define GET_RX_LEN_ADDR(eptn) (uint32_t *)((USB->buftbl + eptn * 8 + 6) * 2 + g_usb_packet_address)
/**
* @brief get usb endpoint tx/rx data length
* @param eptn: endpoint number
* @retval the length of tx/rx
*/
#define USB_GET_TX_LEN(eptn) ((uint16_t)(*GET_TX_LEN_ADDR(eptn)) & 0x3ff)
#define USB_GET_RX_LEN(eptn) ((uint16_t)(*GET_RX_LEN_ADDR(eptn)) & 0x3ff)
/**
* @brief double buffer mode get endpoint buf0/buf1 data length
* @param eptn: endpoint number
* @retval the length of buf0/buf1
*/
#define USB_DBUF0_GET_LEN(eptn) USB_GET_TX_LEN(eptn)
#define USB_DBUF1_GET_LEN(eptn) USB_GET_RX_LEN(eptn)
/**
* @brief set usb length of rx buffer
* @param reg: usb rx length register
* @param len: rx max length
* @param blks: number of blocks
*/
#define BLK32(reg, len, blks) { \
blks = (len) >> 5; \
if(((len) & 0x1F) == 0) \
blks --; \
*reg = ((uint16_t)((blks) << 10) | 0x8000); \
}
#define BLK2(reg, len, blks) { \
blks = (len) >> 1; \
if(((len) & 0x1) == 0) \
blks ++; \
*reg = (uint16_t)((blks) << 10); \
}
#define USB_SET_RXLEN_REG(reg, len) { \
uint16_t blks; \
if(len > 62) \
{ \
BLK32(reg, len, blks); \
} \
else \
{ \
BLK2(reg, len, blks); \
} \
}
/**
* @brief set endpoint tx/rx transfer length
* @param eptn: endpoint number
* @param len: transfer length
* @retval none
*/
#define USB_SET_TXLEN(eptn, len) (*(GET_TX_LEN_ADDR(eptn)) = (len))
#define USB_SET_RXLEN(eptn, len) { \
uint32_t *rx_reg = GET_RX_LEN_ADDR(eptn); \
USB_SET_RXLEN_REG(rx_reg, (len)); \
}
/**
* @brief double buffer mode set endpoint rx buf0 length
* @param eptn: endpoint number
* @param len: transfer length
* @retval none
*/
#define USB_OUT_EPT_DOUBLE_BUF0(eptn, len) { \
uint32_t *rx_reg = GET_TX_LEN_ADDR(eptn); \
USB_SET_RXLEN_REG(rx_reg, (len)); \
}
/**
* @brief double buffer mode set endpoint buf0 length
* @param eptn: endpoint number
* @param len: transfer length
* @param dir: transfer direction(in/out)
* @retval none
*/
#define USB_SET_EPT_DOUBLE_BUF0_LEN(eptn, len, dir) { \
if(dir == DATA_TRANS_OUT) \
{ \
USB_OUT_EPT_DOUBLE_BUF0(eptn, len); \
} \
else \
{ \
*(GET_TX_LEN_ADDR(eptn)) = (len); \
} \
}
/**
* @brief double buffer mode set endpoint buf1 length
* @param eptn: endpoint number
* @param len: transfer length
* @param dir: transfer direction(in/out)
* @retval none
*/
#define USB_SET_EPT_DOUBLE_BUF1_LEN(eptn, len, dir) { \
if(dir == DATA_TRANS_OUT) \
{ \
USB_SET_RXLEN(eptn, len); \
} \
else \
{ \
*(GET_RX_LEN_ADDR(eptn)) = (len); \
} \
}
/**
* @brief set usb endpoint tx/rx fifo address
* @param eptn: endpoint number
* @param address: offset of the fifo address
* @retval none
*/
#define USB_SET_TX_ADDRESS(eptn, address) (*(uint32_t *)((USB->buftbl + eptn * 8) * 2 + g_usb_packet_address) = address)
#define USB_SET_RX_ADDRESS(eptn, address) (*(uint32_t *)((USB->buftbl + eptn * 8 + 4) * 2 + g_usb_packet_address) = address)
/**
* @brief set double buffer mode usb endpoint buf0/buf1 fifo address
* @param eptn: endpoint number
* @param address: offset of the fifo address
* @retval none
*/
#define USB_SET_DOUBLE_BUFF0_ADDRESS(eptn, address) (USB_SET_TX_ADDRESS(eptn, address))
#define USB_SET_DOUBLE_BUFF1_ADDRESS(eptn, address) (USB_SET_RX_ADDRESS(eptn, address))
/**
* @brief set usb tx/rx toggle
* @param eptn: endpoint number
* @retval none
*/
#define USB_TOGGLE_TXDTS(eptn) (USB->ept[eptn] = ((USB->ept[eptn] & USB_EPT_BIT_MASK) | USB_TXDTS | USB_RXTC | USB_TXTC))
#define USB_TOGGLE_RXDTS(eptn) (USB->ept[eptn] = ((USB->ept[eptn] & USB_EPT_BIT_MASK) | USB_RXDTS | USB_RXTC | USB_TXTC))
/**
* @brief clear usb tx/rx toggle
* @param eptn: endpoint number
* @retval none
*/
#define USB_CLEAR_TXDTS(eptn) { \
if(USB->ept_bit[eptn].txdts != 0) \
USB_TOGGLE_TXDTS(eptn); \
}
#define USB_CLEAR_RXDTS(eptn) { \
if(USB->ept_bit[eptn].rxdts != 0) \
USB_TOGGLE_RXDTS(eptn); \
}
/**
* @brief set usb endpoint type
*/
/**
* @brief set usb transfer type
* @param eptn: endpoint number
* @param type: transfer type
* @retval none
*/
#define USB_SET_TRANS_TYPE(eptn, type) (USB->ept[eptn] = (USB->ept[eptn] & USB_EPT_BIT_MASK & (~USB_TRANS_TYPE)) | type)
/**
* @brief set/clear usb extend function
* @param eptn: endpoint number
* @retval none
*/
#define USB_SET_EXF(eptn) (USB->ept[eptn] = USB_TXTC | USB_RXTC | ((USB->ept[eptn] | USB_EXF) & USB_EPT_BIT_MASK))
#define USB_CLEAR_EXF(eptn) (USB->ept[eptn] = USB_TXTC | USB_RXTC | (USB->ept[eptn] & ((~USB_EXF) & USB_EPT_BIT_MASK)))
/**
* @brief set usb device address
* @param eptn: endpoint number
* @param address: device address
* @retval none
*/
#define USB_SET_EPT_ADDRESS(eptn, address) (USB->ept[eptn] = ((USB->ept[eptn] & USB_EPT_BIT_MASK & (~USB_EPTADDR)) | address))
/**
* @brief free buffer used by application
* @param eptn: endpoint number
* @param inout: transfer direction
* @retval none
*/
#define USB_FREE_DB_USER_BUFFER(eptn, inout) { \
if(inout == DATA_TRANS_IN) \
{ \
USB_TOGGLE_RXDTS(eptn); \
} \
else \
{ \
USB_TOGGLE_TXDTS(eptn); \
} \
}
/**
* @brief clear tx/rx transfer completed flag
* @param eptn: endpoint number
* @retval none
*/
#define USB_CLEAR_TXTC(eptn) (USB->ept[eptn] &= 0xFF7F & USB_EPT_BIT_MASK)
#define USB_CLEAR_RXTC(eptn) (USB->ept[eptn] &= 0x7FFF & USB_EPT_BIT_MASK)
/**
* @brief set/clear endpoint double buffer mode
* @param eptn: endpoint number
* @retval none
*/
#define USB_SET_EPT_DOUBLE_BUFFER(eptn) USB_SET_EXF(eptn)
#define USB_CLEAR_EPT_DOUBLE_BUFFER(eptn) USB_CLEAR_EXF(eptn)
/**
* @}
*/
/** @defgroup USB_exported_types
* @{
*/
/**
* @brief usb endpoint infomation structure definition
*/
typedef struct
{
uint8_t eptn; /*!< endpoint register number (0~7) */
uint8_t ept_address; /*!< endpoint address */
uint8_t inout; /*!< endpoint dir DATA_TRANS_IN or DATA_TRANS_OUT */
uint8_t trans_type; /*!< endpoint type:
EPT_CONTROL_TYPE, EPT_BULK_TYPE, EPT_INT_TYPE, EPT_ISO_TYPE*/
uint16_t tx_addr; /*!< endpoint tx buffer offset address */
uint16_t rx_addr; /*!< endpoint rx buffer offset address */
uint16_t maxpacket; /*!< endpoint max packet*/
uint8_t is_double_buffer; /*!< endpoint double buffer flag */
uint8_t stall; /*!< endpoint is stall state */
uint16_t status; /*!< endpoint status */
/* transmission buffer and count */
uint16_t total_len; /*!< endpoint transmission total length */
uint16_t trans_len; /*!< endpoint transmission length*/
uint8_t *trans_buf; /*!< endpoint transmission buffer */
uint16_t last_len; /*!< last transfer length */
uint16_t rem0_len; /*!< rem transfer length */
uint16_t ept0_slen; /*!< endpoint 0 transfer sum length */
}usb_ept_info;
/**
* @brief type define usb register all
*/
typedef struct
{
/**
* @brief usb endpoint register, offset:0x00
*/
union
{
__IO uint32_t ept[8];
struct
{
__IO uint32_t eptaddr : 4; /* [3:0] */
__IO uint32_t txsts : 2; /* [5:4] */
__IO uint32_t txdts : 1; /* [6] */
__IO uint32_t txtc : 1; /* [7] */
__IO uint32_t exf : 1; /* [8] */
__IO uint32_t trans_type : 2; /* [10:9] */
__IO uint32_t setuptc : 1; /* [11] */
__IO uint32_t rxsts : 2; /* [13:12] */
__IO uint32_t rxdts : 1; /* [14] */
__IO uint32_t rxtc : 1; /* [15] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} ept_bit[8];
};
__IO uint32_t reserved1[8];
/**
* @brief usb control register, offset:0x40
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t csrst : 1; /* [0] */
__IO uint32_t disusb : 1; /* [1] */
__IO uint32_t lpm : 1; /* [2] */
__IO uint32_t ssp : 1; /* [3] */
__IO uint32_t gresume : 1; /* [4] */
__IO uint32_t reserved1 : 3; /* [7:5] */
__IO uint32_t lsofien : 1; /* [8] */
__IO uint32_t sofien : 1; /* [9] */
__IO uint32_t rstien : 1; /* [10] */
__IO uint32_t spien : 1; /* [11] */
__IO uint32_t wkien : 1; /* [12] */
__IO uint32_t beien : 1; /* [13] */
__IO uint32_t ucforien : 1; /* [14] */
__IO uint32_t tcien : 1; /* [15] */
__IO uint32_t reserved2 : 16; /* [31:16] */
} ctrl_bit;
};
/**
* @brief usb interrupt status register, offset:0x44
*/
union
{
__IO uint32_t intsts;
struct
{
__IO uint32_t ept_num : 4; /* [3:0] */
__IO uint32_t inout : 1; /* [4] */
__IO uint32_t reserved1 : 3; /* [7:5] */
__IO uint32_t lsof : 1; /* [8] */
__IO uint32_t sof : 1; /* [9] */
__IO uint32_t rst : 1; /* [10] */
__IO uint32_t sp : 1; /* [11] */
__IO uint32_t wk : 1; /* [12] */
__IO uint32_t be : 1; /* [13] */
__IO uint32_t ucfor : 1; /* [14] */
__IO uint32_t tc : 1; /* [15] */
__IO uint32_t reserved2 : 16; /* [31:16] */
} intsts_bit;
};
/**
* @brief usb frame number register, offset:0x48
*/
union
{
__IO uint32_t sofrnum;
struct
{
__IO uint32_t sofnum : 11; /* [10:0] */
__IO uint32_t lsofnum : 2; /* [12:11] */
__IO uint32_t clck : 1; /* [13] */
__IO uint32_t dmsts : 1; /* [14] */
__IO uint32_t dpsts : 1; /* [15] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} sofrnum_bit;
};
/**
* @brief usb device address register, offset:0x4c
*/
union
{
__IO uint32_t devaddr;
struct
{
__IO uint32_t addr : 7; /* [6:0] */
__IO uint32_t cen : 1; /* [7] */
__IO uint32_t reserved1 : 24; /* [31:8] */
} devaddr_bit;
};
/**
* @brief usb buffer address register, offset:0x50
*/
union
{
__IO uint32_t buftbl;
struct
{
__IO uint32_t reserved1 : 3; /* [2:0] */
__IO uint32_t btaddr : 13; /* [15:3] */
__IO uint32_t reserved2 : 16; /* [31:16] */
} buftbl_bit;
};
__IO uint32_t reserved2[3];
/**
* @brief usb cfg control register, offset:0x60
*/
union
{
__IO uint32_t cfg;
struct
{
__IO uint32_t sofouten : 1; /* [0] */
__IO uint32_t puo : 1; /* [1] */
__IO uint32_t reserved1 : 30; /* [31:2] */
} cfg_bit;
};
} usbd_type;
/**
* @}
*/
#define USB ((usbd_type *) USBFS_BASE)
typedef usbd_type usb_reg_type;
extern uint32_t g_usb_packet_address;
/** @defgroup USB_exported_functions
* @{
*/
void usb_dev_init(usbd_type *usbx);
void usb_connect(usbd_type *usbx);
void usb_disconnect(usbd_type *usbx);
void usb_usbbufs_enable(usbd_type *usbx, confirm_state state);
void usb_ept_open(usbd_type *usbx, usb_ept_info *ept_info);
void usb_ept_close(usbd_type *usbx, usb_ept_info *ept_info);
void usb_write_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes);
void usb_read_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes);
void usb_interrupt_enable(usbd_type *usbx, uint16_t interrupt, confirm_state new_state);
void usb_set_address(usbd_type *usbx, uint8_t address);
void usb_ept_stall(usbd_type *usbx, usb_ept_info *ept_info);
void usb_enter_suspend(usbd_type *usbx);
void usb_exit_suspend(usbd_type *usbx);
void usb_remote_wkup_set(usbd_type *usbx);
void usb_remote_wkup_clear(usbd_type *usbx);
uint16_t usb_buffer_malloc(uint16_t maxpacket);
void usb_buffer_free(void);
flag_status usb_flag_get(usbd_type *usbx, uint16_t flag);
flag_status usb_interrupt_flag_get(usbd_type *usbx, uint16_t flag);
void usb_flag_clear(usbd_type *usbx, uint16_t flag);
#ifdef __cplusplus
}
#endif
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

181
libraries/drivers/inc/at32f403a_407_wdt.h Normal file
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@@ -0,0 +1,181 @@
/**
**************************************************************************
* @file at32f403a_407_wdt.h
* @brief at32f403a_407 wdt header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F403A_407_WDT_H
#define __AT32F403A_407_WDT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f403a_407.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @addtogroup WDT
* @{
*/
/** @defgroup WDT_flags_definition
* @brief wdt flag
* @{
*/
#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
/**
* @}
*/
/** @defgroup WDT_exported_types
* @{
*/
/**
* @brief wdt division value type
*/
typedef enum
{
WDT_CLK_DIV_4 = 0x00, /*!< wdt clock divider value is 4 */
WDT_CLK_DIV_8 = 0x01, /*!< wdt clock divider value is 8 */
WDT_CLK_DIV_16 = 0x02, /*!< wdt clock divider value is 16 */
WDT_CLK_DIV_32 = 0x03, /*!< wdt clock divider value is 32 */
WDT_CLK_DIV_64 = 0x04, /*!< wdt clock divider value is 64 */
WDT_CLK_DIV_128 = 0x05, /*!< wdt clock divider value is 128 */
WDT_CLK_DIV_256 = 0x06 /*!< wdt clock divider value is 256 */
} wdt_division_type;
/**
* @brief wdt cmd value type
*/
typedef enum
{
WDT_CMD_LOCK = 0x0000, /*!< disable write protection command */
WDT_CMD_UNLOCK = 0x5555, /*!< enable write protection command */
WDT_CMD_ENABLE = 0xCCCC, /*!< enable wdt command */
WDT_CMD_RELOAD = 0xAAAA /*!< reload command */
} wdt_cmd_value_type;
/**
* @brief type define wdt register all
*/
typedef struct
{
/**
* @brief wdt cmd register, offset:0x00
*/
union
{
__IO uint32_t cmd;
struct
{
__IO uint32_t cmd : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cmd_bit;
};
/**
* @brief wdt div register, offset:0x04
*/
union
{
__IO uint32_t div;
struct
{
__IO uint32_t div : 3; /* [2:0] */
__IO uint32_t reserved1 : 29;/* [31:3] */
} div_bit;
};
/**
* @brief wdt rld register, offset:0x08
*/
union
{
__IO uint32_t rld;
struct
{
__IO uint32_t rld : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} rld_bit;
};
/**
* @brief wdt sts register, offset:0x0C
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t divf : 1; /* [0] */
__IO uint32_t rldf : 1; /* [1] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} sts_bit;
};
} wdt_type;
/**
* @}
*/
#define WDT ((wdt_type *) WDT_BASE)
/** @defgroup WDT_exported_functions
* @{
*/
void wdt_enable(void);
void wdt_counter_reload(void);
void wdt_reload_value_set(uint16_t reload_value);
void wdt_divider_set(wdt_division_type division);
void wdt_register_write_enable( confirm_state new_state);
flag_status wdt_flag_get(uint16_t wdt_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f403a_407_wwdt.h
* @brief at32f403a_407 wwdt header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F403A_407_WWDT_H
#define __AT32F403A_407_WWDT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f403a_407.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @addtogroup WWDT
* @{
*/
/** @defgroup WWDT_enable_bit_definition
* @brief wwdt enable bit
* @{
*/
#define WWDT_EN_BIT ((uint32_t)0x00000080) /*!< wwdt enable bit */
/**
* @}
*/
/** @defgroup WWDT_exported_types
* @{
*/
/**
* @brief wwdt division type
*/
typedef enum
{
WWDT_PCLK1_DIV_4096 = 0x00, /*!< wwdt counter clock = (pclk1/4096)/1) */
WWDT_PCLK1_DIV_8192 = 0x01, /*!< wwdt counter clock = (pclk1/4096)/2) */
WWDT_PCLK1_DIV_16384 = 0x02, /*!< wwdt counter clock = (pclk1/4096)/4) */
WWDT_PCLK1_DIV_32768 = 0x03 /*!< wwdt counter clock = (pclk1/4096)/8) */
} wwdt_division_type;
/**
* @brief type define wwdt register all
*/
typedef struct
{
/**
* @brief wwdt ctrl register, offset:0x00
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t cnt : 7; /* [6:0] */
__IO uint32_t wwdten : 1; /* [7] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} ctrl_bit;
};
/**
* @brief wwdt cfg register, offset:0x04
*/
union
{
__IO uint32_t cfg;
struct
{
__IO uint32_t win : 7; /* [6:0] */
__IO uint32_t div : 2; /* [8:7] */
__IO uint32_t rldien : 1; /* [9] */
__IO uint32_t reserved1 : 22;/* [31:10] */
} cfg_bit;
};
/**
* @brief wwdt cfg register, offset:0x08
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t rldf : 1; /* [0] */
__IO uint32_t reserved1 : 31;/* [31:1] */
} sts_bit;
};
} wwdt_type;
/**
* @}
*/
#define WWDT ((wwdt_type *) WWDT_BASE)
/** @defgroup WWDT_exported_functions
* @{
*/
void wwdt_reset(void);
void wwdt_divider_set(wwdt_division_type division);
void wwdt_flag_clear(void);
void wwdt_enable(uint8_t wwdt_cnt);
void wwdt_interrupt_enable(void);
flag_status wwdt_flag_get(void);
flag_status wwdt_interrupt_flag_get(void);
void wwdt_counter_set(uint8_t wwdt_cnt);
void wwdt_window_counter_set(uint8_t window_cnt);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f403a_407_xmc.h
* @brief at32f403a_407 xmc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F403A_407_XMC_H
#define __AT32F403A_407_XMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f403a_407.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @addtogroup XMC
* @{
*/
/** @defgroup XMC_exported_types
* @{
*/
/**
* @brief xmc data address bus multiplexing type
*/
typedef enum
{
XMC_DATA_ADDR_MUX_DISABLE = 0x00000000, /*!< xmc address/data multiplexing disable */
XMC_DATA_ADDR_MUX_ENABLE = 0x00000002 /*!< xmc address/data multiplexing enable */
} xmc_data_addr_mux_type;
/**
* @brief xmc burst access mode type
*/
typedef enum
{
XMC_BURST_MODE_DISABLE = 0x00000000, /*!< xmc burst mode disable */
XMC_BURST_MODE_ENABLE = 0x00000100 /*!< xmc burst mode enable */
} xmc_burst_access_mode_type;
/**
* @brief xmc asynchronous wait type
*/
typedef enum
{
XMC_ASYN_WAIT_DISABLE = 0x00000000, /*!< xmc wait signal during asynchronous transfers disbale */
XMC_ASYN_WAIT_ENABLE = 0x00008000 /*!< xmc wait signal during asynchronous transfers enable */
} xmc_asyn_wait_type;
/**
* @brief xmc wrapped mode type
*/
typedef enum
{
XMC_WRAPPED_MODE_DISABLE = 0x00000000, /*!< xmc direct wrapped burst is disbale */
XMC_WRAPPED_MODE_ENABLE = 0x00000400 /*!< xmc direct wrapped burst is enable */
} xmc_wrap_mode_type;
/**
* @brief xmc write operation type
*/
typedef enum
{
XMC_WRITE_OPERATION_DISABLE = 0x00000000, /*!< xmc write operations is disable */
XMC_WRITE_OPERATION_ENABLE = 0x00001000 /*!< xmc write operations is enable */
} xmc_write_operation_type;
/**
* @brief xmc wait signal type
*/
typedef enum
{
XMC_WAIT_SIGNAL_DISABLE = 0x00000000, /*!< xmc nwait signal is disable */
XMC_WAIT_SIGNAL_ENABLE = 0x00002000 /*!< xmc nwait signal is enable */
} xmc_wait_signal_type;
/**
* @brief xmc write burst type
*/
typedef enum
{
XMC_WRITE_BURST_SYN_DISABLE = 0x00000000, /*!< xmc write operations are always performed in asynchronous mode */
XMC_WRITE_BURST_SYN_ENABLE = 0x00080000 /*!< xmc write operations are performed in synchronous mode */
} xmc_write_burst_type;
/**
* @brief xmc extended mode type
*/
typedef enum
{
XMC_WRITE_TIMING_DISABLE = 0x00000000, /*!< xmc write timing disable */
XMC_WRITE_TIMING_ENABLE = 0x00004000 /*!< xmc write timing enable */
} xmc_extended_mode_type;
/**
* @brief xmc nand wait type
*/
typedef enum
{
XMC_WAIT_OPERATION_DISABLE = 0x00000000, /*!< xmc wait operation for the nand flash memory bank disable */
XMC_WAIT_OPERATION_ENABLE = 0x00000002 /*!< xmc wait operation for the nand flash memory bank enable */
} xmc_nand_wait_type;
/**
* @brief xmc ecc enable type
*/
typedef enum
{
XMC_ECC_OPERATION_DISABLE = 0x00000000, /*!< xmc ecc module disable */
XMC_ECC_OPERATION_ENABLE = 0x00000040 /*!< xmc ecc module enable */
} xmc_ecc_enable_type;
/**
* @brief xmc nor/sram bank type
*/
typedef enum
{
XMC_BANK1_NOR_SRAM1 = 0x00000000, /*!< xmc nor/sram subbank1 */
XMC_BANK1_NOR_SRAM4 = 0x00000003 /*!< xmc nor/sram subbank4 */
} xmc_nor_sram_subbank_type;
/**
* @brief xmc class bank type
*/
typedef enum
{
XMC_BANK2_NAND = 0x00000010, /*!< xmc nand flash bank2 */
} xmc_class_bank_type;
/**
* @brief xmc memory type
*/
typedef enum
{
XMC_DEVICE_SRAM = 0x00000000, /*!< xmc device choice sram */
XMC_DEVICE_PSRAM = 0x00000004, /*!< xmc device choice psram */
XMC_DEVICE_NOR = 0x00000008 /*!< xmc device choice nor flash */
} xmc_memory_type;
/**
* @brief xmc data width type
*/
typedef enum
{
XMC_BUSTYPE_8_BITS = 0x00000000, /*!< xmc databuss width 8bits */
XMC_BUSTYPE_16_BITS = 0x00000010 /*!< xmc databuss width 16bits */
} xmc_data_width_type;
/**
* @brief xmc wait signal polarity type
*/
typedef enum
{
XMC_WAIT_SIGNAL_LEVEL_LOW = 0x00000000, /*!< xmc nwait active low */
XMC_WAIT_SIGNAL_LEVEL_HIGH = 0x00000200 /*!< xmc nwait active high */
} xmc_wait_signal_polarity_type;
/**
* @brief xmc wait timing type
*/
typedef enum
{
XMC_WAIT_SIGNAL_SYN_BEFORE = 0x00000000, /*!< xmc nwait signal is active one data cycle before wait state */
XMC_WAIT_SIGNAL_SYN_DURING = 0x00000800 /*!< xmc nwait signal is active during wait state */
} xmc_wait_timing_type;
/**
* @brief xmc access mode type
*/
typedef enum
{
XMC_ACCESS_MODE_A = 0x00000000, /*!< xmc access mode A */
XMC_ACCESS_MODE_B = 0x10000000, /*!< xmc access mode B */
XMC_ACCESS_MODE_C = 0x20000000, /*!< xmc access mode C */
XMC_ACCESS_MODE_D = 0x30000000 /*!< xmc access mode D */
} xmc_access_mode_type;
/**
* @brief xmc ecc page size type
*/
typedef enum
{
XMC_ECC_PAGESIZE_256_BYTES = 0x00000000, /*!< xmc ecc page size 256 bytes */
XMC_ECC_PAGESIZE_512_BYTES = 0x00020000, /*!< xmc ecc page size 512 bytes */
XMC_ECC_PAGESIZE_1024_BYTES = 0x00040000, /*!< xmc ecc page size 1024 bytes */
XMC_ECC_PAGESIZE_2048_BYTES = 0x00060000, /*!< xmc ecc page size 2048 bytes */
XMC_ECC_PAGESIZE_4096_BYTES = 0x00080000, /*!< xmc ecc page size 4096 bytes */
XMC_ECC_PAGESIZE_8192_BYTES = 0x000A0000 /*!< xmc ecc page size 8192 bytes */
} xmc_ecc_pagesize_type;
/**
* @brief xmc interrupt sources type
*/
typedef enum
{
XMC_INT_RISING_EDGE = 0x00000008, /*!< xmc rising edge detection interrupt enable */
XMC_INT_LEVEL = 0x00000010, /*!< xmc high-level edge detection interrupt enable */
XMC_INT_FALLING_EDGE = 0x00000020 /*!< xmc falling edge detection interrupt enable */
} xmc_interrupt_sources_type;
/**
* @brief xmc interrupt flag type
*/
typedef enum
{
XMC_RISINGEDGE_FLAG = 0x00000001, /*!< xmc interrupt rising edge detection flag */
XMC_LEVEL_FLAG = 0x00000002, /*!< xmc interrupt high-level edge detection flag */
XMC_FALLINGEDGE_FLAG = 0x00000004, /*!< xmc interrupt falling edge detection flag */
XMC_FEMPT_FLAG = 0x00000040 /*!< xmc fifo empty flag */
} xmc_interrupt_flag_type;
/**
* @brief nor/sram banks timing parameters
*/
typedef struct
{
xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram write timing enable */
uint32_t addr_setup_time; /*!< xmc nor/sram address setup time */
uint32_t addr_hold_time; /*!< xmc nor/sram address hold time */
uint32_t data_setup_time; /*!< xmc nor/sram data setup time */
uint32_t bus_latency_time; /*!< xmc nor/sram bus latency time */
uint32_t clk_psc; /*!< xmc nor/sram clock prescale */
uint32_t data_latency_time; /*!< xmc nor/sram data latency time */
xmc_access_mode_type mode; /*!< xmc nor/sram access mode */
} xmc_norsram_timing_init_type;
/**
* @brief xmc nor/sram init structure definition
*/
typedef struct
{
xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
xmc_data_addr_mux_type data_addr_multiplex; /*!< xmc nor/sram address/data multiplexing enable */
xmc_memory_type device; /*!< xmc nor/sram memory device */
xmc_data_width_type bus_type; /*!< xmc nor/sram data bus width */
xmc_burst_access_mode_type burst_mode_enable; /*!< xmc nor/sram burst mode enable */
xmc_asyn_wait_type asynwait_enable; /*!< xmc nor/sram nwait in asynchronous transfer enable */
xmc_wait_signal_polarity_type wait_signal_lv; /*!< xmc nor/sram nwait polarity */
xmc_wrap_mode_type wrapped_mode_enable; /*!< xmc nor/sram wrapped enable */
xmc_wait_timing_type wait_signal_config; /*!< xmc nor/sram nwait timing configuration */
xmc_write_operation_type write_enable; /*!< xmc nor/sram write enable */
xmc_wait_signal_type wait_signal_enable; /*!< xmc nor/sram nwait in synchronous transfer enable */
xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram read-write timing different */
xmc_write_burst_type write_burst_syn; /*!< xmc nor/sram memory write mode control */
} xmc_norsram_init_type;
/**
* @brief nand timing parameters xmc
*/
typedef struct
{
xmc_class_bank_type class_bank; /*!< xmc nand bank */
uint32_t mem_setup_time; /*!< xmc nand memory setup time */
uint32_t mem_waite_time; /*!< xmc nand memory wait time */
uint32_t mem_hold_time; /*!< xmc nand memory hold time */
uint32_t mem_hiz_time; /*!< xmc nand memory databus high resistance time */
} xmc_nand_timinginit_type;
/**
* @brief xmc nand init structure definition
*/
typedef struct
{
xmc_class_bank_type nand_bank; /*!< xmc nand bank */
xmc_nand_wait_type wait_enable; /*!< xmc wait feature enable */
xmc_data_width_type bus_type; /*!< xmc nand bus width */
xmc_ecc_enable_type ecc_enable; /*!< xmc nand ecc enable */
xmc_ecc_pagesize_type ecc_pagesize; /*!< xmc nand ecc page size */
uint32_t delay_time_cycle; /*!< xmc nand cle to re delay */
uint32_t delay_time_ar; /*!< xmc nand ale to re delay */
} xmc_nand_init_type;
typedef struct
{
/**
* @brief xmc bank1 bk1ctrl register, offset:0x00+0x08*(x-1) x= 1 or 4
*/
union
{
__IO uint32_t bk1ctrl;
struct
{
__IO uint32_t en : 1; /* [0] */
__IO uint32_t admuxen : 1; /* [1] */
__IO uint32_t dev : 2; /* [3:2] */
__IO uint32_t extmdbw : 2; /* [5:4] */
__IO uint32_t noren : 1; /* [6] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t syncben : 1; /* [8] */
__IO uint32_t nwpol : 1; /* [9] */
__IO uint32_t wrapen : 1; /* [10] */
__IO uint32_t nwtcfg : 1; /* [11] */
__IO uint32_t wen : 1; /* [12] */
__IO uint32_t nwsen : 1; /* [13] */
__IO uint32_t rwtd : 1; /* [14] */
__IO uint32_t nwasen : 1; /* [15] */
__IO uint32_t crpgs : 3; /* [18:16] */
__IO uint32_t mwmc : 1; /* [19] */
__IO uint32_t reserved2 : 12;/* [31:20] */
} bk1ctrl_bit;
};
/**
* @brief xmc bank1 bk1tmg register, offset:0x04+0x08*(x-1) x= 1 or 4
*/
union
{
__IO uint32_t bk1tmg;
struct
{
__IO uint32_t addrst : 4; /* [3:0] */
__IO uint32_t addrht : 4; /* [7:4] */
__IO uint32_t dtst : 8; /* [15:8] */
__IO uint32_t buslat : 4; /* [19:16] */
__IO uint32_t clkpsc : 4; /* [23:20] */
__IO uint32_t dtlat : 4; /* [27:24] */
__IO uint32_t asyncm : 2; /* [29:28] */
__IO uint32_t reserved1 : 2; /* [31:30] */
} bk1tmg_bit;
};
} xmc_bank1_ctrl_tmg_reg_type;
typedef struct
{
/**
* @brief xmc bank1 bk1tmgwr register, offset:0x104+0x08*(x-1) x= 1 or 4
*/
union
{
__IO uint32_t bk1tmgwr;
struct
{
__IO uint32_t addrst : 4; /* [3:0] */
__IO uint32_t addrht : 4; /* [7:4] */
__IO uint32_t dtst : 8; /* [15:8] */
__IO uint32_t buslat : 4; /* [19:16] */
__IO uint32_t reserved1 : 8; /* [27:20] */
__IO uint32_t asyncm : 2; /* [29:28] */
__IO uint32_t reserved2 : 2; /* [31:30] */
} bk1tmgwr_bit;
};
/**
* @brief xmc bank1 reserved register
*/
__IO uint32_t reserved1;
} xmc_bank1_tmgwr_reg_type;
/**
* @brief xmc bank1 registers
*/
typedef struct
{
/**
* @brief xmc bank1 ctrl and tmg register, offset:0x00~0x1C
*/
xmc_bank1_ctrl_tmg_reg_type ctrl_tmg_group[4];
/**
* @brief xmc bank1 reserved register, offset:0x20~0x100
*/
__IO uint32_t reserved1[57];
/**
* @brief xmc bank1 tmgwr register, offset:0x104~0x11C
*/
xmc_bank1_tmgwr_reg_type tmgwr_group[4];
/**
* @brief xmc bank1 reserved register, offset:0x120~0x21C
*/
__IO uint32_t reserved2[63];
/**
* @brief xmc bank1 ext register, offset:0x220~0x22C
*/
union
{
__IO uint32_t ext[4];
struct
{
__IO uint32_t buslatw2w : 8; /* [7:0] */
__IO uint32_t buslatr2r : 8; /* [15:8] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} ext_bit[4];
};
} xmc_bank1_type;
/**
* @brief xmc bank2 registers
*/
typedef struct
{
/**
* @brief xmc bk2ctrl register, offset:0x60
*/
union
{
__IO uint32_t bk2ctrl;
struct
{
__IO uint32_t reserved1 : 1; /* [0] */
__IO uint32_t nwen : 1; /* [1] */
__IO uint32_t en : 1; /* [2] */
__IO uint32_t dev : 1; /* [3] */
__IO uint32_t extmdbw : 2; /* [5:4] */
__IO uint32_t eccen : 1; /* [6] */
__IO uint32_t reserved2 : 2; /* [8:7] */
__IO uint32_t tcr : 4; /* [12:9] */
__IO uint32_t tar : 4; /* [16:13] */
__IO uint32_t eccpgs : 3; /* [19:17] */
__IO uint32_t reserved3 : 12;/* [31:20] */
} bk2ctrl_bit;
};
/**
* @brief xmc bk2is register, offset:0x64
*/
union
{
__IO uint32_t bk2is;
struct
{
__IO uint32_t res : 1; /* [0] */
__IO uint32_t hls : 1; /* [1] */
__IO uint32_t fes : 1; /* [2] */
__IO uint32_t reien : 1; /* [3] */
__IO uint32_t hlien : 1; /* [4] */
__IO uint32_t feien : 1; /* [5] */
__IO uint32_t fifoe : 1; /* [6] */
__IO uint32_t reserved1 : 25;/* [31:7] */
} bk2is_bit;
};
/**
* @brief xmc bk2tmgmem register, offset:0x68
*/
union
{
__IO uint32_t bk2tmgmem;
struct
{
__IO uint32_t cmst : 8; /* [7:0] */
__IO uint32_t cmwt : 8; /* [15:8] */
__IO uint32_t cmht : 8; /* [23:16] */
__IO uint32_t cmdhizt : 8; /* [31:24] */
} bk2tmgmem_bit;
};
/**
* @brief xmc bk2tmgatt register, offset:0x6C
*/
union
{
__IO uint32_t bk2tmgatt;
struct
{
__IO uint32_t amst : 8; /* [7:0] */
__IO uint32_t amwt : 8; /* [15:8] */
__IO uint32_t amht : 8; /* [23:16] */
__IO uint32_t amdhizt : 8; /* [31:24] */
} bk2tmgatt_bit;
};
/**
* @brief xmc reserved register, offset:0x70
*/
__IO uint32_t reserved1;
/**
* @brief xmc bk2ecc register, offset:0x74
*/
union
{
__IO uint32_t bk2ecc;
struct
{
__IO uint32_t ecc : 32; /* [31:0] */
} bk2ecc_bit;
};
} xmc_bank2_type;
/**
* @}
*/
#define XMC_BANK1 ((xmc_bank1_type *) XMC_BANK1_REG_BASE)
#define XMC_BANK2 ((xmc_bank2_type *) XMC_BANK2_REG_BASE)
/** @defgroup XMC_exported_functions
* @{
*/
void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank);
void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct);
void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct);
void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct);
void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct);
void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state);
void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
void xmc_nand_reset(xmc_class_bank_type xmc_bank);
void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct);
void xmc_nand_timing_config(xmc_nand_timinginit_type* xmc_common_spacetiming_struct,
xmc_nand_timinginit_type* xmc_attribute_spacetiming_struct);
void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct);
void xmc_nand_timing_default_para_init(xmc_nand_timinginit_type* xmc_common_spacetiming_struct,
xmc_nand_timinginit_type* xmc_attribute_spacetiming_struct);
void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank);
void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state);
flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
flag_status xmc_interrupt_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif