/* add user code begin Header */ /** ************************************************************************** * @file at32f415_wk_config.c * @brief work bench config program ************************************************************************** * Copyright notice & Disclaimer * * The software Board Support Package (BSP) that is made available to * download from Artery official website is the copyrighted work of Artery. * Artery authorizes customers to use, copy, and distribute the BSP * software and its related documentation for the purpose of design and * development in conjunction with Artery microcontrollers. Use of the * software is governed by this copyright notice and the following disclaimer. * * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. * ************************************************************************** */ /* add user code end Header */ #include "at32f415_wk_config.h" /* private includes ----------------------------------------------------------*/ /* add user code begin private includes */ /* add user code end private includes */ /* private typedef -----------------------------------------------------------*/ /* add user code begin private typedef */ /* add user code end private typedef */ /* private define ------------------------------------------------------------*/ /* add user code begin private define */ /* add user code end private define */ /* private macro -------------------------------------------------------------*/ /* add user code begin private macro */ /* add user code end private macro */ /* private variables ---------------------------------------------------------*/ /* add user code begin private variables */ /* add user code end private variables */ /* private function prototypes --------------------------------------------*/ /* add user code begin function prototypes */ /* add user code end function prototypes */ /* private user code ---------------------------------------------------------*/ /* add user code begin 0 */ /* add user code end 0 */ /** * @brief system clock config program * @note the system clock is configured as follow: * system clock (sclk) = hick / 12 * pll_mult * system clock source = HICK_VALUE * - sclk = 144000000 * - ahbdiv = 1 * - ahbclk = 144000000 * - apb1div = 2 * - apb1clk = 72000000 * - apb2div = 2 * - apb2clk = 72000000 * - pll_mult = 36 * - flash_wtcyc = 4 cycle * @param none * @retval none */ void wk_system_clock_config(void) { /* reset crm */ crm_reset(); /* config flash psr register */ flash_psr_set(FLASH_WAIT_CYCLE_4); /* enable lick */ crm_clock_source_enable(CRM_CLOCK_SOURCE_LICK, TRUE); /* wait till lick is ready */ while(crm_flag_get(CRM_LICK_STABLE_FLAG) != SET) { } /* enable hick */ crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); /* wait till hick is ready */ while(crm_flag_get(CRM_HICK_STABLE_FLAG) != SET) { } /* config pll clock resource */ crm_pll_config(CRM_PLL_SOURCE_HICK, CRM_PLL_MULT_36); /* enable pll */ crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); /* wait till pll is ready */ while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) { } /* config ahbclk */ crm_ahb_div_set(CRM_AHB_DIV_1); /* config apb2clk, the maximum frequency of APB2 clock is 75 MHz */ crm_apb2_div_set(CRM_APB2_DIV_2); /* config apb1clk, the maximum frequency of APB1 clock is 75 MHz */ crm_apb1_div_set(CRM_APB1_DIV_2); /* enable auto step mode */ crm_auto_step_mode_enable(TRUE); /* select pll as system clock source */ crm_sysclk_switch(CRM_SCLK_PLL); /* wait till pll is used as system clock source */ while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) { } /* disable auto step mode */ crm_auto_step_mode_enable(FALSE); /* update system_core_clock global variable */ system_core_clock_update(); } /** * @brief config periph clock * @param none * @retval none */ void wk_periph_clock_config(void) { /* enable iomux periph clock */ crm_periph_clock_enable(CRM_IOMUX_PERIPH_CLOCK, TRUE); /* enable gpioa periph clock */ crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); /* enable gpiob periph clock */ crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); /* enable tmr1 periph clock */ crm_periph_clock_enable(CRM_TMR1_PERIPH_CLOCK, TRUE); /* enable tmr3 periph clock */ crm_periph_clock_enable(CRM_TMR3_PERIPH_CLOCK, TRUE); } /** * @brief nvic config * @param none * @retval none */ void wk_nvic_config(void) { nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); } /** * @brief init tmr1 function. * @param none * @retval none */ void wk_tmr1_init(void) { /* add user code begin tmr1_init 0 */ /* add user code end tmr1_init 0 */ gpio_init_type gpio_init_struct; tmr_output_config_type tmr_output_struct; tmr_brkdt_config_type tmr_brkdt_struct; gpio_default_para_init(&gpio_init_struct); /* add user code begin tmr1_init 1 */ /* add user code end tmr1_init 1 */ /* configure the CH1 pin */ gpio_init_struct.gpio_pins = GPIO_PINS_8; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; gpio_init(GPIOA, &gpio_init_struct); /* configure the CH2 pin */ gpio_init_struct.gpio_pins = GPIO_PINS_9; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; gpio_init(GPIOA, &gpio_init_struct); /* configure the CH3 pin */ gpio_init_struct.gpio_pins = GPIO_PINS_10; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; gpio_init(GPIOA, &gpio_init_struct); /* configure the CH4 pin */ gpio_init_struct.gpio_pins = GPIO_PINS_11; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; gpio_init(GPIOA, &gpio_init_struct); /* configure counter settings */ tmr_base_init(TMR1, 65535, 0); tmr_cnt_dir_set(TMR1, TMR_COUNT_UP); tmr_clock_source_div_set(TMR1, TMR_CLOCK_DIV1); tmr_repetition_counter_set(TMR1, 0); tmr_period_buffer_enable(TMR1, FALSE); /* configure primary mode settings */ tmr_sub_sync_mode_set(TMR1, FALSE); tmr_primary_mode_select(TMR1, TMR_PRIMARY_SEL_RESET); /* configure channel 1 output settings */ tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF; tmr_output_struct.oc_output_state = TRUE; tmr_output_struct.occ_output_state = FALSE; tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH; tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH; tmr_output_struct.oc_idle_state = FALSE; tmr_output_struct.occ_idle_state = FALSE; tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_1, &tmr_output_struct); tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_1, 0); tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_1, FALSE); /* configure channel 2 output settings */ tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF; tmr_output_struct.oc_output_state = TRUE; tmr_output_struct.occ_output_state = FALSE; tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH; tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH; tmr_output_struct.oc_idle_state = FALSE; tmr_output_struct.occ_idle_state = FALSE; tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_2, &tmr_output_struct); tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_2, 0); tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_2, FALSE); /* configure channel 3 output settings */ tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF; tmr_output_struct.oc_output_state = TRUE; tmr_output_struct.occ_output_state = FALSE; tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH; tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH; tmr_output_struct.oc_idle_state = FALSE; tmr_output_struct.occ_idle_state = FALSE; tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_3, &tmr_output_struct); tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_3, 0); tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_3, FALSE); /* configure channel 4 output settings */ tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF; tmr_output_struct.oc_output_state = TRUE; tmr_output_struct.occ_output_state = FALSE; tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH; tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH; tmr_output_struct.oc_idle_state = FALSE; tmr_output_struct.occ_idle_state = FALSE; tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_4, &tmr_output_struct); tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_4, 0); tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_4, FALSE); /* configure break and dead-time settings */ tmr_brkdt_struct.brk_enable = FALSE; tmr_brkdt_struct.auto_output_enable = FALSE; tmr_brkdt_struct.brk_polarity = TMR_BRK_INPUT_ACTIVE_LOW; tmr_brkdt_struct.fcsoen_state = FALSE; tmr_brkdt_struct.fcsodis_state = FALSE; tmr_brkdt_struct.wp_level = TMR_WP_OFF; tmr_brkdt_struct.deadtime = 0; tmr_brkdt_config(TMR1, &tmr_brkdt_struct); tmr_output_enable(TMR1, TRUE); tmr_counter_enable(TMR1, TRUE); /* add user code begin tmr1_init 2 */ /* add user code end tmr1_init 2 */ } /** * @brief init tmr3 function. * @param none * @retval none */ void wk_tmr3_init(void) { /* add user code begin tmr3_init 0 */ /* add user code end tmr3_init 0 */ gpio_init_type gpio_init_struct; tmr_output_config_type tmr_output_struct; gpio_default_para_init(&gpio_init_struct); /* add user code begin tmr3_init 1 */ /* add user code end tmr3_init 1 */ /* configure the CH3 pin */ gpio_init_struct.gpio_pins = GPIO_PINS_0; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; gpio_init(GPIOB, &gpio_init_struct); /* configure the CH4 pin */ gpio_init_struct.gpio_pins = GPIO_PINS_1; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; gpio_init(GPIOB, &gpio_init_struct); /* configure counter settings */ tmr_base_init(TMR3, 65535, 0); tmr_cnt_dir_set(TMR3, TMR_COUNT_UP); tmr_clock_source_div_set(TMR3, TMR_CLOCK_DIV1); tmr_period_buffer_enable(TMR3, FALSE); /* configure primary mode settings */ tmr_sub_sync_mode_set(TMR3, FALSE); tmr_primary_mode_select(TMR3, TMR_PRIMARY_SEL_RESET); /* configure channel 3 output settings */ tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF; tmr_output_struct.oc_output_state = TRUE; tmr_output_struct.occ_output_state = FALSE; tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH; tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH; tmr_output_struct.oc_idle_state = FALSE; tmr_output_struct.occ_idle_state = FALSE; tmr_output_channel_config(TMR3, TMR_SELECT_CHANNEL_3, &tmr_output_struct); tmr_channel_value_set(TMR3, TMR_SELECT_CHANNEL_3, 0); tmr_output_channel_buffer_enable(TMR3, TMR_SELECT_CHANNEL_3, FALSE); /* configure channel 4 output settings */ tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF; tmr_output_struct.oc_output_state = TRUE; tmr_output_struct.occ_output_state = FALSE; tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH; tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH; tmr_output_struct.oc_idle_state = FALSE; tmr_output_struct.occ_idle_state = FALSE; tmr_output_channel_config(TMR3, TMR_SELECT_CHANNEL_4, &tmr_output_struct); tmr_channel_value_set(TMR3, TMR_SELECT_CHANNEL_4, 0); tmr_output_channel_buffer_enable(TMR3, TMR_SELECT_CHANNEL_4, FALSE); tmr_counter_enable(TMR3, TRUE); /* add user code begin tmr3_init 2 */ /* add user code end tmr3_init 2 */ } /* add user code begin 1 */ /* add user code end 1 */