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QD4C-firmware/libraries/zf_common/zf_common_clock.c

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2023-12-11 21:45:06 +08:00
/*********************************************************************************************************************
* CH32V307VCT6 Opensourec Library <EFBFBD><EFBFBD><EFBFBD><EFBFBD>CH32V307VCT6 <EFBFBD><EFBFBD>Դ<EFBFBD>⣩<EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڹٷ<EFBFBD> SDK <EFBFBD>ӿڵĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>
* Copyright (c) 2022 SEEKFREE <EFBFBD><EFBFBD><EFBFBD>ɿƼ<EFBFBD>
*
feat: 根据新板卡QD4C更新时钟配置 硬件上更换为 16MHz 的外部晶振，将PLL输入源更改为二分频之后的HSE，后续倍频系数不变（仅更改了144MHz下的配置）
2024-04-15 23:08:37 +08:00
* <EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD> CH32V307VCT6 <EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
first commit
2023-12-11 21:45:06 +08:00
*
* CH32V307VCT6 <EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
feat: 根据新板卡QD4C更新时钟配置 硬件上更换为 16MHz 的外部晶振，将PLL输入源更改为二分频之后的HSE，后续倍频系数不变（仅更改了144MHz下的配置）
2024-04-15 23:08:37 +08:00
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ը<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ᷢ<EFBFBD><EFBFBD><EFBFBD><EFBFBD> GPL<EFBFBD><EFBFBD>GNU General Public License<EFBFBD><EFBFBD><EFBFBD><EFBFBD> GNU ͨ<EFBFBD>ù<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֤<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD> GPL <EFBFBD>ĵ<EFBFBD> 3 <EFBFBD>棨<EFBFBD><EFBFBD> GPL3.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><EFBFBD>κκ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>İ汾<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<EFBFBD><EFBFBD><EFBFBD>޸<EFBFBD><EFBFBD><EFBFBD>
first commit
2023-12-11 21:45:06 +08:00
*
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD>ķ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>δ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>κεı<EFBFBD>֤
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ի<EFBFBD><EFBFBD>ʺ<EFBFBD><EFBFBD>ض<EFBFBD><EFBFBD><EFBFBD>;<EFBFBD>ı<EFBFBD>֤
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϸ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> GPL
*
* <EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬʱ<EFBFBD>յ<EFBFBD>һ<EFBFBD><EFBFBD> GPL <EFBFBD>ĸ<EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD>У<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><https://www.gnu.org/licenses/>
*
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD> GPL3.0 <EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>֤Э<EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD>İ汾
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӣ<EFBFBD>İ<EFBFBD><EFBFBD><EFBFBD> libraries/doc <EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>µ<EFBFBD> GPL3_permission_statement.txt <EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>֤<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> libraries <EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>µ<EFBFBD> LICENSE <EFBFBD>ļ<EFBFBD>
* <EFBFBD><EFBFBD>ӭ<EFBFBD><EFBFBD>λʹ<EFBFBD>ò<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD>޸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD>뱣<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɿƼ<EFBFBD><EFBFBD>İ<EFBFBD>Ȩ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*
* <EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> zf_common_clock
* <EFBFBD><EFBFBD>˾<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>ɶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɿƼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>޹<EFBFBD>˾
* <EFBFBD>汾<EFBFBD><EFBFBD>Ϣ <EFBFBD>鿴 libraries/doc <EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> version <EFBFBD>ļ<EFBFBD> <EFBFBD>汾˵<EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> MounRiver Studio V1.8.1
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽ̨ CH32V307VCT6
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> https://seekfree.taobao.com/
*
* <EFBFBD>޸ļ<EFBFBD>¼
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ע
feat: 根据新板卡QD4C更新时钟配置 硬件上更换为 16MHz 的外部晶振，将PLL输入源更改为二分频之后的HSE，后续倍频系数不变（仅更改了144MHz下的配置）
2024-04-15 23:08:37 +08:00
* 2022-09-15 <EFBFBD><EFBFBD> W first version
first commit
2023-12-11 21:45:06 +08:00
********************************************************************************************************************/
#include "ch32v30x.h"
#include "zf_common_function.h"
#include "zf_common_interrupt.h"
#include "zf_common_clock.h"
uint32 system_clock = SYSTEM_CLOCK_144M; // ϵͳʱ<CDB3><CAB1><EFBFBD><EFBFBD>Ϣ
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ʱ<EFBFBD>ӻָ<D3BB><D6B8><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD> <20>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> void
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> void
//-------------------------------------------------------------------------------------------------------------------
void clock_reset(void)
{
feat: 根据新板卡QD4C更新时钟配置 硬件上更换为 16MHz 的外部晶振，将PLL输入源更改为二分频之后的HSE，后续倍频系数不变（仅更改了144MHz下的配置）
2024-04-15 23:08:37 +08:00
RCC->CTLR |= (uint32) 0x00000001; //ʹ<><CAB9> HSI <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
first commit
2023-12-11 21:45:06 +08:00
RCC->CFGR0 &= (uint32) 0xF8FF0000;
RCC->CTLR &= (uint32) 0xFEF6FFFF;
RCC->CTLR &= (uint32) 0xFFFBFFFF;
RCC->CFGR0 &= (uint32) 0xFF80FFFF;
RCC->INTR = (uint32) 0x009F0000; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϲ<D0B6><CFB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> clock ʱ<><CAB1>Ƶ<EFBFBD><C6B5> <20>Ƽ<EFBFBD>ʹ<EFBFBD><CAB9> zf_common_clock.h <20><> system_clock_enum <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> void
//-------------------------------------------------------------------------------------------------------------------
void clock_set_freq(uint32 clock)
{
clock_reset();
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t) RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do {
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t) 0x01;
}
else
{
HSEStatus = (uint32_t) 0x00;
}
if (HSEStatus == (uint32_t) 0x01)
{
// /* Enable Prefetch Buffer */
// FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; ((uint8_t)0x10)
//
// /* Flash 2 wait state */
// FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); ((uint8_t)0x03)
// FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; ((uint8_t)0x02)
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t) RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t) RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t) RCC_PPRE1_DIV1;
/* PLL configuration: PLLCLK = HSE * ? = ? MHz */
RCC->CFGR0 &= (uint32) ((uint32) ~(RCC_PLLSRC | RCC_PLLXTPRE
| RCC_PLLMULL));
if (clock == SYSTEM_CLOCK_144M)
feat: 根据新板卡QD4C更新时钟配置 硬件上更换为 16MHz 的外部晶振，将PLL输入源更改为二分频之后的HSE，后续倍频系数不变（仅更改了144MHz下的配置）
2024-04-15 23:08:37 +08:00
RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE_Div2
first commit
2023-12-11 21:45:06 +08:00
| RCC_PLLMULL18_EXTEN);
else if (clock == SYSTEM_CLOCK_120M)
RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
| RCC_PLLMULL15_EXTEN);
else if (clock == SYSTEM_CLOCK_96M)
RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
| RCC_PLLMULL12_EXTEN);
else if (clock == SYSTEM_CLOCK_72M)
RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
| RCC_PLLMULL9_EXTEN);
else if (clock == SYSTEM_CLOCK_48M)
RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
| RCC_PLLMULL6_EXTEN);
else if (clock == SYSTEM_CLOCK_24M)
RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
| RCC_PLLMULL3_EXTEN);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t) ((uint32_t) ~(RCC_SW));
RCC->CFGR0 |= (uint32_t) RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
while(1);
// <20>ⲿ<EFBFBD><E2B2BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD><C8B6><EFBFBD>ȱʧ ʱ<><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʧ<EFBFBD><CAA7>
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ʱ<EFBFBD>ӳ<EFBFBD>ʼ<EFBFBD><CABC>
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> clock ʱ<><CAB1>Ƶ<EFBFBD><C6B5> <20>Ƽ<EFBFBD>ʹ<EFBFBD><CAB9> zf_common_clock.h <20><> system_clock_enum <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> void
// ʹ<><CAB9>ʾ<EFBFBD><CABE> clock_init(SYSTEM_CLOCK_144M); // <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ 144MHz
//-------------------------------------------------------------------------------------------------------------------
void clock_init(uint32 clock)
{
system_clock = clock; // <20><>¼<EFBFBD><C2BC><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ƶ<EFBFBD><C6B5>
clock_reset();
clock_set_freq(clock);
interrupt_init();
}
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