btl143/QD4C-firmware
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feat: 根据新板卡QD4C更新时钟配置

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硬件上更换为 16MHz 的外部晶振，将PLL输入源更改为二分频之后的HSE，后续倍频系数不变（仅更改了144MHz下的配置）
This commit is contained in:
bmy
2024-04-15 23:08:37 +08:00
parent fbed8b272e
commit 75b9cc4a8f
2 changed files with 7 additions and 7 deletions
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2
app/main.c
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@@ -39,7 +39,7 @@ uint8_t last_state;
int main(void)
{
TYPE_UNION test_data[BY_FRAME_DATA_NUM];
clock_init(SYSTEM_CLOCK_120M);
clock_init(SYSTEM_CLOCK_144M);
system_delay_init();
debug_init();

2
libraries/zf_common/zf_common_clock.c
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@@ -105,7 +105,7 @@ void clock_set_freq(uint32 clock)
| RCC_PLLMULL));
if (clock == SYSTEM_CLOCK_144M)
RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE_Div2
| RCC_PLLMULL18_EXTEN);
else if (clock == SYSTEM_CLOCK_120M)
RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE