commit eaa7cc0eeaa0eb34a88ca2ff51d40e65bf3d5ec3 Author: CaoWangrenbo Date: Mon Dec 11 21:45:06 2023 +0800 first commit diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000..ecc57c4 --- /dev/null +++ b/.clang-format @@ -0,0 +1,38 @@ +--- +BasedOnStyle: Microsoft +Language: Cpp + +################################### +# indent conf +################################### + +UseTab: Never +IndentWidth: 4 +TabWidth: 4 +ColumnLimit: 0 +AccessModifierOffset: -4 +NamespaceIndentation: All +FixNamespaceComments: false +BreakBeforeBraces: Linux + +################################### +# other styles +################################### + +# +# for more conf, you can ref: https://clang.llvm.org/docs/ClangFormatStyleOptions.html +# + +AllowShortIfStatementsOnASingleLine: true + +AllowShortLoopsOnASingleLine: true + +AllowShortBlocksOnASingleLine: true + +IndentCaseLabels: true + +SortIncludes: false + +AlignConsecutiveMacros: AcrossEmptyLines + +AlignConsecutiveAssignments: Consecutive diff --git a/.eide.usr.ctx.json b/.eide.usr.ctx.json new file mode 100644 index 0000000..b7dab6d --- /dev/null +++ b/.eide.usr.ctx.json @@ -0,0 +1,3 @@ +{ + "target": "Debug" +} \ No newline at end of file diff --git a/.eide/debug.files.options.yml b/.eide/debug.files.options.yml new file mode 100644 index 0000000..2486c4f --- /dev/null +++ b/.eide/debug.files.options.yml @@ -0,0 +1,31 @@ +########################################################################################## +# Append Compiler Options For Source Files +# +# syntax: +# : +# +# examples: +# 'main.cpp': --cpp11 -Og ... +# 'src/*.c': -gnu -O2 ... +# 'src/lib/**/*.cpp': --cpp11 -Os ... +# '!Application/*.c': -O0 +# '**/*.c': -O2 -gnu ... +# +# For more syntax, please refer to: https://www.npmjs.com/package/micromatch +# +########################################################################################## + +version: '1.0' + +# +# for source files with filesystem paths +# +files: +# './test/**/*.c': --c99 + +# +# for source files with virtual paths +# +virtualPathFiles: +# 'virtual_folder/**/*.c': --c99 + diff --git a/.eide/debug.riscv.gcc.options.json b/.eide/debug.riscv.gcc.options.json new file mode 100644 index 0000000..ebda364 --- /dev/null +++ b/.eide/debug.riscv.gcc.options.json @@ -0,0 +1,30 @@ +{ + "version": 2, + "beforeBuildTasks": [], + "afterBuildTasks": [], + "global": { + "output-debug-info": "enable", + "arch": "rv32imafc", + "abi": "ilp32f", + "code-model": "medlow", + "misc-control": "-fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -msave-restore -fno-common" + }, + "c/cpp-compiler": { + "language-c": "c11", + "language-cpp": "c++11", + "optimization": "level-debug", + "warnings": "all-warnings", + "one-elf-section-per-function": true, + "one-elf-section-per-data": true, + "C_FLAGS": "-Wl,-Bstatic -std=gnu99" + }, + "asm-compiler": { + "ASM_FLAGS": "-Wl,-Bstatic" + }, + "linker": { + "output-format": "elf", + "remove-unused-input-sections": true, + "LD_FLAGS": "-nostartfiles -Xlinker --gc-sections -Wl,-Map,\"firmware_violet_zf.map\" --specs=nano.specs --specs=nosys.specs", + "LIB_FLAGS": "-lm -lzf_device_config" + } +} \ No newline at end of file diff --git a/.eide/eide.json b/.eide/eide.json new file mode 100644 index 0000000..4ea68a9 --- /dev/null +++ b/.eide/eide.json @@ -0,0 +1,69 @@ +{ + "name": "violet_firmware_zf", + "type": "RISC-V", + "dependenceList": [], + "srcDirs": [ + "app", + "libraries/sdk", + "libraries/zf_common", + "libraries/zf_device", + "libraries/zf_driver" + ], + "virtualFolder": { + "name": "", + "files": [], + "folders": [] + }, + "outDir": "build", + "deviceName": null, + "packDir": null, + "miscInfo": { + "uid": "69341645eb5f07c48df11ef1dfcd69cb" + }, + "targets": { + "Debug": { + "excludeList": [], + "toolchain": "RISCV_GCC", + "compileConfig": { + "linkerScriptPath": "libraries\\sdk\\Ld\\Link.ld", + "options": "null" + }, + "uploader": "Custom", + "uploadConfig": { + "bin": "${ExecutableName}.bin", + "commandLine": "${ProjectRoot}/tools/download.cmd ${programFile}", + "eraseChipCommand": "${ProjectRoot}/tools/erase.cmd" + }, + "uploadConfigMap": { + "JLink": { + "bin": "", + "baseAddr": "", + "cpuInfo": { + "vendor": "null", + "cpuName": "null" + }, + "proType": 1, + "speed": 8000, + "otherCmds": "" + } + }, + "custom_dep": { + "name": "default", + "incList": [ + "app", + "libraries/sdk/Peripheral", + "libraries/sdk/Core", + "libraries/zf_common", + "libraries/zf_device", + "libraries/zf_driver" + ], + "libList": [ + "libraries/zf_device" + ], + "sourceDirList": [], + "defineList": [] + } + } + }, + "version": "3.3" +} \ No newline at end of file diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..f085a67 --- /dev/null +++ b/.gitignore @@ -0,0 +1,93 @@ +# Created by https://www.toptal.com/developers/gitignore/api/visualstudiocode,eclipse +# Edit at https://www.toptal.com/developers/gitignore?templates=visualstudiocode,eclipse + +### Eclipse ### +.metadata +bin/ +tmp/ +*.tmp +*.bak +*.swp +*~.nib +local.properties +.settings/ +.loadpath +.recommenders + +# External tool builders +.externalToolBuilders/ + +# PyDev specific (Python IDE for Eclipse) +*.pydevproject + + +# CDT- autotools +.autotools + +# Java annotation processor (APT) +.factorypath + +# PDT-specific (PHP Development Tools) +.buildpath + +# sbteclipse plugin +.target + +# Tern plugin +.tern-project + +# TeXlipse plugin +.texlipse + +# STS (Spring Tool Suite) +.springBeans + +# Code Recommenders +.recommenders/ + +# Annotation Processing +.apt_generated/ +.apt_generated_test/ + +# Scala IDE specific (Scala & Java development for Eclipse) +.cache-main +.scala_dependencies +.worksheet + +# Uncomment this line if you wish to ignore the project description file. +# Typically, this file would be tracked if it contains build/dependency configurations: +#.project + +### Eclipse Patch ### +# Spring Boot Tooling +.sts4-cache/ + +### VisualStudioCode ### +.vscode/* +!.vscode/settings.json +!.vscode/tasks.json +!.vscode/launch.json +!.vscode/extensions.json +!.vscode/*.code-snippets + +# Local History for Visual Studio Code +.history/ + +# Built Visual Studio Code Extensions +*.vsix + +### VisualStudioCode Patch ### +# Ignore all local history of files +.history +.ionide + +# End of https://www.toptal.com/developers/gitignore/api/visualstudiocode,eclipse + +### mrs build path +obj/* + +### EIDE build path +build/* + +### workplace setting +*.code-workspace diff --git a/.vscode/launch.json b/.vscode/launch.json new file mode 100644 index 0000000..d4d5714 --- /dev/null +++ b/.vscode/launch.json @@ -0,0 +1,17 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "cwd": "${workspaceRoot}", + "type": "cortex-debug", + "request": "launch", + "name": "jlink", + "servertype": "jlink", + "interface": "swd", + "executable": "build\\Debug\\violet_firmware_zf.elf", + "runToEntryPoint": "main", + "device": "null", + "toolchainPrefix": "riscv-none-embed" + } + ] +} \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..487a390 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "sonarlint.pathToCompileCommands": "${workspaceFolder}\\build\\Debug\\compile_commands.json" +} \ No newline at end of file diff --git a/Readme.md b/Readme.md new file mode 100644 index 0000000..4680052 --- /dev/null +++ b/Readme.md @@ -0,0 +1,29 @@ +# fireware_violet + +## 使用 VSCode + EIDE + GCC + OpenOCD 开发 + +* 确保 VSCode 安装了 `EIDE` 插件 + +* 将文件 `firmware_violet.code-workspace_eg` 重命名为 `firmware_violet.code-workspace` + +* 双击 `firmware_violet.code-workspace` 从工作区开启 VSCode + +* 工作区设置中修改 EIDE 插件设置，将 `EIDE.RISCV.InstallDirectory` 和 `EIDE.OpenOCD.ExePath` 两项设置更改为自己 MRS 下 ToolChains 中 GCC 和 OpenOCD 的路径 + +### eg. + +`EIDE.RISCV.InstallDirectory` - `D:\Program_Files_nospace\MounRiver\MounRiver_Studio\toolchain\RISC-V Embedded GCC` + +`EIDE.OpenOCD.ExePath` - `D:\Program_Files_nospace\MounRiver\MounRiver_Studio\toolchain\OpenOCD\bin\openocd.exe` + +然后就可以愉快的使用 VSCode 进行开发和下载了 + +## 常用快捷键： + +* 编译：`F7` + +* 下载：`Ctrl + Alt + D` + +* 擦除：`Ctrl + Alt + E`（虽然没什么用） + +* 调试：`F5` （需配合 Cortex-Debug 插件，由于不支持 `gdb version < 9` 设置起来稍微复杂，后面再补说明） diff --git a/app/isr.c b/app/isr.c new file mode 100644 index 0000000..210feae --- /dev/null +++ b/app/isr.c @@ -0,0 +1,493 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ isr +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "zf_common_headfile.h" +void NMI_Handler(void) __attribute__((interrupt())); +void HardFault_Handler(void) __attribute__((interrupt())); + +void USART1_IRQHandler(void) __attribute__((interrupt())); +void USART2_IRQHandler(void) __attribute__((interrupt())); +void USART3_IRQHandler(void) __attribute__((interrupt())); +void UART4_IRQHandler (void) __attribute__((interrupt())); +void UART5_IRQHandler (void) __attribute__((interrupt())); +void UART6_IRQHandler (void) __attribute__((interrupt())); +void UART7_IRQHandler (void) __attribute__((interrupt())); +void UART8_IRQHandler (void) __attribute__((interrupt())); +void DVP_IRQHandler (void) __attribute__((interrupt())); +//void TIM1_BRK_IRQHandler (void) __attribute__((interrupt())); +void TIM1_UP_IRQHandler (void) __attribute__((interrupt())); +//void TIM1_TRG_COM_IRQHandler (void) __attribute__((interrupt())); +//void TIM1_CC_IRQHandler (void) __attribute__((interrupt())); +void TIM2_IRQHandler (void) __attribute__((interrupt())); +void TIM3_IRQHandler (void) __attribute__((interrupt())); +void TIM4_IRQHandler (void) __attribute__((interrupt())); +void TIM5_IRQHandler (void) __attribute__((interrupt())); +void TIM6_IRQHandler (void) __attribute__((interrupt())); +void TIM7_IRQHandler (void) __attribute__((interrupt())); +//void TIM8_BRK_IRQHandler (void) __attribute__((interrupt())); +void TIM8_UP_IRQHandler (void) __attribute__((interrupt())); +//void TIM8_TRG_COM_IRQHandler (void) __attribute__((interrupt())); +//void TIM8_CC_IRQHandler (void) __attribute__((interrupt())); +//void TIM9_BRK_IRQHandler (void) __attribute__((interrupt())); +void TIM9_UP_IRQHandler (void) __attribute__((interrupt())); +//void TIM9_TRG_COM_IRQHandler (void) __attribute__((interrupt())); +//void TIM9_CC_IRQHandler (void) __attribute__((interrupt())); +//void TIM10_BRK_IRQHandler (void) __attribute__((interrupt())); +void TIM10_UP_IRQHandler (void) __attribute__((interrupt())); +//void TIM10_TRG_COM_IRQHandler (void) __attribute__((interrupt())); +//void TIM10_CC_IRQHandler (void) __attribute__((interrupt())); + +void EXTI0_IRQHandler(void) __attribute__((interrupt())); +void EXTI1_IRQHandler(void) __attribute__((interrupt())); +void EXTI2_IRQHandler(void) __attribute__((interrupt())); +void EXTI3_IRQHandler(void) __attribute__((interrupt())); +void EXTI4_IRQHandler(void) __attribute__((interrupt())); +void EXTI9_5_IRQHandler(void) __attribute__((interrupt())); +void EXTI15_10_IRQHandler(void) __attribute__((interrupt())); + +void USART1_IRQHandler(void) +{ + if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET) + { + + USART_ClearITPendingBit(USART1, USART_IT_RXNE); + } +} +void USART2_IRQHandler(void) +{ + if(USART_GetITStatus(USART2, USART_IT_RXNE) != RESET) + { + + + USART_ClearITPendingBit(USART2, USART_IT_RXNE); + } +} +void USART3_IRQHandler(void) +{ + if(USART_GetITStatus(USART3, USART_IT_RXNE) != RESET) + { +#if DEBUG_UART_USE_INTERRUPT // debug ж + debug_interrupr_handler(); // debug ڽմ ݻᱻ debug λȡ +#endif // ޸ DEBUG_UART_INDEX δҪŵӦĴжȥ + USART_ClearITPendingBit(USART3, USART_IT_RXNE); + } +} +void UART4_IRQHandler (void) +{ + if(USART_GetITStatus(UART4, USART_IT_RXNE) != RESET) + { + + USART_ClearITPendingBit(UART4, USART_IT_RXNE); + } +} +void UART5_IRQHandler (void) +{ + if(USART_GetITStatus(UART5, USART_IT_RXNE) != RESET) + { + camera_uart_handler(); + USART_ClearITPendingBit(UART5, USART_IT_RXNE); + } +} +void UART6_IRQHandler (void) +{ + if(USART_GetITStatus(UART6, USART_IT_RXNE) != RESET) + { + + USART_ClearITPendingBit(UART6, USART_IT_RXNE); + } +} +void UART7_IRQHandler (void) +{ + if(USART_GetITStatus(UART7, USART_IT_RXNE) != RESET) + { + wireless_module_uart_handler(); + USART_ClearITPendingBit(UART7, USART_IT_RXNE); + } +} +void UART8_IRQHandler (void) +{ + if(USART_GetITStatus(UART8, USART_IT_RXNE) != RESET) + { + gps_uart_callback(); + USART_ClearITPendingBit(UART8, USART_IT_RXNE); + } + +} + + + +void DVP_IRQHandler(void) +{ + if (DVP->IFR & RB_DVP_IF_FRM_DONE) + { + camera_dvp_handler(); + DVP->IFR &= ~RB_DVP_IF_FRM_DONE; + } +} +void EXTI0_IRQHandler(void) +{ + if(SET == EXTI_GetITStatus(EXTI_Line0)) + { + EXTI_ClearITPendingBit(EXTI_Line0); + + } +} + +void EXTI1_IRQHandler(void) +{ + if(SET == EXTI_GetITStatus(EXTI_Line1)) + { + EXTI_ClearITPendingBit(EXTI_Line1); + + } +} + +void EXTI2_IRQHandler(void) +{ + if(SET == EXTI_GetITStatus(EXTI_Line2)) + { + EXTI_ClearITPendingBit(EXTI_Line2); + + } +} + +void EXTI3_IRQHandler(void) +{ + if(SET == EXTI_GetITStatus(EXTI_Line3)) + { + EXTI_ClearITPendingBit(EXTI_Line3); + + } +} + +void EXTI4_IRQHandler(void) +{ + if(SET == EXTI_GetITStatus(EXTI_Line4)) + { + EXTI_ClearITPendingBit(EXTI_Line4); + + } +} + +void EXTI9_5_IRQHandler(void) +{ + if(SET == EXTI_GetITStatus(EXTI_Line5)) + { + EXTI_ClearITPendingBit(EXTI_Line5); + + } + if(SET == EXTI_GetITStatus(EXTI_Line6)) + { + EXTI_ClearITPendingBit(EXTI_Line6); + + } + if(SET == EXTI_GetITStatus(EXTI_Line7)) + { + EXTI_ClearITPendingBit(EXTI_Line7); + + } + if(SET == EXTI_GetITStatus(EXTI_Line8)) + { + EXTI_ClearITPendingBit(EXTI_Line8); + + } + if(SET == EXTI_GetITStatus(EXTI_Line9)) + { + EXTI_ClearITPendingBit(EXTI_Line9); + + } + +} + +void EXTI15_10_IRQHandler(void) +{ + if(SET == EXTI_GetITStatus(EXTI_Line10)) + { + + // ˴дû (A10/B10..E10) Ŵ + + // ˴дû (A10/B10..E10) Ŵ + + EXTI_ClearITPendingBit(EXTI_Line10); + } + if(SET == EXTI_GetITStatus(EXTI_Line11)) + { + EXTI_ClearITPendingBit(EXTI_Line11); + + } + if(SET == EXTI_GetITStatus(EXTI_Line12)) + { + EXTI_ClearITPendingBit(EXTI_Line12); + + } + if(SET == EXTI_GetITStatus(EXTI_Line13)) + { + // -----------------* ToF INT ж Ԥжϴ *----------------- + tof_module_exti_handler(); + // -----------------* ToF INT ж Ԥжϴ *----------------- + // ˴дû (A13/B13..E13) Ŵ + + // ˴дû (A13/B13..E13) Ŵ + + EXTI_ClearITPendingBit(EXTI_Line13); + + } + if(SET == EXTI_GetITStatus(EXTI_Line14)) + { + // -----------------* DM1XA ź Ԥжϴ *----------------- + dm1xa_light_callback(); + // -----------------* DM1XA ź Ԥжϴ *----------------- + EXTI_ClearITPendingBit(EXTI_Line14); + } + if(SET == EXTI_GetITStatus(EXTI_Line15)) + { + // -----------------* DM1XA /ź Ԥжϴ *----------------- + dm1xa_sound_callback(); + // -----------------* DM1XA /ź Ԥжϴ *----------------- + EXTI_ClearITPendingBit(EXTI_Line15); + } +} + + +void TIM1_UP_IRQHandler(void) +{ + if(TIM_GetITStatus(TIM1, TIM_IT_Update) != RESET) + { + TIM_ClearITPendingBit(TIM1, TIM_IT_Update); + + } +} + + +void TIM2_IRQHandler(void) +{ + if(TIM_GetITStatus(TIM2, TIM_IT_Update) != RESET) + { + TIM_ClearITPendingBit(TIM2, TIM_IT_Update ); + + + } +} + +void TIM3_IRQHandler(void) +{ + if(TIM_GetITStatus(TIM3, TIM_IT_Update) != RESET) + { + TIM_ClearITPendingBit(TIM3, TIM_IT_Update ); + + + } +} + +void TIM4_IRQHandler(void) +{ + if(TIM_GetITStatus(TIM4, TIM_IT_Update) != RESET) + { + TIM_ClearITPendingBit(TIM4, TIM_IT_Update ); + + + } +} + +void TIM5_IRQHandler(void) +{ + if(TIM_GetITStatus(TIM5, TIM_IT_Update) != RESET) + { + TIM_ClearITPendingBit(TIM5, TIM_IT_Update ); + + + } +} + +void TIM6_IRQHandler(void) +{ + if(TIM_GetITStatus(TIM6, TIM_IT_Update) != RESET) + { + TIM_ClearITPendingBit(TIM6, TIM_IT_Update ); + + } +} + +void TIM7_IRQHandler(void) +{ + if(TIM_GetITStatus(TIM7, TIM_IT_Update) != RESET) + { + TIM_ClearITPendingBit(TIM7, TIM_IT_Update ); + + + } +} + + +void TIM8_UP_IRQHandler(void) +{ + if(TIM_GetITStatus(TIM8, TIM_IT_Update) != RESET) + { + TIM_ClearITPendingBit(TIM8, TIM_IT_Update); + + } +} + + +void TIM9_UP_IRQHandler(void) +{ + if(TIM_GetITStatus(TIM9, TIM_IT_Update) != RESET) + { + TIM_ClearITPendingBit(TIM9, TIM_IT_Update); + + } +} + + +void TIM10_UP_IRQHandler(void) +{ + if(TIM_GetITStatus(TIM10, TIM_IT_Update) != RESET) + { + TIM_ClearITPendingBit(TIM10, TIM_IT_Update); + + } +} + + + +//.section .text.vector_handler, "ax", @progbits + +// .weak EXTI0_IRQHandler /* EXTI Line 0 */ +// .weak EXTI1_IRQHandler /* EXTI Line 1 */ +// .weak EXTI2_IRQHandler /* EXTI Line 2 */ +// .weak EXTI3_IRQHandler /* EXTI Line 3 */ +// .weak EXTI4_IRQHandler /* EXTI Line 4 */ +// .weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ +// .weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ +// .weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ +// .weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ +// .weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ +// .weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ +// .weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ +// .weak ADC1_2_IRQHandler /* ADC1_2 */ +// .weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ +// .weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ +// .weak CAN1_RX1_IRQHandler /* CAN1 RX1 */ +// .weak CAN1_SCE_IRQHandler /* CAN1 SCE */ +// .weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */ +// .weak TIM1_BRK_IRQHandler /* TIM1 Break */ +// .weak TIM1_UP_IRQHandler /* TIM1 Update */ +// .weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ +// .weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */ +// .weak TIM2_IRQHandler /* TIM2 */ +// .weak TIM3_IRQHandler /* TIM3 */ +// .weak TIM4_IRQHandler /* TIM4 */ +// .weak I2C1_EV_IRQHandler /* I2C1 Event */ +// .weak I2C1_ER_IRQHandler /* I2C1 Error */ +// .weak I2C2_EV_IRQHandler /* I2C2 Event */ +// .weak I2C2_ER_IRQHandler /* I2C2 Error */ +// .weak SPI1_IRQHandler /* SPI1 */ +// .weak SPI2_IRQHandler /* SPI2 */ +// .weak USART1_IRQHandler /* USART1 */ +// .weak USART2_IRQHandler /* USART2 */ +// .weak USART3_IRQHandler /* USART3 */ +// .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ +// .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ +// .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ +// .weak TIM8_BRK_IRQHandler /* TIM8 Break */ +// .weak TIM8_UP_IRQHandler /* TIM8 Update */ +// .weak TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ +// .weak TIM8_CC_IRQHandler /* TIM8 Capture Compare */ +// .weak RNG_IRQHandler /* RNG */ +// .weak FSMC_IRQHandler /* FSMC */ +// .weak SDIO_IRQHandler /* SDIO */ +// .weak TIM5_IRQHandler /* TIM5 */ +// .weak SPI3_IRQHandler /* SPI3 */ +// .weak UART4_IRQHandler /* UART4 */ +// .weak UART5_IRQHandler /* UART5 */ +// .weak TIM6_IRQHandler /* TIM6 */ +// .weak TIM7_IRQHandler /* TIM7 */ +// .weak DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ +// .weak DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ +// .weak DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ +// .weak DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ +// .weak DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ +// .weak ETH_IRQHandler /* ETH */ +// .weak ETH_WKUP_IRQHandler /* ETH WakeUp */ +// .weak CAN2_TX_IRQHandler /* CAN2 TX */ +// .weak CAN2_RX0_IRQHandler /* CAN2 RX0 */ +// .weak CAN2_RX1_IRQHandler /* CAN2 RX1 */ +// .weak CAN2_SCE_IRQHandler /* CAN2 SCE */ +// .weak OTG_FS_IRQHandler /* OTGFS */ +// .weak USBHSWakeup_IRQHandler /* USBHS Wakeup */ +// .weak USBHS_IRQHandler /* USBHS */ +// .weak DVP_IRQHandler /* DVP */ +// .weak UART6_IRQHandler /* UART6 */ +// .weak UART7_IRQHandler /* UART7 */ +// .weak UART8_IRQHandler /* UART8 */ +// .weak TIM9_BRK_IRQHandler /* TIM9 Break */ +// .weak TIM9_UP_IRQHandler /* TIM9 Update */ +// .weak TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */ +// .weak TIM9_CC_IRQHandler /* TIM9 Capture Compare */ +// .weak TIM10_BRK_IRQHandler /* TIM10 Break */ +// .weak TIM10_UP_IRQHandler /* TIM10 Update */ +// .weak TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */ +// .weak TIM10_CC_IRQHandler /* TIM10 Capture Compare */ +// .weak DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ +// .weak DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ +// .weak DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */ +// .weak DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */ +// .weak DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */ +// .weak DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ + +/******************************************************************************* +* Function Name : NMI_Handler +* Description : This function handles NMI exception. +* Input : None +* Return : None +*******************************************************************************/ +void NMI_Handler(void) +{ +} + +/******************************************************************************* +* Function Name : HardFault_Handler +* Description : This function handles Hard Fault exception. +* Input : None +* Return : None +*******************************************************************************/ +void HardFault_Handler(void) +{ + while (1) + { + } +} + + diff --git a/app/isr.h b/app/isr.h new file mode 100644 index 0000000..81cfd34 --- /dev/null +++ b/app/isr.h @@ -0,0 +1,47 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ isr +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + + +#ifndef __ISR_H +#define __ISR_H + + +#include "zf_common_headfile.h" + + + +#endif + + diff --git a/app/main.c b/app/main.c new file mode 100644 index 0000000..d71eb23 --- /dev/null +++ b/app/main.c @@ -0,0 +1,57 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ main +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +#include "zf_common_headfile.h" + + +int main (void) +{ + clock_init(SYSTEM_CLOCK_120M); // ʼоƬʱ ƵΪ 120MHz + debug_init(); // رڳʼMPU ʱ Դ + + // ˴дû ʼ + ips114_init(); + mt9v03x_init(); + // ˴дû ʼ + + while(1) + { + // ˴дҪѭִеĴ + if(mt9v03x_finish_flag){ + ips114_show_gray_image(0, 0, mt9v03x_image[0], 188, 120, 188, 120,0); + } + // ˴дҪѭִеĴ + } +} + diff --git a/libraries/doc/GPL3_permission_statement.txt b/libraries/doc/GPL3_permission_statement.txt new file mode 100644 index 0000000..9114bb3 --- /dev/null +++ b/libraries/doc/GPL3_permission_statement.txt @@ -0,0 +1,13 @@ +CH32V307VCT6 Opensourec Library : An open source library of third party interfaces based on the official SDK +Copyright (C) 2022 SEEKFREE 逐飞科技 + +CH32V307VCT6 Opensourec Library is free software: +you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, +either version 3 of the License, or (at your option) any later version. + +CH32V307VCT6 Opensourec Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +See the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along with CH32V307VCT6 Opensourec Library. +If not, see . \ No newline at end of file diff --git a/libraries/doc/version.txt b/libraries/doc/version.txt new file mode 100644 index 0000000..77497d5 --- /dev/null +++ b/libraries/doc/version.txt @@ -0,0 +1,182 @@ +V3.4.0 + (2023-11-22) Ż IPS/TFT Ļʾ߼ ͼʾЧ + (2023-11-22) ޸ IMU ̬תضʹֵ쳣 + (2023-11-22) ͷʼ FIFO ò ڴռ + +V3.3.2 + (2023-10-17) ͷɼģʽJPEG->ԭʼݸʽ + (2023-10-17) ͷ˫BUFF + +V3.3.1 + (2023-08-05) ɼʼ˲ + +V3.3.0 + (2023-07-05) zf_device_type ToF + (2023-07-05) ToF ģ DL1B + (2023-07-05) ޸ soft_iic transfer ȡΪ 0 ʱ restart źŵ bug + (2023-07-05) ޸ĬƵʵ120Mhz + (2023-07-05) RAMʼַƫ64ֽڣRAMռ1KB + +V3.2.0 + (2023-05-25) SPIWIFI + (2023-05-20) િЭ + +V3.1.8 + (2023-05-20) Ļʾ޸Ϊ double + (2023-05-20) ޸IMU660RAʼ쳣 BUG + (2023-05-20) ޸ OLED_8X16_FONT ʾ쳣 ɱ淶ʱ + (2023-05-20) ͫIICͨţĬ֡40֡ + +V3.1.7 + (2023-05-11) FLASHдлϵͳƵǰϵͳʱӸλ,޸޸ƵʲɹBUG + +V3.1.6 + (2023-05-04) ޸3ӳbug + +V3.1.5 + (2023-04-26) ɾеӲѹջжĬʹѹջ + +V3.1.4 + (2023-04-24) ޸IMU66RAIICbug + +V3.1.3 + (2023-04-24) ޸ErBW_sύflashbug + (2023-04-24) ޸ErBW_sύflashϵͳƵʴ120Mhzbug + +V3.1.2 + (2023-04-11) ޸Ǵύspi bug + (2023-04-17) ͷlibļ + (2023-04-17) GPS ޸벿ִ RMC + (2023-04-17) ̬ת޸Ϊ궨庯 + (2023-04-17) ͷִڳʼʧܺرմж + (2023-04-17) wifi ԶӲԴӿ + (2023-04-17) DL1A INT жϲɼ + +V3.1.1 + (2023-03-21) ޸usʱ׼ȷ + (2023-03-21) ޸usʱ׼ȷMCUķͶ˳ʼʧ + +V3.1.0 + (2023-03-18) MCUȥ + (2023-03-18) TOF + (2023-03-18) ʱ10޷ʹõBUG + (2023-03-13) gpsļ + (2023-03-13) ޸3ӳBUG + +V3.0.3 + (2023-03-10) ޸ijЩʱûֵ + +V3.0.2 + (2022-12-26) ޸ + +V3.0.1 + (2022-11-28) GPSײ + (2022-11-28) Ӵָ + +V3.0.0 + (2022-09-14) ʹµSDK + (2022-10-14) 汾 + +V1.6.0 + (2022-04-26) Եʹýӿ + (2022-04-26) µ OLED 6*8 ֿ뾯 + (2022-04-26) ӽǶȱӿ + +V1.5.8 + (2022-04-20) zf_pwm.hļеSystemCoreClock滻Ϊsystem_clock, + (2022-04-25) ޸ļ + +V1.5.7 + (2022-04-16) ޸1.8TFTĻֱʲԵ⡣ + +V1.5.6 + (2022-04-14) ޸IICACKźŲԵ + +V1.5.5 + (2022-03-29) ADC_InitStructureṹ帳ֵ޸ADCֵ׼ + +V1.5.4 + (2022-03-26) ɾǰжȼ + +V1.5.3 + (2022-03-22) ȸ㵥Ԫ + +V1.5.2 + (2022-03-21) ͷDVPɼ֡ģʽ޸Ϊѭɼģʽ + (2022-03-21) ʾ + +V1.5.1 + (2022-03-16) ޸Ļ + (2022-03-16) ޸ĿжϺ + (2022-03-16) ޸ģӿ + (2022-03-16) еint8_t->int8,int16_t->int16,int32_t->int32 + +V1.5.0 + (2022-03-10) CH573ļ + +V1.4.1 + (2022-02-17) ɫ궨RGB565_ + +V1.4.0 + (2022-02-14) GPIOжļ + (2022-02-14) ޸flashļ + +V1.3.7 + (2022-02-13) ޸uart.cencoder.cвֲȷע + (2022-02-13) ޸encoder_channel_enumö嶨 + +V1.3.6 + (2022-01-24) ޸IPS2.0ģʽʾȫ + +V1.3.5 + (2022-01-17) ޸Ķʱʱ׼ + +V1.3.4 + (2022-01-17) ޸flash޸ö嶨壬޸ֻд0-64KB flash + +V1.3.3 + (2022-01-10) ޸ch2еĺ궨 + +V1.3.2 + (2022-01-10) ԻisrļеCH1CH2Ļص + +V1.3.1 + (2022-01-10) ԻCH1CH2 + +V1.3.0 + (2022-01-06) 򿪣ʾо + (2022-01-06) ޸ıʼ + +V1.2.3 + (2022-01-04) ޸IJֲȷע + +V1.2.2 + (2021-12-23) ͷɼɱ־λvolatile + +V1.2.1 + (2021-12-09) ޸ͷע + +V1.2.0 + (2021-12-08) ޸ ͷD0-D7궨⡣ + +V1.1.0 + (2021-12-01) ĻĬϵĻɫΪɫ + (2021-12-01) дߴļ + (2021-12-01) fifoļ + (2021-12-01) ޸ OLED ʾ BUG + (2021-12-02) ޸ myabsʽʱ⡣ + (2021-12-03) ͫɫͷļ + (2021-12-03) дļ + +V1.0.3 + (2021-12-01) ޸ijЩļʽһµµ롣 + +V1.0.2 + (2021-11-30) رADC_BUFFʹADCֵ׼ȷ + (2021-11-30) code· + +V1.0.1 + (2021-11-29) USE_ZF_TYPEDEFֵΪ1 + +V1.0.0 + (2021-11-25) 汾,⹫ diff --git a/libraries/sdk/Core/core_riscv.c b/libraries/sdk/Core/core_riscv.c new file mode 100644 index 0000000..88f4dac --- /dev/null +++ b/libraries/sdk/Core/core_riscv.c @@ -0,0 +1,419 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : core_riscv.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : RISC-V Core Peripheral Access Layer Source File +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/********************************************************************* + * @fn __get_FFLAGS + * + * @brief Return the Floating-Point Accrued Exceptions + * + * @return fflags value + */ +uint32_t __get_FFLAGS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "fflags" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_FFLAGS + * + * @brief Set the Floating-Point Accrued Exceptions + * + * @param value - set FFLAGS value + * + * @return none + */ +void __set_FFLAGS(uint32_t value) +{ + __ASM volatile ("csrw fflags, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_FRM + * + * @brief Return the Floating-Point Dynamic Rounding Mode + * + * @return frm value + */ +uint32_t __get_FRM(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "frm" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_FRM + * + * @brief Set the Floating-Point Dynamic Rounding Mode + * + * @param value - set frm value + * + * @return none + */ +void __set_FRM(uint32_t value) +{ + __ASM volatile ("csrw frm, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_FCSR + * + * @brief Return the Floating-Point Control and Status Register + * + * @return fcsr value + */ +uint32_t __get_FCSR(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "fcsr" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_FCSR + * + * @brief Set the Floating-Point Dynamic Rounding Mode + * + * @param value - set fcsr value + * + * @return none + */ +void __set_FCSR(uint32_t value) +{ + __ASM volatile ("csrw fcsr, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile ("csrw misa, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MIE + * + * @brief Return the Machine Interrupt Enable Register + * + * @return mie value + */ +uint32_t __get_MIE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mie" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set mie value + * + * @return none + */ +void __set_MIE(uint32_t value) +{ + __ASM volatile ("csrw mie, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile ("csrw mepc, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile ("csrw mcause, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile ("csrw mtval, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); + return (result); +} + diff --git a/libraries/sdk/Core/core_riscv.h b/libraries/sdk/Core/core_riscv.h new file mode 100644 index 0000000..3c63c1a --- /dev/null +++ b/libraries/sdk/Core/core_riscv.h @@ -0,0 +1,373 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : core_riscv.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : RISC-V Core Peripheral Access Layer Header File for CH32V30x +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint64_t vuc64; /* Read Only */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint64_t uc64; /* Read Only */ +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int64_t vsc64; /* Read Only */ +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int64_t sc64; /* Read Only */ +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint64_t vu64; +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int64_t vs64; +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int64_t s64; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO u32 CTLR; + __IO u32 SR; + __IO u64 CNT; + __IO u64 CMP; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000 ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + +#define SysTick ((SysTick_Type *) 0xE000F000) + +/********************************************************************* + * @fn __enable_irq + * + * @brief Enable Global Interrupt + * + * @return none + */ +RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) ); +} + +/********************************************************************* + * @fn __disable_irq + * + * @brief Disable Global Interrupt + * + * @return none + */ +RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn: Interrupt Numbers + * + * @return none + */ +RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn: Interrupt Numbers + * + * @return none + */ +RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn: Interrupt Numbers + * + * @return 1 - Interrupt Enable + * 0 - Interrupt Disable + */ +RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn: Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn: Interrupt Numbers + * + * @return None + */ +RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn: Interrupt Numbers + * + * @return None + */ +RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn: Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * priority - + * bit7 - pre-emption priority + * bit6~bit4 - subpriority + * @return None + */ +RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return None + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return None + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + uint32_t t; + + t = NVIC->SCTLR; + NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev) + NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); + asm volatile ("wfi"); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param add - VTF interrupt service function base address. + * IRQn -Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * @return None + */ +RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ + if(num > 3) return ; + + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else{ + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return None + */ +RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + + +/* Core_Exported_Functions */ +extern uint32_t __get_FFLAGS(void); +extern void __set_FFLAGS(uint32_t value); +extern uint32_t __get_FRM(void); +extern void __set_FRM(uint32_t value); +extern uint32_t __get_FCSR(void); +extern void __set_FCSR(uint32_t value); +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MIE(void); +extern void __set_MIE(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MTVAL(void); +extern void __set_MTVAL(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + + +#endif + + + + + diff --git a/libraries/sdk/Ld/Link.ld b/libraries/sdk/Ld/Link.ld new file mode 100644 index 0000000..aa73cb2 --- /dev/null +++ b/libraries/sdk/Ld/Link.ld @@ -0,0 +1 @@ +ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V30x_D8C - CH32V305RB-CH32V305FB CH32V30x_D8 - CH32V303CB-CH32V303RB */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K */ /* CH32V30x_D8C - CH32V307VC-CH32V307WC-CH32V307RC CH32V30x_D8 - CH32V303VC-CH32V303RC FLASH + RAM supports the following configuration FLASH-192K + RAM-128K FLASH-224K + RAM-96K FLASH-256K + RAM-64K FLASH-288K + RAM-32K */ RAM (xrw) : ORIGIN = 0x20000040, LENGTH = 63K FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.glue_7) *(.glue_7t) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file diff --git a/libraries/sdk/Peripheral/ch32v30x.h b/libraries/sdk/Peripheral/ch32v30x.h new file mode 100644 index 0000000..229e947 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x.h @@ -0,0 +1,5243 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : CH32V30x Device Peripheral Access Layer Header File. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_H +#define __CH32V30x_H + + + +#ifdef __cplusplus + extern "C" { +#endif + +//#define CH32V30x_D8 /* CH32V303x */ +#define CH32V30x_D8C /* CH32V307x-CH32V305x */ + +#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ + +/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x1000) /* Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTicK_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + +#ifdef CH32V30x_D8 + TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ + TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */ + RNG_IRQn = 63, /* RNG global Interrupt */ + FSMC_IRQn = 64, /* FSMC global Interrupt */ + SDIO_IRQn = 65, /* SDIO global Interrupt */ + TIM5_IRQn = 66, /* TIM5 global Interrupt */ + SPI3_IRQn = 67, /* SPI3 global Interrupt */ + UART4_IRQn = 68, /* UART4 global Interrupt */ + UART5_IRQn = 69, /* UART5 global Interrupt */ + TIM6_IRQn = 70, /* TIM6 global Interrupt */ + TIM7_IRQn = 71, /* TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */ + OTG_FS_IRQn = 83, /* OTGFS global Interrupt */ + UART6_IRQn = 87, /* UART6 global Interrupt */ + UART7_IRQn = 88, /* UART7 global Interrupt */ + UART8_IRQn = 89, /* UART8 global Interrupt */ + TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */ + TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */ + TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */ + TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */ + TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */ + TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */ + TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */ + TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */ + DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */ + DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */ + DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */ + DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */ + DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */ + +#endif + +#ifdef CH32V30x_D8C + USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ + TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */ + RNG_IRQn = 63, /* RNG global Interrupt */ + FSMC_IRQn = 64, /* FSMC global Interrupt */ + SDIO_IRQn = 65, /* SDIO global Interrupt */ + TIM5_IRQn = 66, /* TIM5 global Interrupt */ + SPI3_IRQn = 67, /* SPI3 global Interrupt */ + UART4_IRQn = 68, /* UART4 global Interrupt */ + UART5_IRQn = 69, /* UART5 global Interrupt */ + TIM6_IRQn = 70, /* TIM6 global Interrupt */ + TIM7_IRQn = 71, /* TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 77, /* ETH global Interrupt */ + ETH_WKUP_IRQn = 78, /* ETH WakeUp Interrupt */ + CAN2_TX_IRQn = 79, /* CAN2 TX Interrupts */ + CAN2_RX0_IRQn = 80, /* CAN2 RX0 Interrupts */ + CAN2_RX1_IRQn = 81, /* CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 82, /* CAN2 SCE Interrupt */ + OTG_FS_IRQn = 83, /* OTGFS global Interrupt */ + USBHSWakeup_IRQn = 84, /* USBHS WakeUp Interrupt */ + USBHS_IRQn = 85, /* USBHS global Interrupt */ + DVP_IRQn = 86, /* DVP global Interrupt */ + UART6_IRQn = 87, /* UART6 global Interrupt */ + UART7_IRQn = 88, /* UART7 global Interrupt */ + UART8_IRQn = 89, /* UART8 global Interrupt */ + TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */ + TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */ + TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */ + TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */ + TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */ + TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */ + TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */ + TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */ + DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */ + DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */ + DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */ + DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */ + DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */ + +#endif +} IRQn_Type; + +#define HardFault_IRQn EXC_IRQn +#define ADC1_2_IRQn ADC_IRQn + + +#include +#include "core_riscv.h" + + + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13[5]; + __IO uint16_t DATAR11; + uint16_t RESERVED14; + __IO uint16_t DATAR12; + uint16_t RESERVED15; + __IO uint16_t DATAR13; + uint16_t RESERVED16; + __IO uint16_t DATAR14; + uint16_t RESERVED17; + __IO uint16_t DATAR15; + uint16_t RESERVED18; + __IO uint16_t DATAR16; + uint16_t RESERVED19; + __IO uint16_t DATAR17; + uint16_t RESERVED20; + __IO uint16_t DATAR18; + uint16_t RESERVED21; + __IO uint16_t DATAR19; + uint16_t RESERVED22; + __IO uint16_t DATAR20; + uint16_t RESERVED23; + __IO uint16_t DATAR21; + uint16_t RESERVED24; + __IO uint16_t DATAR22; + uint16_t RESERVED25; + __IO uint16_t DATAR23; + uint16_t RESERVED26; + __IO uint16_t DATAR24; + uint16_t RESERVED27; + __IO uint16_t DATAR25; + uint16_t RESERVED28; + __IO uint16_t DATAR26; + uint16_t RESERVED29; + __IO uint16_t DATAR27; + uint16_t RESERVED30; + __IO uint16_t DATAR28; + uint16_t RESERVED31; + __IO uint16_t DATAR29; + uint16_t RESERVED32; + __IO uint16_t DATAR30; + uint16_t RESERVED33; + __IO uint16_t DATAR31; + uint16_t RESERVED34; + __IO uint16_t DATAR32; + uint16_t RESERVED35; + __IO uint16_t DATAR33; + uint16_t RESERVED36; + __IO uint16_t DATAR34; + uint16_t RESERVED37; + __IO uint16_t DATAR35; + uint16_t RESERVED38; + __IO uint16_t DATAR36; + uint16_t RESERVED39; + __IO uint16_t DATAR37; + uint16_t RESERVED40; + __IO uint16_t DATAR38; + uint16_t RESERVED41; + __IO uint16_t DATAR39; + uint16_t RESERVED42; + __IO uint16_t DATAR40; + uint16_t RESERVED43; + __IO uint16_t DATAR41; + uint16_t RESERVED44; + __IO uint16_t DATAR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/* Controller Area Network TxMailBox */ +typedef struct +{ + __IO uint32_t TXMIR; + __IO uint32_t TXMDTR; + __IO uint32_t TXMDLR; + __IO uint32_t TXMDHR; +} CAN_TxMailBox_TypeDef; + +/* Controller Area Network FIFOMailBox */ +typedef struct +{ + __IO uint32_t RXMIR; + __IO uint32_t RXMDTR; + __IO uint32_t RXMDLR; + __IO uint32_t RXMDHR; +} CAN_FIFOMailBox_TypeDef; + +/* Controller Area Network FilterRegister */ +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/* Controller Area Network */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t STATR; + __IO uint32_t TSTATR; + __IO uint32_t RFIFO0; + __IO uint32_t RFIFO1; + __IO uint32_t INTENR; + __IO uint32_t ERRSR; + __IO uint32_t BTIMR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FCTLR; + __IO uint32_t FMCFGR; + uint32_t RESERVED2; + __IO uint32_t FSCFGR; + uint32_t RESERVED3; + __IO uint32_t FAFIFOR; + uint32_t RESERVED4; + __IO uint32_t FWR; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[28]; +} CAN_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + +/* Digital to Analog Converter */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SWTR; + __IO uint32_t R12BDHR1; + __IO uint32_t L12BDHR1; + __IO uint32_t R8BDHR1; + __IO uint32_t R12BDHR2; + __IO uint32_t L12BDHR2; + __IO uint32_t R8BDHR2; + __IO uint32_t RD12BDHR; + __IO uint32_t LD12BDHR; + __IO uint32_t RD8BDHR; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + +/* DMA Channel Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* FSMC Bank1 Registers */ +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/* FSMC Bank1E Registers */ +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/* FSMC Bank2 Registers */ +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; + + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + +/* SDIO Registers */ +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DMACFGR; + uint16_t RESERVED18; + __IO uint16_t DMAADR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* OPA Registers */ +typedef struct +{ + __IO uint32_t CR; +} OPA_TypeDef; + +/* RNG Registers */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t DR; +} RNG_TypeDef; + +/* DVP Registers */ +typedef struct +{ + __IO uint8_t CR0; + __IO uint8_t CR1; + __IO uint8_t IER; + __IO uint8_t Reserved0; + __IO uint16_t ROW_NUM; + __IO uint16_t COL_NUM; + __IO uint32_t DMA_BUF0; + __IO uint32_t DMA_BUF1; + __IO uint8_t IFR; + __IO uint8_t STATUS; + __IO uint16_t Reserved1; + __IO uint16_t ROW_CNT; + __IO uint16_t Reserved2; + __IO uint16_t HOFFCNT; + __IO uint16_t VST; + __IO uint16_t CAPCNT; + __IO uint16_t VLINE; + __IO uint32_t DR; +} DVP_TypeDef; + +/* USBHS Registers */ +typedef struct +{ + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t ENDP_CONFIG; + __IO uint32_t ENDP_TYPE; + __IO uint32_t BUF_MODE; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_RX_DMA; + __IO uint32_t UEP2_RX_DMA; + __IO uint32_t UEP3_RX_DMA; + __IO uint32_t UEP4_RX_DMA; + __IO uint32_t UEP5_RX_DMA; + __IO uint32_t UEP6_RX_DMA; + __IO uint32_t UEP7_RX_DMA; + __IO uint32_t UEP8_RX_DMA; + __IO uint32_t UEP9_RX_DMA; + __IO uint32_t UEP10_RX_DMA; + __IO uint32_t UEP11_RX_DMA; + __IO uint32_t UEP12_RX_DMA; + __IO uint32_t UEP13_RX_DMA; + __IO uint32_t UEP14_RX_DMA; + __IO uint32_t UEP15_RX_DMA; + __IO uint32_t UEP1_TX_DMA; + __IO uint32_t UEP2_TX_DMA; + __IO uint32_t UEP3_TX_DMA; + __IO uint32_t UEP4_TX_DMA; + __IO uint32_t UEP5_TX_DMA; + __IO uint32_t UEP6_TX_DMA; + __IO uint32_t UEP7_TX_DMA; + __IO uint32_t UEP8_TX_DMA; + __IO uint32_t UEP9_TX_DMA; + __IO uint32_t UEP10_TX_DMA; + __IO uint32_t UEP11_TX_DMA; + __IO uint32_t UEP12_TX_DMA; + __IO uint32_t UEP13_TX_DMA; + __IO uint32_t UEP14_TX_DMA; + __IO uint32_t UEP15_TX_DMA; + __IO uint16_t UEP0_MAX_LEN; + __IO uint16_t RESERVED2; + __IO uint16_t UEP1_MAX_LEN; + __IO uint16_t RESERVED3; + __IO uint16_t UEP2_MAX_LEN; + __IO uint16_t RESERVED4; + __IO uint16_t UEP3_MAX_LEN; + __IO uint16_t RESERVED5; + __IO uint16_t UEP4_MAX_LEN; + __IO uint16_t RESERVED6; + __IO uint16_t UEP5_MAX_LEN; + __IO uint16_t RESERVED7; + __IO uint16_t UEP6_MAX_LEN; + __IO uint16_t RESERVED8; + __IO uint16_t UEP7_MAX_LEN; + __IO uint16_t RESERVED9; + __IO uint16_t UEP8_MAX_LEN; + __IO uint16_t RESERVED10; + __IO uint16_t UEP9_MAX_LEN; + __IO uint16_t RESERVED11; + __IO uint16_t UEP10_MAX_LEN; + __IO uint16_t RESERVED12; + __IO uint16_t UEP11_MAX_LEN; + __IO uint16_t RESERVED13; + __IO uint16_t UEP12_MAX_LEN; + __IO uint16_t RESERVED14; + __IO uint16_t UEP13_MAX_LEN; + __IO uint16_t RESERVED15; + __IO uint16_t UEP14_MAX_LEN; + __IO uint16_t RESERVED16; + __IO uint16_t UEP15_MAX_LEN; + __IO uint16_t RESERVED17; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint16_t UEP8_TX_LEN; + __IO uint8_t UEP8_TX_CTRL; + __IO uint8_t UEP8_RX_CTRL; + __IO uint16_t UEP9_TX_LEN; + __IO uint8_t UEP9_TX_CTRL; + __IO uint8_t UEP9_RX_CTRL; + __IO uint16_t UEP10_TX_LEN; + __IO uint8_t UEP10_TX_CTRL; + __IO uint8_t UEP10_RX_CTRL; + __IO uint16_t UEP11_TX_LEN; + __IO uint8_t UEP11_TX_CTRL; + __IO uint8_t UEP11_RX_CTRL; + __IO uint16_t UEP12_TX_LEN; + __IO uint8_t UEP12_TX_CTRL; + __IO uint8_t UEP12_RX_CTRL; + __IO uint16_t UEP13_TX_LEN; + __IO uint8_t UEP13_TX_CTRL; + __IO uint8_t UEP13_RX_CTRL; + __IO uint16_t UEP14_TX_LEN; + __IO uint8_t UEP14_TX_CTRL; + __IO uint8_t UEP14_RX_CTRL; + __IO uint16_t UEP15_TX_LEN; + __IO uint8_t UEP15_TX_CTRL; + __IO uint8_t UEP15_RX_CTRL; +} USBHSD_TypeDef; + +typedef struct __attribute__((packed)) +{ + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t HOST_EP_CONFIG; + __IO uint32_t HOST_EP_TYPE; + __IO uint32_t RESERVED2; + __IO uint32_t RESERVED3; + __IO uint32_t RESERVED4; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t RESERVED5; + __IO uint32_t RESERVED6; + __IO uint32_t RESERVED7; + __IO uint32_t RESERVED8; + __IO uint32_t RESERVED9; + __IO uint32_t RESERVED10; + __IO uint32_t RESERVED11; + __IO uint32_t RESERVED12; + __IO uint32_t RESERVED13; + __IO uint32_t RESERVED14; + __IO uint32_t RESERVED15; + __IO uint32_t RESERVED16; + __IO uint32_t RESERVED17; + __IO uint32_t RESERVED18; + __IO uint32_t RESERVED19; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t RESERVED20; + __IO uint32_t RESERVED21; + __IO uint32_t RESERVED22; + __IO uint32_t RESERVED23; + __IO uint32_t RESERVED24; + __IO uint32_t RESERVED25; + __IO uint32_t RESERVED26; + __IO uint32_t RESERVED27; + __IO uint32_t RESERVED28; + __IO uint32_t RESERVED29; + __IO uint32_t RESERVED30; + __IO uint32_t RESERVED31; + __IO uint32_t RESERVED32; + __IO uint32_t RESERVED33; + __IO uint16_t HOST_RX_MAX_LEN; + __IO uint16_t RESERVED34; + __IO uint32_t RESERVED35; + __IO uint32_t RESERVED36; + __IO uint32_t RESERVED37; + __IO uint32_t RESERVED38; + __IO uint32_t RESERVED39; + __IO uint32_t RESERVED40; + __IO uint32_t RESERVED41; + __IO uint32_t RESERVED42; + __IO uint32_t RESERVED43; + __IO uint32_t RESERVED44; + __IO uint32_t RESERVED45; + __IO uint32_t RESERVED46; + __IO uint32_t RESERVED47; + __IO uint32_t RESERVED48; + __IO uint32_t RESERVED49; + __IO uint8_t HOST_EP_PID; + __IO uint8_t RESERVED50; + __IO uint8_t RESERVED51; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t RESERVED52; + __IO uint16_t HOST_SPLIT_DATA; +} USBHSH_TypeDef; + + +/* USBOTG_FS Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint32_t Reserve2; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +}USBOTG_FS_TypeDef; + +typedef struct __attribute__((packed)) +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t Reserve2; + __IO uint8_t HOST_EP_MOD; + __IO uint16_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t Reserve6; + __IO uint32_t Reserve7; + __IO uint32_t Reserve8; + __IO uint32_t Reserve9; + __IO uint32_t Reserve10; + __IO uint16_t Reserve11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + __IO uint8_t Reserve12; + __IO uint8_t Reserve13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t Reserve14; + __IO uint32_t Reserve15; + __IO uint32_t Reserve16; + __IO uint32_t Reserve17; + __IO uint32_t Reserve18; + __IO uint32_t Reserve19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +}USBOTGH_FS_TypeDef; + +/* Ethernet MAC */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + + + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /* FSMC registers base address */ + + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define UART6_BASE (APB1PERIPH_BASE + 0x1800) +#define UART7_BASE (APB1PERIPH_BASE + 0x1C00) +#define UART8_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) +#define SDIO_BASE (APB2PERIPH_BASE + 0x8000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x046C) +#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x0480) +#define DMA2_Channel8_BASE (AHBPERIPH_BASE + 0x0490) +#define DMA2_Channel9_BASE (AHBPERIPH_BASE + 0x04A0) +#define DMA2_Channel10_BASE (AHBPERIPH_BASE + 0x04B0) +#define DMA2_Channel11_BASE (AHBPERIPH_BASE + 0x04C0) +#define DMA2_EXTEN_BASE (AHBPERIPH_BASE + 0x04D0) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define USBHS_BASE (AHBPERIPH_BASE + 0x3400) +#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) +#define OPA_BASE (AHBPERIPH_BASE + 0x3804) +#define RNG_BASE (AHBPERIPH_BASE + 0x3C00) + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define USBFS_BASE ((uint32_t)0x50000000) +#define DVP_BASE ((uint32_t)0x50050000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) + +#define OB_BASE ((uint32_t)0x1FFFF800) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define UART6 ((USART_TypeDef *) UART6_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) + +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TKey1 ((ADC_TypeDef *) ADC1_BASE) +#define TKey2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_EXTEN ((DMA_TypeDef *) DMA2_EXTEN_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) +#define DMA2_Channel9 ((DMA_Channel_TypeDef *) DMA2_Channel9_BASE) +#define DMA2_Channel10 ((DMA_Channel_TypeDef *) DMA2_Channel10_BASE) +#define DMA2_Channel11 ((DMA_Channel_TypeDef *) DMA2_Channel11_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define USBHSD ((USBHSD_TypeDef *) USBHS_BASE) +#define USBHSH ((USBHSH_TypeDef *) USBHS_BASE) +#define USBOTG_FS ((USBOTG_FS_TypeDef *)USBFS_BASE) +#define USBOTG_H_FS ((USBOTGH_FS_TypeDef *)USBFS_BASE) +#define EXTEN ((EXTEN_TypeDef *) EXTEN_BASE) +#define OPA ((OPA_TypeDef *) OPA_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) + +#define DVP ((DVP_TypeDef *) DVP_BASE) + +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) + +#define OB ((OB_TypeDef *) OB_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR11 register *******************/ +#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR12 register *******************/ +#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR13 register *******************/ +#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR14 register *******************/ +#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR15 register *******************/ +#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR16 register *******************/ +#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR17 register *******************/ +#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_DATAR18 register ********************/ +#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR19 register *******************/ +#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR20 register *******************/ +#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR21 register *******************/ +#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR22 register *******************/ +#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR23 register *******************/ +#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR24 register *******************/ +#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR25 register *******************/ +#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR26 register *******************/ +#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR27 register *******************/ +#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR28 register *******************/ +#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR29 register *******************/ +#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR30 register *******************/ +#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR31 register *******************/ +#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR32 register *******************/ +#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR33 register *******************/ +#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR34 register *******************/ +#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR35 register *******************/ +#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR36 register *******************/ +#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR37 register *******************/ +#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR38 register *******************/ +#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR39 register *******************/ +#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR40 register *******************/ +#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR41 register *******************/ +#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR42 register *******************/ +#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* Controller Area Network */ +/******************************************************************************/ + +/******************* Bit definition for CAN_CTLR register ********************/ +#define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */ +#define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */ +#define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */ +#define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */ +#define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */ +#define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */ +#define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */ +#define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */ +#define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */ + +/******************* Bit definition for CAN_STATR register ********************/ +#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ +#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ +#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ +#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ +#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ +#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ +#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ +#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTATR register ********************/ +#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ + +#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFIFO0 register *******************/ +#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ +#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ +#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ +#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFIFO1 register *******************/ +#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ +#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ +#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ +#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTENR register *******************/ +#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ +#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ERRSR register *******************/ +#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ +#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ +#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ + +#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ + +#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ + +/******************* Bit definition for CAN_BTIMR register ********************/ +#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) /* Baud Rate Prescaler */ +#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) /* Time Segment 1 */ +#define CAN_BTIMR_TS2 ((uint32_t)0x00700000) /* Time Segment 2 */ +#define CAN_BTIMR_SJW ((uint32_t)0x03000000) /* Resynchronization Jump Width */ +#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */ +#define CAN_BTIMR_SILM ((uint32_t)0x80000000) /* Silent Mode */ + +/****************** Bit definition for CAN_TXMI0R register ********************/ +#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TXMDT0R register *******************/ +#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/****************** Bit definition for CAN_TXMDL0R register *******************/ +#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/****************** Bit definition for CAN_TXMDH0R register *******************/ +#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI1R register *******************/ +#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT1R register ******************/ +#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL1R register ******************/ +#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH1R register ******************/ +#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI2R register *******************/ +#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT2R register ******************/ +#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL2R register ******************/ +#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH2R register ******************/ +#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI0R register *******************/ +#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT0R register ******************/ +#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL0R register ******************/ +#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH0R register ******************/ +#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI1R register *******************/ +#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT1R register ******************/ +#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL1R register ******************/ +#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH1R register ******************/ +#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_FCTLR register ********************/ +#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ + +/******************* Bit definition for CAN_FMCFGR register *******************/ +#define CAN_FMCFGR_FBM ((uint16_t)0x3FFF) /* Filter Mode */ +#define CAN_FMCFGR_FBM0 ((uint16_t)0x0001) /* Filter Init Mode bit 0 */ +#define CAN_FMCFGR_FBM1 ((uint16_t)0x0002) /* Filter Init Mode bit 1 */ +#define CAN_FMCFGR_FBM2 ((uint16_t)0x0004) /* Filter Init Mode bit 2 */ +#define CAN_FMCFGR_FBM3 ((uint16_t)0x0008) /* Filter Init Mode bit 3 */ +#define CAN_FMCFGR_FBM4 ((uint16_t)0x0010) /* Filter Init Mode bit 4 */ +#define CAN_FMCFGR_FBM5 ((uint16_t)0x0020) /* Filter Init Mode bit 5 */ +#define CAN_FMCFGR_FBM6 ((uint16_t)0x0040) /* Filter Init Mode bit 6 */ +#define CAN_FMCFGR_FBM7 ((uint16_t)0x0080) /* Filter Init Mode bit 7 */ +#define CAN_FMCFGR_FBM8 ((uint16_t)0x0100) /* Filter Init Mode bit 8 */ +#define CAN_FMCFGR_FBM9 ((uint16_t)0x0200) /* Filter Init Mode bit 9 */ +#define CAN_FMCFGR_FBM10 ((uint16_t)0x0400) /* Filter Init Mode bit 10 */ +#define CAN_FMCFGR_FBM11 ((uint16_t)0x0800) /* Filter Init Mode bit 11 */ +#define CAN_FMCFGR_FBM12 ((uint16_t)0x1000) /* Filter Init Mode bit 12 */ +#define CAN_FMCFGR_FBM13 ((uint16_t)0x2000) /* Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FSCFGR register *******************/ +#define CAN_FSCFGR_FSC ((uint16_t)0x3FFF) /* Filter Scale Configuration */ +#define CAN_FSCFGR_FSC0 ((uint16_t)0x0001) /* Filter Scale Configuration bit 0 */ +#define CAN_FSCFGR_FSC1 ((uint16_t)0x0002) /* Filter Scale Configuration bit 1 */ +#define CAN_FSCFGR_FSC2 ((uint16_t)0x0004) /* Filter Scale Configuration bit 2 */ +#define CAN_FSCFGR_FSC3 ((uint16_t)0x0008) /* Filter Scale Configuration bit 3 */ +#define CAN_FSCFGR_FSC4 ((uint16_t)0x0010) /* Filter Scale Configuration bit 4 */ +#define CAN_FSCFGR_FSC5 ((uint16_t)0x0020) /* Filter Scale Configuration bit 5 */ +#define CAN_FSCFGR_FSC6 ((uint16_t)0x0040) /* Filter Scale Configuration bit 6 */ +#define CAN_FSCFGR_FSC7 ((uint16_t)0x0080) /* Filter Scale Configuration bit 7 */ +#define CAN_FSCFGR_FSC8 ((uint16_t)0x0100) /* Filter Scale Configuration bit 8 */ +#define CAN_FSCFGR_FSC9 ((uint16_t)0x0200) /* Filter Scale Configuration bit 9 */ +#define CAN_FSCFGR_FSC10 ((uint16_t)0x0400) /* Filter Scale Configuration bit 10 */ +#define CAN_FSCFGR_FSC11 ((uint16_t)0x0800) /* Filter Scale Configuration bit 11 */ +#define CAN_FSCFGR_FSC12 ((uint16_t)0x1000) /* Filter Scale Configuration bit 12 */ +#define CAN_FSCFGR_FSC13 ((uint16_t)0x2000) /* Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FAFIFOR register *******************/ +#define CAN_FAFIFOR_FFA ((uint16_t)0x3FFF) /* Filter FIFO Assignment */ +#define CAN_FAFIFOR_FFA0 ((uint16_t)0x0001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FAFIFOR_FFA1 ((uint16_t)0x0002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FAFIFOR_FFA2 ((uint16_t)0x0004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FAFIFOR_FFA3 ((uint16_t)0x0008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FAFIFOR_FFA4 ((uint16_t)0x0010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FAFIFOR_FFA5 ((uint16_t)0x0020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FAFIFOR_FFA6 ((uint16_t)0x0040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FAFIFOR_FFA7 ((uint16_t)0x0080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FAFIFOR_FFA8 ((uint16_t)0x0100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FAFIFOR_FFA9 ((uint16_t)0x0200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FAFIFOR_FFA10 ((uint16_t)0x0400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FAFIFOR_FFA11 ((uint16_t)0x0800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FAFIFOR_FFA12 ((uint16_t)0x1000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FAFIFOR_FFA13 ((uint16_t)0x2000) /* Filter FIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FWR register *******************/ +#define CAN_FWR_FACT ((uint16_t)0x3FFF) /* Filter Active */ +#define CAN_FWR_FACT0 ((uint16_t)0x0001) /* Filter 0 Active */ +#define CAN_FWR_FACT1 ((uint16_t)0x0002) /* Filter 1 Active */ +#define CAN_FWR_FACT2 ((uint16_t)0x0004) /* Filter 2 Active */ +#define CAN_FWR_FACT3 ((uint16_t)0x0008) /* Filter 3 Active */ +#define CAN_FWR_FACT4 ((uint16_t)0x0010) /* Filter 4 Active */ +#define CAN_FWR_FACT5 ((uint16_t)0x0020) /* Filter 5 Active */ +#define CAN_FWR_FACT6 ((uint16_t)0x0040) /* Filter 6 Active */ +#define CAN_FWR_FACT7 ((uint16_t)0x0080) /* Filter 7 Active */ +#define CAN_FWR_FACT8 ((uint16_t)0x0100) /* Filter 8 Active */ +#define CAN_FWR_FACT9 ((uint16_t)0x0200) /* Filter 9 Active */ +#define CAN_FWR_FACT10 ((uint16_t)0x0400) /* Filter 10 Active */ +#define CAN_FWR_FACT11 ((uint16_t)0x0800) /* Filter 11 Active */ +#define CAN_FWR_FACT12 ((uint16_t)0x1000) /* Filter 12 Active */ +#define CAN_FWR_FACT13 ((uint16_t)0x2000) /* Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + + + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + +/******************************************************************************/ +/* Digital to Analog Converter */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CTLR register ********************/ +#define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */ +#define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */ +#define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */ + +#define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */ +#define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */ + +#define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */ +#define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */ +#define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */ +#define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */ + +#define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */ +#define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */ +#define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */ + +#define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */ + +#define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTR register ******************/ +#define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */ +#define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */ + +/***************** Bit definition for DAC_R12BDHR1 register ******************/ +#define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR1 register ******************/ +#define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR1 register ******************/ +#define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_R12BDHR2 register ******************/ +#define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR2 register ******************/ +#define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR2 register ******************/ +#define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_RD12BDHR register ******************/ +#define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ +#define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_LD12BDHR register ******************/ +#define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ +#define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_RD8BDHR register ******************/ +#define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */ +#define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + +#define DMA_GIF8 ((uint32_t)0x00000001) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x00000002) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x00000004) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x00000008) /* Channel 8 Transfer Error flag */ +#define DMA_GIF9 ((uint32_t)0x00000010) /* Channel 9 Global interrupt flag */ +#define DMA_TCIF9 ((uint32_t)0x00000020) /* Channel 9 Transfer Complete flag */ +#define DMA_HTIF9 ((uint32_t)0x00000040) /* Channel 9 Half Transfer flag */ +#define DMA_TEIF9 ((uint32_t)0x00000080) /* Channel 9 Transfer Error flag */ +#define DMA_GIF10 ((uint32_t)0x00000100) /* Channel 10 Global interrupt flag */ +#define DMA_TCIF10 ((uint32_t)0x00000200) /* Channel 10 Transfer Complete flag */ +#define DMA_HTIF10 ((uint32_t)0x00000400) /* Channel 10 Half Transfer flag */ +#define DMA_TEIF10 ((uint32_t)0x00000800) /* Channel 10 Transfer Error flag */ +#define DMA_GIF11 ((uint32_t)0x00001000) /* Channel 11 Global interrupt flag */ +#define DMA_TCIF11 ((uint32_t)0x00002000) /* Channel 11 Transfer Complete flag */ +#define DMA_HTIF11 ((uint32_t)0x00004000) /* Channel 11 Half Transfer flag */ +#define DMA_TEIF11 ((uint32_t)0x00008000) /* Channel 11 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + + +/******************* Bit definition for FLASH_ACTLR register ******************/ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */ +#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */ +#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ +#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ +#define FLASH_CTLR_OPTWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FAST_LOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */ +#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */ +#define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */ +#define FLASH_CTLR_PAGE_BER64 ((uint32_t)0x00080000) /* Block Erase 64K */ +#define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /* BFB2 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ +#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */ +#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */ +#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */ +#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */ +#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */ +#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */ +#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */ +#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */ + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + + + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +/* for other CH32V30x */ +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ +#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ +/* for CH32V307 */ +#define RCC_PLLMULL18_EXTEN ((uint32_t)0x00000000) /* PLL input clock*18 */ +#define RCC_PLLMULL3_EXTEN ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4_EXTEN ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5_EXTEN ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6_EXTEN ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7_EXTEN ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8_EXTEN ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9_EXTEN ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10_EXTEN ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11_EXTEN ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12_EXTEN ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13_EXTEN ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14_EXTEN ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL6_5_EXTEN ((uint32_t)0x00340000) /* PLL input clock*6.5 */ +#define RCC_PLLMULL15_EXTEN ((uint32_t)0x00380000) /* PLL input clock*15 */ +#define RCC_PLLMULL16_EXTEN ((uint32_t)0x003C0000) /* PLL input clock*16 */ + +#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ + + +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ + + +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ + +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ + + +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + + +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ + +#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ +#define RCC_FLITFEN ((uint16_t)0x0010) /* FLITF clock enable */ +#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ +#define RCC_USBHD ((uint16_t)0x1000) + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ + +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ + + +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ + +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + + +#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */ +#define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */ +#define RCC_RTCSEL_HSE ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************************************************************************/ +/* RNG */ +/******************************************************************************/ +/******************** Bit definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN ((uint32_t)0x00000004) +#define RNG_CR_IE ((uint32_t)0x00000008) + +/******************** Bit definition for RNG_SR register *******************/ +#define RNG_SR_DRDY ((uint32_t)0x00000001) +#define RNG_SR_CECS ((uint32_t)0x00000002) +#define RNG_SR_SECS ((uint32_t)0x00000004) +#define RNG_SR_CEIS ((uint32_t)0x00000020) +#define RNG_SR_SEIS ((uint32_t)0x00000040) + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCH register *******************/ +#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ +#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ +#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */ +#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */ +#define EXTEN_ETH_10M_EN ((uint32_t)0x00000004) /* Bit 2 */ +#define EXTEN_ETH_RGMII_SEL ((uint32_t)0x00000008) /* Bit 3 */ +#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + +#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */ +#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ +#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define EXTEN_LDO_TRIM ((uint32_t)0x00000C00) /* LDO_TRIM[1:0] bits */ +#define EXTEN_LDO_TRIM0 ((uint32_t)0x00000400) /* Bit 0 */ +#define EXTEN_LDO_TRIM1 ((uint32_t)0x00000800) /* Bit 1 */ + + +/******************************************************************************/ +/* DVP */ +/******************************************************************************/ + +/******************* Bit definition for DVP_CR0 register ********************/ +#define RB_DVP_ENABLE 0x01 // RW, DVP enable +#define RB_DVP_V_POLAR 0x02 // RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_H_POLAR 0x04 // RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_P_POLAR 0x08 // RW, DVP PCLK polarity control: 1 = invert, 0 = not invert +#define RB_DVP_MSK_DAT_MOD 0x30 +#define RB_DVP_D8_MOD 0x00 // RW, DVP 8bits data mode +#define RB_DVP_D10_MOD 0x10 // RW, DVP 10bits data mode +#define RB_DVP_D12_MOD 0x20 // RW, DVP 12bits data mode +#define RB_DVP_JPEG 0x40 // RW, DVP JPEG mode + +/******************* Bit definition for DVP_CR1 register ********************/ +#define RB_DVP_DMA_EN 0x01 // RW, DVP dma enable +#define RB_DVP_ALL_CLR 0x02 // RW, DVP all clear, high action +#define RB_DVP_RCV_CLR 0x04 // RW, DVP receive logic clear, high action +#define RB_DVP_BUF_TOG 0x08 // RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0 +#define RB_DVP_CM 0x10 // RW, DVP capture mode +#define RB_DVP_CROP 0x20 // RW, DVP Crop feature enable +#define RB_DVP_FCRC 0xC0 // RW, DVP frame capture rate control: +#define DVP_RATE_100P 0x00 //00 = every frame captured (100%) +#define DVP_RATE_50P 0x40 //01 = every alternate frame captured (50%) +#define DVP_RATE_25P 0x80 //10 = one frame in four frame captured (25%) + +/******************* Bit definition for DVP_IER register ********************/ +#define RB_DVP_IE_STR_FRM 0x01 // RW, DVP frame start interrupt enable +#define RB_DVP_IE_ROW_DONE 0x02 // RW, DVP row received done interrupt enable +#define RB_DVP_IE_FRM_DONE 0x04 // RW, DVP frame received done interrupt enable +#define RB_DVP_IE_FIFO_OV 0x08 // RW, DVP receive fifo overflow interrupt enable +#define RB_DVP_IE_STP_FRM 0x10 // RW, DVP frame stop interrupt enable + +/******************* Bit definition for DVP_IFR register ********************/ +#define RB_DVP_IF_STR_FRM 0x01 // RW1, interrupt flag for DVP frame start +#define RB_DVP_IF_ROW_DONE 0x02 // RW1, interrupt flag for DVP row receive done +#define RB_DVP_IF_FRM_DONE 0x04 // RW1, interrupt flag for DVP frame receive done +#define RB_DVP_IF_FIFO_OV 0x08 // RW1, interrupt flag for DVP receive fifo overflow +#define RB_DVP_IF_STP_FRM 0x10 // RW1, interrupt flag for DVP frame stop + +/******************* Bit definition for DVP_STATUS register ********************/ +#define RB_DVP_FIFO_RDY 0x01 // RO, DVP receive fifo ready +#define RB_DVP_FIFO_FULL 0x02 // RO, DVP receive fifo full +#define RB_DVP_FIFO_OV 0x04 // RO, DVP receive fifo overflow +#define RB_DVP_MSK_FIFO_CNT 0x70 // RO, DVP receive fifo count + + + + + +#ifdef __cplusplus +} +#endif + +#endif + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_adc.c b/libraries/sdk/Peripheral/ch32v30x_adc.c new file mode 100644 index 0000000..2896a40 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_adc.c @@ -0,0 +1,1180 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_adc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the ADC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_adc.h" +#include "ch32v30x_rcc.h" + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } + else if(ADCx == ADC2) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | + (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_ResetCalibration + * + * @brief Resets the selected ADC calibration registers. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return none + */ +void ADC_ResetCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_RSTCAL_Set; +} + +/********************************************************************* + * @fn ADC_GetResetCalibrationStatus + * + * @brief Gets the selected ADC reset calibration registers status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_StartCalibration + * + * @brief Starts the selected ADC calibration process. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return None + */ +void ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_CAL_Set; +} + +/********************************************************************* + * @fn ADC_GetCalibrationStatus + * + * @brief Gets the selected ADC calibration status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_GetDualModeConversionValue + * + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * + * @return RDATAR_ADDRESS - The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + return (*(__IO uint32_t *)RDATAR_ADDRESS); +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. + * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. + * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. + * ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 - External interrupt + * line 15 event selected. + * ADC_ExternalTrigInjecConv_None: Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 4. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 12bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_TempSensorVrefintCmd + * + * @brief Enables or disables the temperature sensor and Vrefint channel. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADC1->CTLR2 |= CTLR2_TSVREFE_Set; + } + else + { + ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn TempSensor_Volt_To_Temper + * + * @brief Internal Temperature Sensor Voltage to temperature. + * + * @param Value - Voltage Value(mv). + * + * @return Temper - Temperature Value. + */ +s32 TempSensor_Volt_To_Temper(s32 Value) +{ + s32 Temper, Refer_Volt, Refer_Temper; + s32 k = 43; + + Refer_Volt = (s32)((*(u32 *)0x1FFFF720) & 0x0000FFFF); + Refer_Temper = (s32)(((*(u32 *)0x1FFFF720) >> 16) & 0x0000FFFF); + + Temper = Refer_Temper + ((Value - Refer_Volt) * 10 + (k >> 1)) / k; + + return Temper; +} + +/********************************************************************* + * @fn ADC_BufferCmd + * + * @brief Enables or disables the ADCx buffer. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= (1 << 26); + } + else + { + ADCx->CTLR1 &= ~(1 << 26); + } +} + +/********************************************************************* + * @fn Get_CalibrationValue + * + * @brief Get ADCx Calibration Value. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return CalibrationValue + */ +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) +{ + __IO uint8_t i, j; + uint16_t buf[10]; + __IO uint16_t t; + + for(i = 0; i < 10; i++) + { + ADC_ResetCalibration(ADCx); + while(ADC_GetResetCalibrationStatus(ADCx)) + ; + ADC_StartCalibration(ADCx); + while(ADC_GetCalibrationStatus(ADCx)) + ; + buf[i] = ADCx->RDATAR; + } + + for(i = 0; i < 10; i++) + { + for(j = 0; j < 9; j++) + { + if(buf[j] > buf[j + 1]) + { + t = buf[j]; + buf[j] = buf[j + 1]; + buf[j + 1] = t; + } + } + } + + t = 0; + for(i = 0; i < 6; i++) + { + t += buf[i + 2]; + } + + t = (t / 6) + ((t % 6) / 3); + + return (int16_t)(2048 - (int16_t)t); +} diff --git a/libraries/sdk/Peripheral/ch32v30x_adc.h b/libraries/sdk/Peripheral/ch32v30x_adc.h new file mode 100644 index 0000000..f1375b1 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_adc.h @@ -0,0 +1,228 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_adc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* ADC firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_ADC_H +#define __CH32V30x_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ + + uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. + This parameter can be a value of @ref ADC_OutputBuffer */ + + uint32_t ADC_Pga; /* Specifies the PGA gain multiple. + This parameter can be a value of @ref ADC_Pga */ +}ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) + + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +/*ADC_output_buffer*/ +#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) +#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) + +/*ADC_pga*/ +#define ADC_Pga_1 ((uint32_t)0x00000000) +#define ADC_Pga_4 ((uint32_t)0x08000000) +#define ADC_Pga_16 ((uint32_t)0x10000000) +#define ADC_Pga_64 ((uint32_t)0x18000000) + +/* ADC_sampling_time */ +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) + + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + + +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); +s32 TempSensor_Volt_To_Temper(s32 Value); +void ADC_BufferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +int16_t Get_CalibrationValue(ADC_TypeDef* ADCx); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_bkp.c b/libraries/sdk/Peripheral/ch32v30x_bkp.c new file mode 100644 index 0000000..e7420b7 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_bkp.c @@ -0,0 +1,242 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_bkp.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the BKP firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_bkp.h" +#include "ch32v30x_rcc.h" + +/* BKP registers bit mask */ + +/* OCTLR register bit mask */ +#define OCTLR_CAL_MASK ((uint16_t)0xFF80) +#define OCTLR_MASK ((uint16_t)0xFC7F) + +/********************************************************************* + * @fn BKP_DeInit + * + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * + * @return none + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/********************************************************************* + * @fn BKP_TamperPinLevelConfig + * + * @brief Configures the Tamper Pin active level. + * + * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. + * BKP_TamperPinLevel_High - Tamper pin active on high level. + * BKP_TamperPinLevel_Low - Tamper pin active on low level. + * + * @return none + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + if(BKP_TamperPinLevel) + { + BKP->TPCTLR |= (1 << 1); + } + else + { + BKP->TPCTLR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn BKP_TamperPinCmd + * + * @brief Enables or disables the Tamper Pin activation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCTLR |= (1 << 0); + } + else + { + BKP->TPCTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn BKP_ITConfig + * + * @brief Enables or disables the Tamper Pin Interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_ITConfig(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCSR |= (1 << 2); + } + else + { + BKP->TPCSR &= ~(1 << 2); + } +} + +/********************************************************************* + * @fn BKP_RTCOutputConfig + * + * @brief Select the RTC output source to output on the Tamper pin. + * + * @param BKP_RTCOutputSource - specifies the RTC output source. + * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. + * BKP_RTCOutputSource_CalibClock - output the RTC clock with + * frequency divided by 64 on the Tamper pin. + * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal + * on the Tamper pin. + * BKP_RTCOutputSource_Second - output the RTC Second pulse + * signal on the Tamper pin. + * + * @return none + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_MASK; + tmpreg |= BKP_RTCOutputSource; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_SetRTCCalibrationValue + * + * @brief Sets RTC Clock Calibration value. + * + * @param CalibrationValue - specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_CAL_MASK; + tmpreg |= CalibrationValue; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_WriteBackupRegister + * + * @brief Writes user data to the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * Data - data to write. + * + * @return none + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn BKP_ReadBackupRegister + * + * @brief Reads data from the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * This parameter can be BKP_DRx where x=[1, 42]. + * + * @return none + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn BKP_GetFlagStatus + * + * @brief Checks whether the Tamper Pin Event flag is set or not. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus BKP_GetFlagStatus(void) +{ + if(BKP->TPCSR & (1 << 8)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearFlag + * + * @brief Clears Tamper Pin Event pending flag. + * + * @return none + */ +void BKP_ClearFlag(void) +{ + BKP->TPCSR |= BKP_CTE; +} + +/********************************************************************* + * @fn BKP_GetITStatus + * + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * + * @return ITStatus - SET or RESET. + */ +ITStatus BKP_GetITStatus(void) +{ + if(BKP->TPCSR & (1 << 9)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearITPendingBit + * + * @brief Clears Tamper Pin Interrupt pending bit. + * + * @return none + */ +void BKP_ClearITPendingBit(void) +{ + BKP->TPCSR |= BKP_CTI; +} diff --git a/libraries/sdk/Peripheral/ch32v30x_bkp.h b/libraries/sdk/Peripheral/ch32v30x_bkp.h new file mode 100644 index 0000000..16daced --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_bkp.h @@ -0,0 +1,97 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_bkp.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* BKP firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_BKP_H +#define __CH32V30x_BKP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* Tamper_Pin_active_level */ +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) + +/* RTC_output_source_to_output_on_the_Tamper_pin */ +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) + +/* Data_Backup_Register */ +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_can.c b/libraries/sdk/Peripheral/ch32v30x_can.c new file mode 100644 index 0000000..9b64390 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_can.c @@ -0,0 +1,1207 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_can.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the CAN firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_can.h" +#include "ch32v30x_rcc.h" + +/* CAN CTLR Register bits */ +#define CTLR_DBF ((uint32_t)0x00010000) + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) + +/* CAN FCTLR Register bits */ +#define FCTLR_FINIT ((uint32_t)0x00000001) + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + +/* Flags in TSTATR register */ +#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) +/* Flags in RFIFO1 register */ +#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) +/* Flags in RFIFO0 register */ +#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) +/* Flags in STATR register */ +#define CAN_FLAGS_STATR ((uint32_t)0x01000000) +/* Flags in ERRSR register */ +#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +#define CAN_MODE_MASK ((uint32_t)0x00000003) + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/********************************************************************* + * @fn CAN_DeInit + * + * @brief Deinitializes the CAN peripheral registers to their default reset + * values. + * + * @param CANx - where x can be 1 or 2 to select the CAN peripheral. + * + * @return none + */ +void CAN_DeInit(CAN_TypeDef *CANx) +{ + if(CANx == CAN1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/********************************************************************* + * @fn CAN_Init + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_InitStruct - pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * + * @return InitStatus - CAN InitStatus state. + * CAN_InitStatus_Failed. + * CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + + CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); + CANx->CTLR |= CAN_CTLR_INRQ; + + while(((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + if(CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; + } + + if(CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_ABOM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; + } + + if(CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_AWUM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; + } + + if(CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->CTLR |= CAN_CTLR_NART; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; + } + + if(CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_RFLM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFLM; + } + + if(CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TXFP; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; + } + + CANx->BTIMR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; + wait_ack = 0; + + while(((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success; + } + } + + return InitStatus; +} + +/********************************************************************* + * @fn CAN_FilterInit + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * + * @param CAN_FilterInitStruct - pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration information. + * + * @return none + */ +void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FWR &= ~(uint32_t)filter_number_bit_pos; + + if(CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + CAN1->FSCFGR &= ~(uint32_t)filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if(CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + CAN1->FSCFGR |= filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + if(CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos; + } + else + { + CAN1->FMCFGR |= (uint32_t)filter_number_bit_pos; + } + + if(CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + CAN1->FAFIFOR &= ~(uint32_t)filter_number_bit_pos; + } + + if(CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + CAN1->FAFIFOR |= (uint32_t)filter_number_bit_pos; + } + + if(CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FWR |= filter_number_bit_pos; + } + + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_StructInit + * + * @brief Fills each CAN_InitStruct member with its default value. + * + * @param CAN_InitStruct - pointer to a CAN_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct) +{ + CAN_InitStruct->CAN_TTCM = DISABLE; + CAN_InitStruct->CAN_ABOM = DISABLE; + CAN_InitStruct->CAN_AWUM = DISABLE; + CAN_InitStruct->CAN_NART = DISABLE; + CAN_InitStruct->CAN_RFLM = DISABLE; + CAN_InitStruct->CAN_TXFP = DISABLE; + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + CAN_InitStruct->CAN_Prescaler = 1; +} + +/********************************************************************* + * @fn CAN_SlaveStartBank + * + * @brief This function applies only to CH32 Connectivity line devices. + * + * @param CAN_BankNumber - Select the start slave bank filter from 1..27. + * + * @return none + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FCTLR &= (uint32_t)0xFFFFC0F1; + CAN1->FCTLR |= (uint32_t)(CAN_BankNumber) << 8; + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_DBGFreeze + * + * @brief Enables or disables the DBG Freeze for CAN. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + CANx->CTLR |= CTLR_DBF; + } + else + { + CANx->CTLR &= ~CTLR_DBF; + } +} + +/********************************************************************* + * @fn CAN_TTComModeCmd + * + * @brief Enables or disabes the CAN Time TriggerOperation communication mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + + CANx->sTxMailBox[0].TXMDTR |= ((uint32_t)CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR |= ((uint32_t)CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR |= ((uint32_t)CAN_TXMDT2R_TGT); + } + else + { + CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTCM); + + CANx->sTxMailBox[0].TXMDTR &= ((uint32_t)~CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR &= ((uint32_t)~CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR &= ((uint32_t)~CAN_TXMDT2R_TGT); + } +} + +/********************************************************************* + * @fn CAN_Transmit + * + * @brief Initiates the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TxMessage - pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * + * @return transmit_mailbox - The number of the mailbox that is used for + * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage) +{ + uint8_t transmit_mailbox = 0; + + if((CANx->TSTATR & CAN_TSTATR_TME0) == CAN_TSTATR_TME0) + { + transmit_mailbox = 0; + } + else if((CANx->TSTATR & CAN_TSTATR_TME1) == CAN_TSTATR_TME1) + { + transmit_mailbox = 1; + } + else if((CANx->TSTATR & CAN_TSTATR_TME2) == CAN_TSTATR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if(transmit_mailbox != CAN_TxStatus_NoMailBox) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; + if(TxMessage->IDE == CAN_Id_Standard) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | + TxMessage->RTR); + } + else + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | + TxMessage->IDE | + TxMessage->RTR); + } + + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; + + CANx->sTxMailBox[transmit_mailbox].TXMDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TXMDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; + } + + return transmit_mailbox; +} + +/********************************************************************* + * @fn CAN_TransmitStatus + * + * @brief Checks the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TransmitMailbox - the number of the mailbox that is used for + * transmission. + * + * @return state - + * CAN_TxStatus_Ok. + * CAN_TxStatus_Failed. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + switch(TransmitMailbox) + { + case(CAN_TXMAILBOX_0): + state = CANx->TSTATR & (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0); + break; + + case(CAN_TXMAILBOX_1): + state = CANx->TSTATR & (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1); + break; + + case(CAN_TXMAILBOX_2): + state = CANx->TSTATR & (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2); + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + switch(state) + { + case(0x0): + state = CAN_TxStatus_Pending; + break; + + case(CAN_TSTATR_RQCP0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Failed; + break; + + case(CAN_TSTATR_RQCP1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Failed; + break; + + case(CAN_TSTATR_RQCP2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Failed; + break; + + case(CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Ok; + break; + + case(CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Ok; + break; + + case(CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Ok; + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + return (uint8_t)state; +} + +/********************************************************************* + * @fn CAN_CancelTransmit + * + * @brief Cancels a transmit request. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Mailbox - Mailbox number. + * CAN_TXMAILBOX_0. + * CAN_TXMAILBOX_1. + * CAN_TXMAILBOX_2. + * + * @return none + */ +void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox) +{ + switch(Mailbox) + { + case(CAN_TXMAILBOX_0): + CANx->TSTATR |= CAN_TSTATR_ABRQ0; + break; + + case(CAN_TXMAILBOX_1): + CANx->TSTATR |= CAN_TSTATR_ABRQ1; + break; + + case(CAN_TXMAILBOX_2): + CANx->TSTATR |= CAN_TSTATR_ABRQ2; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn CAN_Receive + * + * @brief Receives a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * RxMessage - pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * + * @return none + */ +void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage) +{ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + if(RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 24); + + if(FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_FIFORelease + * + * @brief Releases the specified FIFO. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return none + */ +void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber) +{ + if(FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_MessagePending + * + * @brief Returns the number of pending messages. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return message_pending: which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber) +{ + uint8_t message_pending = 0; + + if(FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RFIFO0 & (uint32_t)0x03); + } + else if(FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RFIFO1 & (uint32_t)0x03); + } + else + { + message_pending = 0; + } + + return message_pending; +} + +/********************************************************************* + * @fn CAN_OperatingModeRequest + * + * @brief Select the CAN Operation mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_OperatingMode - CAN Operating Mode. + * CAN_OperatingMode_Initialization. + * CAN_OperatingMode_Normal. + * CAN_OperatingMode_Sleep. + * + * @return status - + * CAN_ModeStatus_Failed - CAN failed entering the specific mode. + * CAN_ModeStatus_Success - CAN Succeed entering the specific mode. + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + uint32_t timeout = INAK_TIMEOUT; + + if(CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SLEEP)) | CAN_CTLR_INRQ); + + while(((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) && (timeout != 0)) + { + timeout--; + } + if((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if(CAN_OperatingMode == CAN_OperatingMode_Normal) + { + CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SLEEP | CAN_CTLR_INRQ)); + + while(((CANx->STATR & CAN_MODE_MASK) != 0) && (timeout != 0)) + { + timeout--; + } + if((CANx->STATR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if(CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + while(((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) && (timeout != 0)) + { + timeout--; + } + if((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t)status; +} + +/********************************************************************* + * @fn CAN_Sleep + * + * @brief Enters the low power mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return sleepstatus - + * CAN_Sleep_Ok. + * CAN_Sleep_Failed. + */ +uint8_t CAN_Sleep(CAN_TypeDef *CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + if((CANx->STATR & (CAN_STATR_SLAK | CAN_STATR_INAK)) == CAN_STATR_SLAK) + { + sleepstatus = CAN_Sleep_Ok; + } + + return (uint8_t)sleepstatus; +} + +/********************************************************************* + * @fn CAN_WakeUp + * + * @brief Wakes the CAN up. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return wakeupstatus - + * CAN_WakeUp_Ok. + * CAN_WakeUp_Failed. + */ +uint8_t CAN_WakeUp(CAN_TypeDef *CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + CANx->CTLR &= ~(uint32_t)CAN_CTLR_SLEEP; + + while(((CANx->STATR & CAN_STATR_SLAK) == CAN_STATR_SLAK) && (wait_slak != 0x00)) + { + wait_slak--; + } + if((CANx->STATR & CAN_STATR_SLAK) != CAN_STATR_SLAK) + { + wakeupstatus = CAN_WakeUp_Ok; + } + + return (uint8_t)wakeupstatus; +} + +/********************************************************************* + * @fn CAN_GetLastErrorCode + * + * @brief Returns the CANx's last error code (LEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return errorcode - specifies the Error code. + * CAN_ErrorCode_NoErr - No Error. + * CAN_ErrorCode_StuffErr - Stuff Error. + * CAN_ErrorCode_FormErr - Form Error. + * CAN_ErrorCode_ACKErr - Acknowledgment Error. + * CAN_ErrorCode_BitRecessiveErr - Bit Recessive Error. + * CAN_ErrorCode_BitDominantErr - Bit Dominant Error. + * CAN_ErrorCode_CRCErr - CRC Error. + * CAN_ErrorCode_SoftwareSetErr - Software Set Error. + */ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx) +{ + uint8_t errorcode = 0; + + errorcode = (((uint8_t)CANx->ERRSR) & (uint8_t)CAN_ERRSR_LEC); + + return errorcode; +} + +/********************************************************************* + * @fn CAN_GetReceiveErrorCounter + * + * @brief Returns the CANx Receive Error Counter (REC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return counter - CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx) +{ + uint8_t counter = 0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_REC) >> 24); + + return counter; +} + +/********************************************************************* + * @fn CAN_GetLSBTransmitErrorCounter + * + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx) +{ + uint8_t counter = 0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_TEC) >> 16); + + return counter; +} + +/********************************************************************* + * @fn CAN_ITConfig + * + * @brief Enables or disables the specified CANx interrupts. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt sources to be enabled or disabled. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_LEC. + * CAN_IT_ERR. + * CAN_IT_WKU. + * CAN_IT_SLK. + * NewState - ENABLE or DISABLE. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + CANx->INTENR |= CAN_IT; + } + else + { + CANx->INTENR &= ~CAN_IT; + } +} + +/********************************************************************* + * @fn CAN_GetFlagStatus + * + * @brief Checks whether the specified CAN flag is set or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to check. + * CAN_FLAG_EWG. + * CAN_FLAG_EPV. + * CAN_FLAG_BOF. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FMP1. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FMP0. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * NewState - ENABLE or DISABLE. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((CAN_FLAG & CAN_FLAGS_ERRSR) != (uint32_t)RESET) + { + if((CANx->ERRSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_STATR) != (uint32_t)RESET) + { + if((CANx->STATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) + { + if((CANx->TSTATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) + { + if((CANx->RFIFO0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((uint32_t)(CANx->RFIFO1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/********************************************************************* + * @fn CAN_ClearFlag + * + * @brief Clears the CAN's pending flags. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to clear. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * + * @return none + */ +void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp = 0; + + if(CAN_FLAG == CAN_FLAG_LEC) + { + CANx->ERRSR = (uint32_t)RESET; + } + else + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) + { + CANx->RFIFO0 = (uint32_t)(flagtmp); + } + else if((CAN_FLAG & CAN_FLAGS_RFIFO1) != (uint32_t)RESET) + { + CANx->RFIFO1 = (uint32_t)(flagtmp); + } + else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) + { + CANx->TSTATR = (uint32_t)(flagtmp); + } + else + { + CANx->STATR = (uint32_t)(flagtmp); + } + } +} + +/********************************************************************* + * @fn CAN_GetITStatus + * + * @brief Checks whether the specified CANx interrupt has occurred or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt source to check. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return ITStatus - SET or RESET. + */ +ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + + if((CANx->INTENR & CAN_IT) != RESET) + { + switch(CAN_IT) + { + case CAN_IT_TME: + itstatus = CheckITStatus(CANx->TSTATR, CAN_TSTATR_RQCP0 | CAN_TSTATR_RQCP1 | CAN_TSTATR_RQCP2); + break; + + case CAN_IT_FMP0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FMP0); + break; + + case CAN_IT_FF0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FULL0); + break; + + case CAN_IT_FOV0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FOVR0); + break; + + case CAN_IT_FMP1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FMP1); + break; + + case CAN_IT_FF1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FULL1); + break; + + case CAN_IT_FOV1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FOVR1); + break; + + case CAN_IT_WKU: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_WKUI); + break; + + case CAN_IT_SLK: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_SLAKI); + break; + + case CAN_IT_EWG: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EWGF); + break; + + case CAN_IT_EPV: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EPVF); + break; + + case CAN_IT_BOF: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_BOFF); + break; + + case CAN_IT_LEC: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_LEC); + break; + + case CAN_IT_ERR: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_ERRI); + break; + + default: + itstatus = RESET; + break; + } + } + else + { + itstatus = RESET; + } + + return itstatus; +} + +/********************************************************************* + * @fn CAN_ClearITPendingBit + * + * @brief Clears the CANx's interrupt pending bits. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the interrupt pending bit to clear. + * CAN_IT_TME. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return none + */ +void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT) +{ + switch(CAN_IT) + { + case CAN_IT_TME: + CANx->TSTATR = CAN_TSTATR_RQCP0 | CAN_TSTATR_RQCP1 | CAN_TSTATR_RQCP2; + break; + + case CAN_IT_FF0: + CANx->RFIFO0 = CAN_RFIFO0_FULL0; + break; + + case CAN_IT_FOV0: + CANx->RFIFO0 = CAN_RFIFO0_FOVR0; + break; + + case CAN_IT_FF1: + CANx->RFIFO1 = CAN_RFIFO1_FULL1; + break; + + case CAN_IT_FOV1: + CANx->RFIFO1 = CAN_RFIFO1_FOVR1; + break; + + case CAN_IT_WKU: + CANx->STATR = CAN_STATR_WKUI; + break; + + case CAN_IT_SLK: + CANx->STATR = CAN_STATR_SLAKI; + break; + + case CAN_IT_EWG: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_EPV: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_BOF: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_LEC: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_ERR: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn CheckITStatus + * + * @brief Checks whether the CAN interrupt has occurred or not. + * + * @param CAN_Reg - specifies the CAN interrupt register to check + * It_Bit - specifies the interrupt source bit to check. + * + * @return ITStatus - SET or RESET. + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + pendingbitstatus = SET; + } + else + { + pendingbitstatus = RESET; + } + + return pendingbitstatus; +} diff --git a/libraries/sdk/Peripheral/ch32v30x_can.h b/libraries/sdk/Peripheral/ch32v30x_can.h new file mode 100644 index 0000000..a5326a4 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_can.h @@ -0,0 +1,366 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_can.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* CAN firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_CAN_H +#define __CH32V30x_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* CAN init structure definition */ +typedef struct +{ + uint16_t CAN_Prescaler; /* Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /* Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /* Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /* Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CAN_NART; /* Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitTypeDef; + +/* CAN filter init structure definition */ +typedef struct +{ + uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /* Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /* Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/* CAN Tx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/* CAN Rx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /* Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/* CAN_sleep_constants */ +#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */ + +/* CAN_Mode */ +#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */ + +/* CAN_Operating_Mode */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */ + +/* CAN_Mode_Status */ +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */ + +/* CAN_synchronisation_jump_width */ +#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ + +/* CAN_time_quantum_in_bit_segment_1 */ +#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_time_quantum_in_bit_segment_2 */ +#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ + +/* CAN_filter_mode */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */ + +/* CAN_filter_scale */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */ + +/* CAN_filter_FIFO */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */ + +/* CAN_identifier_type */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */ + +/* CAN_remote_transmission_request */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */ + +/* CAN_transmit_constants */ +#define CAN_TxStatus_Failed ((uint8_t)0x00)/* CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ + +/* CAN_receive_FIFO_number_constants */ +#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */ + +/* CAN_sleep_constants */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */ + +/* CAN_wake_up_constants */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */ + +/* CAN_Error_Code_constants */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */ + + +/* CAN_flags */ +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */ + + +/* CAN_interrupts */ +#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + +/* CAN_Legacy */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok + + +void CAN_DeInit(CAN_TypeDef* CANx); +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_crc.c b/libraries/sdk/Peripheral/ch32v30x_crc.c new file mode 100644 index 0000000..3ae9236 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_crc.c @@ -0,0 +1,98 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_crc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the CRC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_crc.h" + +/********************************************************************* + * @fn CRC_ResetDR + * + * @brief Resets the CRC Data register (DR). + * + * @return none + */ +void CRC_ResetDR(void) +{ + CRC->CTLR = CRC_CTLR_RESET; +} + +/********************************************************************* + * @fn CRC_CalcCRC + * + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * + * @param Data - data word(32-bit) to compute its CRC. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DATAR = Data; + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_CalcBlockCRC + * + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * + * @param pBuffer - pointer to the buffer containing the data to be computed. + * BufferLength - length of the buffer to be computed. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DATAR = pBuffer[index]; + } + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_GetCRC + * + * @brief Returns the current CRC value. + * + * @return 32-bit CRC. + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_SetIDRegister + * + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * + * @param IDValue - 8-bit value to be stored in the ID register. + * + * @return none + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDATAR = IDValue; +} + +/********************************************************************* + * @fn CRC_GetIDRegister + * + * @brief Returns the 8-bit data stored in the Independent Data(ID) register. + * + * @return 8-bit value of the ID register. + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDATAR); +} diff --git a/libraries/sdk/Peripheral/ch32v30x_crc.h b/libraries/sdk/Peripheral/ch32v30x_crc.h new file mode 100644 index 0000000..6a4055c --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_crc.h @@ -0,0 +1,37 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_crc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* CRC firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_CRC_H +#define __CH32V30x_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_dac.c b/libraries/sdk/Peripheral/ch32v30x_dac.c new file mode 100644 index 0000000..566e0c7 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_dac.c @@ -0,0 +1,302 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dac.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DAC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +****************************************************************************************/ +#include "ch32v30x_dac.h" +#include "ch32v30x_rcc.h" + +/* CTLR register Mask */ +#define CTLR_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTR masks */ +#define DUAL_SWTR_SET ((uint32_t)0x00000003) +#define DUAL_SWTR_RESET ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) +#define DHR12RD_OFFSET ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) + +/********************************************************************* + * @fn DAC_DeInit + * + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * + * @return none + */ +void DAC_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/********************************************************************* + * @fn DAC_Init + * + * @brief Initializes the DAC peripheral according to the specified parameters in + * the DAC_InitStruct. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * DAC_InitStruct - pointer to a DAC_InitTypeDef structure. + * + * @return none + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + tmpreg1 = DAC->CTLR; + tmpreg1 &= ~(CTLR_CLEAR_MASK << DAC_Channel); + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); + tmpreg1 |= tmpreg2 << DAC_Channel; + DAC->CTLR = tmpreg1; +} + +/********************************************************************* + * @fn DAC_StructInit + * + * @brief Fills each DAC_InitStruct member with its default value. + * + * @param DAC_InitStruct - pointer to a DAC_InitTypeDef structure which will be initialized. + * + * @return none + */ +void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct) +{ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/********************************************************************* + * @fn DAC_Cmd + * + * @brief Enables or disables the specified DAC channel. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->CTLR |= (DAC_EN1 << DAC_Channel); + } + else + { + DAC->CTLR &= ~(DAC_EN1 << DAC_Channel); + } +} + +/********************************************************************* + * @fn DAC_DMACmd + * + * @brief Enables or disables the specified DAC channel DMA request. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->CTLR |= (DAC_DMAEN1 << DAC_Channel); + } + else + { + DAC->CTLR &= ~(DAC_DMAEN1 << DAC_Channel); + } +} + +/********************************************************************* + * @fn DAC_SoftwareTriggerCmd + * + * @brief Enables or disables the selected DAC channel software trigger. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->SWTR |= (uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + DAC->SWTR &= ~((uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/********************************************************************* + * @fn DAC_DualSoftwareTriggerCmd + * + * @brief Enables or disables the two DAC channel software trigger. + * + * @param NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->SWTR |= DUAL_SWTR_SET; + } + else + { + DAC->SWTR &= DUAL_SWTR_RESET; + } +} + +/********************************************************************* + * @fn DAC_WaveGenerationCmd + * + * @brief Enables or disables the selected DAC channel wave generation. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * DAC_Wave - Specifies the wave type to enable or disable. + * DAC_Wave_Noise - noise wave generation + * DAC_Wave_Triangle - triangle wave generation + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->CTLR |= DAC_Wave << DAC_Channel; + } + else + { + DAC->CTLR &= ~(DAC_Wave << DAC_Channel); + } +} + +/********************************************************************* + * @fn DAC_SetChannel1Data + * + * @brief Set the specified data holding register value for DAC channel1. + * + * @param DAC_Align - Specifies the data alignment for DAC channel1. + * DAC_Align_8b_R - 8bit right data alignment selected + * DAC_Align_12b_L - 12bit left data alignment selected + * DAC_Align_12b_R - 12bit right data alignment selected + * Data - Data to be loaded in the selected data holding register. + * + * @return none + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn DAC_SetChannel2Data + * + * @brief Set the specified data holding register value for DAC channel2. + * + * @param DAC_Align - Specifies the data alignment for DAC channel1. + * DAC_Align_8b_R - 8bit right data alignment selected + * DAC_Align_12b_L - 12bit left data alignment selected + * DAC_Align_12b_R - 12bit right data alignment selected + * Data - Data to be loaded in the selected data holding register. + * + * @return none + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_OFFSET + DAC_Align; + + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn DAC_SetDualChannelData + * + * @brief Set the specified data holding register value for two DAC. + * + * @param DAC_Align - Specifies the data alignment for DAC channel1. + * DAC_Align_8b_R - 8bit right data alignment selected + * DAC_Align_12b_L - 12bit left data alignment selected + * DAC_Align_12b_R - 12bit right data alignment selected + * Data - Data to be loaded in the selected data holding register. + * Data1 - Data for DAC Channel1. + * Data2 - Data for DAC Channel2 + * + * @return none + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + if(DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_OFFSET + DAC_Align; + + *(__IO uint32_t *)tmp = data; +} + +/********************************************************************* + * @fn DAC_GetDataOutputValue + * + * @brief Returns the last data output value of the selected DAC channel. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * + * @return none + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + return (uint16_t)(*(__IO uint32_t *)tmp); +} diff --git a/libraries/sdk/Peripheral/ch32v30x_dac.h b/libraries/sdk/Peripheral/ch32v30x_dac.h new file mode 100644 index 0000000..1041ae1 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_dac.h @@ -0,0 +1,120 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dac.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DAC firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_DAC_H +#define __CH32V30x_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* DAC Init structure definition */ +typedef struct +{ + uint32_t DAC_Trigger; /* Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /* Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /* Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /* Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + + +/* DAC_trigger_selection */ +#define DAC_Trigger_None ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel + only in High-density devices*/ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */ + +/* DAC_wave_generation */ +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) + + +/* DAC_lfsrunmask_triangleamplitude */ +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */ + +/* DAC_output_buffer */ +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) + +/* DAC_Channel_selection */ +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) + +/* DAC_data_alignment */ +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) + +/* DAC_wave_generation */ +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) + + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/libraries/sdk/Peripheral/ch32v30x_dbgmcu.c b/libraries/sdk/Peripheral/ch32v30x_dbgmcu.c new file mode 100644 index 0000000..87b286f --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_dbgmcu.c @@ -0,0 +1,36 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dbgmcu.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DBGMCU firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +****************************************************************************************/ +#include "ch32v30x_dbgmcu.h" + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) >> 16); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); +} diff --git a/libraries/sdk/Peripheral/ch32v30x_dbgmcu.h b/libraries/sdk/Peripheral/ch32v30x_dbgmcu.h new file mode 100644 index 0000000..f762309 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_dbgmcu.h @@ -0,0 +1,35 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dbgmcu.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DBGMCU firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_DBGMCU_H +#define __CH32V30x_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_dma.c b/libraries/sdk/Peripheral/ch32v30x_dma.c new file mode 100644 index 0000000..30aaffe --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_dma.c @@ -0,0 +1,690 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dma.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DMA firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_dma.h" +#include "ch32v30x_rcc.h" + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA2_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA2_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA2_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) +#define DMA2_Channel9_IT_Mask ((uint32_t)(DMA_GIF9 | DMA_TCIF9 | DMA_HTIF9 | DMA_TEIF9)) +#define DMA2_Channel10_IT_Mask ((uint32_t)(DMA_GIF10 | DMA_TCIF10 | DMA_HTIF10 | DMA_TEIF10)) +#define DMA2_Channel11_IT_Mask ((uint32_t)(DMA_GIF11 | DMA_TCIF11 | DMA_HTIF11 | DMA_TEIF11)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) +#define DMA2_EXTEN_FLAG_Mask ((uint32_t)0x20000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel1) + { + DMA2->INTFCR |= DMA2_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel2) + { + DMA2->INTFCR |= DMA2_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel3) + { + DMA2->INTFCR |= DMA2_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel4) + { + DMA2->INTFCR |= DMA2_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel5) + { + DMA2->INTFCR |= DMA2_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel6) + { + DMA2->INTFCR |= DMA2_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel7) + { + DMA2->INTFCR |= DMA2_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel8) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel8_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel9) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel9_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel10) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel10_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel11) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel11_IT_Mask; + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. + * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. + * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. + * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. + * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_FLAG_GL6 - DMA2 Channel6 global flag. + * DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_FLAG_GL7 - DMA2 Channel7 global flag. + * DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_FLAG_GL8 - DMA2 Channel8 global flag. + * DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_FLAG_GL9 - DMA2 Channel9 global flag. + * DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_FLAG_GL10 - DMA2 Channel10 global flag. + * DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_FLAG_GL11 - DMA2 Channel11 global flag. + * DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag. + * + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask) + { + tmpreg = DMA2->INTFR; + } + else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + tmpreg = DMA2_EXTEN->INTFR; + } + else + { + tmpreg = DMA1->INTFR; + } + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. + * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. + * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. + * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. + * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_FLAG_GL6 - DMA2 Channel6 global flag. + * DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_FLAG_GL7 - DMA2 Channel7 global flag. + * DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_FLAG_GL8 - DMA2 Channel8 global flag. + * DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_FLAG_GL9 - DMA2 Channel9 global flag. + * DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_FLAG_GL10 - DMA2 Channel10 global flag. + * DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_FLAG_GL11 - DMA2 Channel11 global flag. + * DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag. + * + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask) + { + DMA2->INTFCR = DMAy_FLAG; + } + else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + DMA2_EXTEN->INTFCR = DMAy_FLAG; + } + else + { + DMA1->INTFCR = DMAy_FLAG; + } +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_IT_GL2 - DMA2 Channel2 global flag. + * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_IT_GL3 - DMA2 Channel3 global flag. + * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_IT_GL4 - DMA2 Channel4 global flag. + * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_IT_GL5 - DMA2 Channel5 global flag. + * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_IT_GL6 - DMA2 Channel6 global flag. + * DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_IT_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_IT_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_IT_GL7 - DMA2 Channel7 global flag. + * DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_IT_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_IT_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_IT_GL8 - DMA2 Channel8 global flag. + * DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_IT_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_IT_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_IT_GL9 - DMA2 Channel9 global flag. + * DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_IT_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_IT_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_IT_GL10 - DMA2 Channel10 global flag. + * DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_IT_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_IT_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_IT_GL11 - DMA2 Channel11 global flag. + * DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_IT_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_IT_TE11 - DMA2 Channel11 transfer error flag. + * + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + if((DMAy_IT & FLAG_Mask) == FLAG_Mask) + { + tmpreg = DMA2->INTFR; + } + else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + tmpreg = DMA2_EXTEN->INTFR; + } + else + { + tmpreg = DMA1->INTFR; + } + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_IT_GL2 - DMA2 Channel2 global flag. + * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_IT_GL3 - DMA2 Channel3 global flag. + * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_IT_GL4 - DMA2 Channel4 global flag. + * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_IT_GL5 - DMA2 Channel5 global flag. + * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_IT_GL6 - DMA2 Channel6 global flag. + * DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_IT_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_IT_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_IT_GL7 - DMA2 Channel7 global flag. + * DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_IT_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_IT_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_IT_GL8 - DMA2 Channel8 global flag. + * DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_IT_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_IT_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_IT_GL9 - DMA2 Channel9 global flag. + * DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_IT_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_IT_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_IT_GL10 - DMA2 Channel10 global flag. + * DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_IT_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_IT_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_IT_GL11 - DMA2 Channel11 global flag. + * DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_IT_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_IT_TE11 - DMA2 Channel11 transfer error flag. + * + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + if((DMAy_IT & FLAG_Mask) == FLAG_Mask) + { + DMA2->INTFCR = DMAy_IT; + } + else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + DMA2_EXTEN->INTFCR = DMAy_IT; + } + else + { + DMA1->INTFCR = DMAy_IT; + } +} diff --git a/libraries/sdk/Peripheral/ch32v30x_dma.h b/libraries/sdk/Peripheral/ch32v30x_dma.h new file mode 100644 index 0000000..34cefbf --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_dma.h @@ -0,0 +1,268 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dma.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DMA firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_DMA_H +#define __CH32V30x_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) +#define DMA2_IT_GL6 ((uint32_t)0x10100000) +#define DMA2_IT_TC6 ((uint32_t)0x10200000) +#define DMA2_IT_HT6 ((uint32_t)0x10400000) +#define DMA2_IT_TE6 ((uint32_t)0x10800000) +#define DMA2_IT_GL7 ((uint32_t)0x11000000) +#define DMA2_IT_TC7 ((uint32_t)0x12000000) +#define DMA2_IT_HT7 ((uint32_t)0x14000000) +#define DMA2_IT_TE7 ((uint32_t)0x18000000) + +#define DMA2_IT_GL8 ((uint32_t)0x20000001) +#define DMA2_IT_TC8 ((uint32_t)0x20000002) +#define DMA2_IT_HT8 ((uint32_t)0x20000004) +#define DMA2_IT_TE8 ((uint32_t)0x20000008) +#define DMA2_IT_GL9 ((uint32_t)0x20000010) +#define DMA2_IT_TC9 ((uint32_t)0x20000020) +#define DMA2_IT_HT9 ((uint32_t)0x20000040) +#define DMA2_IT_TE9 ((uint32_t)0x20000080) +#define DMA2_IT_GL10 ((uint32_t)0x20000100) +#define DMA2_IT_TC10 ((uint32_t)0x20000200) +#define DMA2_IT_HT10 ((uint32_t)0x20000400) +#define DMA2_IT_TE10 ((uint32_t)0x20000800) +#define DMA2_IT_GL11 ((uint32_t)0x20001000) +#define DMA2_IT_TC11 ((uint32_t)0x20002000) +#define DMA2_IT_HT11 ((uint32_t)0x20004000) +#define DMA2_IT_TE11 ((uint32_t)0x20008000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) +#define DMA2_FLAG_GL6 ((uint32_t)0x10100000) +#define DMA2_FLAG_TC6 ((uint32_t)0x10200000) +#define DMA2_FLAG_HT6 ((uint32_t)0x10400000) +#define DMA2_FLAG_TE6 ((uint32_t)0x10800000) +#define DMA2_FLAG_GL7 ((uint32_t)0x11000000) +#define DMA2_FLAG_TC7 ((uint32_t)0x12000000) +#define DMA2_FLAG_HT7 ((uint32_t)0x14000000) +#define DMA2_FLAG_TE7 ((uint32_t)0x18000000) + +#define DMA2_FLAG_GL8 ((uint32_t)0x20000001) +#define DMA2_FLAG_TC8 ((uint32_t)0x20000002) +#define DMA2_FLAG_HT8 ((uint32_t)0x20000004) +#define DMA2_FLAG_TE8 ((uint32_t)0x20000008) +#define DMA2_FLAG_GL9 ((uint32_t)0x20000010) +#define DMA2_FLAG_TC9 ((uint32_t)0x20000020) +#define DMA2_FLAG_HT9 ((uint32_t)0x20000040) +#define DMA2_FLAG_TE9 ((uint32_t)0x20000080) +#define DMA2_FLAG_GL10 ((uint32_t)0x20000100) +#define DMA2_FLAG_TC10 ((uint32_t)0x20000200) +#define DMA2_FLAG_HT10 ((uint32_t)0x20000400) +#define DMA2_FLAG_TE10 ((uint32_t)0x20000800) +#define DMA2_FLAG_GL11 ((uint32_t)0x20001000) +#define DMA2_FLAG_TC11 ((uint32_t)0x20002000) +#define DMA2_FLAG_HT11 ((uint32_t)0x20004000) +#define DMA2_FLAG_TE11 ((uint32_t)0x20008000) + + +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/libraries/sdk/Peripheral/ch32v30x_dvp.c b/libraries/sdk/Peripheral/ch32v30x_dvp.c new file mode 100644 index 0000000..15e5515 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_dvp.c @@ -0,0 +1,133 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dvp.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DVP firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_dvp.h" + +/********************************************************************* + * @fn DVP_INTCfg + * + * @brief DVP interrupt configuration + * + * @param s - interrupt enable + * ENABLE + * DISABLE + * i - interrupt type + * RB_DVP_IE_STP_FRM + * RB_DVP_IE_FIFO_OV + * RB_DVP_IE_FRM_DONE + * RB_DVP_IE_ROW_DONE + * RB_DVP_IE_STR_FRM + * + * @return none + */ +void DVP_INTCfg(uint8_t s, uint8_t i) +{ + if(s) + { + DVP->IER |= i; + } + else + { + DVP->IER &= ~i; + } +} + +/********************************************************************* + * @fn DVP_Mode + * + * @brief DVP mode + * + * @param s - data bit width + * RB_DVP_D8_MOD + * RB_DVP_D10_MOD + * RB_DVP_D12_MOD + * i - interrupt type + * Video_Mode + * JPEG_Mode + * + * @return none + */ +void DVP_Mode(uint8_t s, DVP_Data_ModeTypeDef i) +{ + DVP->CR0 &= ~RB_DVP_MSK_DAT_MOD; + + if(s) + { + DVP->CR0 |= s; + } + else + { + DVP->CR0 &= ~(3 << 4); + } + + if(i) + { + DVP->CR0 |= RB_DVP_JPEG; + } + else + { + DVP->CR0 &= ~RB_DVP_JPEG; + } +} + +/********************************************************************* + * @fn DVP_Cfg + * + * @brief DVP configuration + * + * @param s - DMA enable control + * DVP_DMA_Enable + * DVP_DMA_Disable + * i - DVP all clear + * DVP_FLAG_FIFO_RESET_Enable + * DVP_FLAG_FIFO_RESET_Disable + * j - receive reset enable + * DVP_RX_RESET_Enable + * DVP_RX_RESET_Disable + * + * @return none + */ +void DVP_Cfg(DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j) +{ + switch(s) + { + case DVP_DMA_Enable: + DVP->CR1 |= RB_DVP_DMA_EN; + break; + case DVP_DMA_Disable: + DVP->CR1 &= ~RB_DVP_DMA_EN; + break; + default: + break; + } + + switch(i) + { + case DVP_RX_RESET_Enable: + DVP->CR1 |= RB_DVP_ALL_CLR; + break; + case DVP_RX_RESET_Disable: + DVP->CR1 &= ~RB_DVP_ALL_CLR; + break; + default: + break; + } + + switch(j) + { + case DVP_RX_RESET_Enable: + DVP->CR1 |= RB_DVP_RCV_CLR; + break; + case DVP_RX_RESET_Disable: + DVP->CR1 &= ~RB_DVP_RCV_CLR; + break; + default: + break; + } +} diff --git a/libraries/sdk/Peripheral/ch32v30x_dvp.h b/libraries/sdk/Peripheral/ch32v30x_dvp.h new file mode 100644 index 0000000..deafaeb --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_dvp.h @@ -0,0 +1,67 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dvp.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DVP firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_DVP_H +#define __CH32V30x_DVP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* DVP Data Mode */ +typedef enum +{ + Video_Mode = 0, + JPEG_Mode, +}DVP_Data_ModeTypeDef; + + +/* DVP DMA */ +typedef enum +{ + DVP_DMA_Disable = 0, + DVP_DMA_Enable, +}DVP_DMATypeDef; + +/* DVP FLAG and FIFO Reset */ +typedef enum +{ + DVP_FLAG_FIFO_RESET_Disable = 0, + DVP_FLAG_FIFO_RESET_Enable, +}DVP_FLAG_FIFO_RESETTypeDef; + +/* DVP RX Reset */ +typedef enum +{ + DVP_RX_RESET_Disable = 0, + DVP_RX_RESET_Enable, +}DVP_RX_RESETTypeDef; + + + +void DVP_INTCfg( uint8_t s, uint8_t i ); +void DVP_Mode( uint8_t s, DVP_Data_ModeTypeDef i); +void DVP_Cfg( DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j); + + + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_eth.c b/libraries/sdk/Peripheral/ch32v30x_eth.c new file mode 100644 index 0000000..ddacd96 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_eth.c @@ -0,0 +1,2522 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_eth.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the ETH firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_eth.h" +#include "ch32v30x_rcc.h" + +ETH_DMADESCTypeDef *DMATxDescToSet; +ETH_DMADESCTypeDef *DMARxDescToGet; +ETH_DMADESCTypeDef *DMAPTPTxDescToSet; +ETH_DMADESCTypeDef *DMAPTPRxDescToGet; + +/********************************************************************* + * @fn ETH_DeInit + * + * @brief ETH hardware initialize again. + * + * @return none + */ +#ifdef CH32V30x_D8C +void ETH_DeInit(void) +{ + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE); +} + +#endif + +/********************************************************************* + * @fn ETH_StructInit + * + * @brief Fills each ETH_InitStruct member with its default value. + * + * @param ETH_InitStruct - pointer to a ETH_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void ETH_StructInit(ETH_InitTypeDef *ETH_InitStruct) +{ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; + ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; + ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + /*------------------------ DMA -----------------------------------*/ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; + ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; + ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; + ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; + ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; +} + +/********************************************************************* + * @fn ETH_Start + * + * @brief Enables ENET MAC and DMA reception/transmission. + * + * @return none + */ +void ETH_Start(void) +{ + ETH_MACTransmissionCmd(ENABLE); + ETH_FlushTransmitFIFO(); + ETH_MACReceptionCmd(ENABLE); + ETH_DMATransmissionCmd(ENABLE); + ETH_DMAReceptionCmd(ENABLE); +} + +/********************************************************************* + * @fn ETH_HandleTxPkt + * + * @brief Transmits a packet, from application buffer, pointed by ppkt. + * + * @param ppkt - pointer to the application's packet buffer to transmit. + * FrameLength - Tx Packet size. + * + * @return ETH_ERROR - in case of Tx desc owned by DMA. + * ETH_SUCCESS - for correct transmission. + */ +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) +{ + uint32_t offset = 0; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + for(offset = 0; offset < FrameLength; offset++) + { + (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset)); + } + + DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_TBUS; + ETH->DMATPDR = 0; + } + + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr); + } + else + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + } + else + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_HandleRxPkt + * + * @brief Receives a packet and copies it to memory pointed by ppkt. + * + * @param ppkt - pointer to the application packet receive buffer. + * + * @return ETH_ERROR - if there is error in reception + * framelength - received packet size if packet reception is correct + */ +uint32_t ETH_HandleRxPkt(uint8_t *ppkt) +{ + uint32_t offset = 0, framelength = 0; + + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + for(offset = 0; offset < framelength; offset++) + { + (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset)); + } + } + else + { + framelength = ETH_ERROR; + } + + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_RBUS; + ETH->DMARPDR = 0; + } + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr); + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return (framelength); +} + +/********************************************************************* + * @fn ETH_GetRxPktSize + * + * @brief Get the size of received the received packet. + * + * @return framelength - received packet size + */ +uint32_t ETH_GetRxPktSize(void) +{ + uint32_t frameLength = 0; + if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); + } + + return frameLength; +} + +/********************************************************************* + * @fn ETH_DropRxPkt + * + * @brief Drop a Received packet. + * + * @return none + */ +void ETH_DropRxPkt(void) +{ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr); + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } +} + +/********************************************************************* + * @fn ETH_ReadPHYRegister + * + * @brief Read a PHY register. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * PHYReg - PHY register address, is the index of one of the 32 PHY register. + * + * @return ETH_ERROR - in case of timeout. + * MAC MIIDR register value - Data read from the selected PHY register. + */ +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + + tmpreg = ETH->MACMIIAR; + tmpreg &= ~MACMIIAR_CR_MASK; + tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA); + tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR); + tmpreg &= ~ETH_MACMIIAR_MW; + tmpreg |= ETH_MACMIIAR_MB; + ETH->MACMIIAR = tmpreg; + + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); + + if(timeout == PHY_READ_TO) + { + return (uint16_t)ETH_ERROR; + } + + return (uint16_t)(ETH->MACMIIDR); +} + +/********************************************************************* + * @fn ETH_WritePHYRegister + * + * @brief Write to a PHY register. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * PHYReg - PHY register address, is the index of one of the 32 PHY register. + * PHYValue - the value to write. + * + * @return ETH_ERROR - in case of timeout. + * ETH_SUCCESS - for correct write + */ +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + + tmpreg = ETH->MACMIIAR; + tmpreg &= ~MACMIIAR_CR_MASK; + tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA); + tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR); + tmpreg |= ETH_MACMIIAR_MW; + tmpreg |= ETH_MACMIIAR_MB; + ETH->MACMIIDR = PHYValue; + ETH->MACMIIAR = tmpreg; + + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); + + if(timeout >= PHY_WRITE_TO) + { + return ETH_ERROR; + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_PHYLoopBackCmd + * + * @brief Enables or disables the PHY loopBack mode. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * NewState - new state of the PHY loopBack mode. + * + * @return ETH_ERROR - in case of bad PHY configuration. + * ETH_SUCCESS - for correct PHY configuration. + */ +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) +{ + uint16_t tmpreg = 0; + + tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + + if(NewState != DISABLE) + { + tmpreg |= PHY_Loopback; + } + else + { + tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); + } + + if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) + { + return ETH_SUCCESS; + } + else + { + return ETH_ERROR; + } +} + +/********************************************************************* + * @fn ETH_MACTransmissionCmd + * + * @brief Enables or disables the MAC transmission. + * + * @param NewState - new state of the MAC transmission. + * + * @return none + */ +void ETH_MACTransmissionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACCR |= ETH_MACCR_TE; + } + else + { + ETH->MACCR &= ~ETH_MACCR_TE; + } +} + +/********************************************************************* + * @fn ETH_MACReceptionCmd + * + * @brief Enables or disables the MAC reception. + * + * @param NewState - new state of the MAC reception. + * + * @return none + */ +void ETH_MACReceptionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACCR |= ETH_MACCR_RE; + } + else + { + ETH->MACCR &= ~ETH_MACCR_RE; + } +} + +/********************************************************************* + * @fn ETH_GetFlowControlBusyStatus + * + * @brief Enables or disables the MAC reception. + * + * @return The new state of flow control busy status bit (SET or RESET). + */ +FlagStatus ETH_GetFlowControlBusyStatus(void) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_InitiatePauseControlFrame + * + * @brief Initiate a Pause Control Frame (Full-duplex only). + * + * @return none + */ +void ETH_InitiatePauseControlFrame(void) +{ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; +} + +/********************************************************************* + * @fn ETH_BackPressureActivationCmd + * + * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). + * + * @param NewState - new state of the MAC BackPressure operation activation. + * + * @return none + */ +void ETH_BackPressureActivationCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACFCR |= ETH_MACFCR_FCBBPA; + } + else + { + ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; + } +} + +/********************************************************************* + * @fn ETH_GetMACFlagStatus + * + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * + * @param ETH_MAC_FLAG - specifies the flag to check. + * + * @return The new state of ETHERNET MAC flag (SET or RESET). + */ +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetMACITStatus + * + * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. + * + * @param ETH_MAC_IT - specifies the interrupt source to check. + * + * @return The new state of ETHERNET MAC interrupt (SET or RESET). + */ +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_MACITConfig + * + * @brief Enables or disables the specified ETHERNET MAC interrupts. + * + * @param ETH_MAC_IT - specifies the interrupt source to check. + * NewState - new state of the specified ETHERNET MAC interrupts. + * + * @return none + */ +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); + } + else + { + ETH->MACIMR |= ETH_MAC_IT; + } +} + +/********************************************************************* + * @fn ETH_MACAddressConfig + * + * @brief Configures the selected MAC address. + * + * @param MacAddr - The MAC addres to configure. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Addr - Pointer on MAC address buffer data (6 bytes). + * + * @return none + */ +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + + tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; + tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; + + (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg; +} + +/********************************************************************* + * @fn ETH_GetMACAddress + * + * @brief Get the selected MAC address. + * + * @param MacAddr - The MAC address to return. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Addr - Pointer on MAC address buffer data (6 bytes). + * + * @return none + */ +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + + tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)); + + Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[4] = (tmpreg & (uint8_t)0xFF); + tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr)); + Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); + Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); + Addr[1] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[0] = (tmpreg & (uint8_t)0xFF); +} + +/********************************************************************* + * @fn ETH_MACAddressPerfectFilterCmd + * + * @brief Enables or disables the Address filter module uses the specified. + * + * @param MacAddr - The MAC address to return. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * NewState - new state of the specified ETHERNET MAC address use. + * + * @return none + */ +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE; + } + else + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_AE); + } +} + +/********************************************************************* + * @fn ETH_MACAddressFilterConfig + * + * @brief Set the filter type for the specified ETHERNET MAC address. + * + * @param MacAddr - specifies the ETHERNET MAC address. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Filter - specifies the used frame received field for comparaison. + * ETH_MAC_AddressFilter_SA - MAC Address is used to compare with the + * SA fields of the received frame. + * ETH_MAC_AddressFilter_DA - MAC Address is used to compare with the + * DA fields of the received frame. + * + * @return none + */ +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) +{ + if(Filter != ETH_MAC_AddressFilter_DA) + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA; + } + else + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_SA); + } +} + +/********************************************************************* + * @fn ETH_MACAddressMaskBytesFilterConfig + * + * @brief Set the filter type for the specified ETHERNET MAC address. + * + * @param MacAddr - specifies the ETHERNET MAC address. + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * MaskByte - specifies the used address bytes for comparaison + * ETH_MAC_AddressMask_Byte5 - Mask MAC Address high reg bits [7:0]. + * ETH_MAC_AddressMask_Byte4 - Mask MAC Address low reg bits [31:24]. + * ETH_MAC_AddressMask_Byte3 - Mask MAC Address low reg bits [23:16]. + * ETH_MAC_AddressMask_Byte2 - Mask MAC Address low reg bits [15:8]. + * ETH_MAC_AddressMask_Byte1 - Mask MAC Address low reg bits [7:0]. + * + * @return none + */ +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) +{ + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_MBC); + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte; +} + +/********************************************************************* + * @fn ETH_DMATxDescChainInit + * + * @brief Initializes the DMA Tx descriptors in chain mode. + * + * @param DMATxDescTab - Pointer on the first Tx desc list + * TxBuff - Pointer on the first TxBuffer list + * TxBuffCount - Number of the used Tx desc in the list + * + * @return none + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (TxBuffCount - 1)) + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab; + } + } + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_DMATxDescRingInit + * + * @brief Initializes the DMA Tx descriptors in ring mode. + * + * @param DMATxDescTab - Pointer on the first Tx desc list. + * TxBuff1 - Pointer on the first TxBuffer1 list. + * TxBuff2 - Pointer on the first TxBuffer2 list. + * TxBuffCount - Number of the used Tx desc in the list. + * + * @return none + */ +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i * ETH_MAX_PACKET_SIZE]); + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i * ETH_MAX_PACKET_SIZE]); + + if(i == (TxBuffCount - 1)) + { + DMATxDesc->Status = ETH_DMATxDesc_TER; + } + } + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_GetDMATxDescFlagStatus + * + * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * ETH_DMATxDescFlag - specifies the flag to check. + * ETH_DMATxDesc_OWN - OWN bit - descriptor is owned by DMA engine + * ETH_DMATxDesc_IC - Interrupt on completetion + * ETH_DMATxDesc_LS - Last Segment + * ETH_DMATxDesc_FS - First Segment + * ETH_DMATxDesc_DC - Disable CRC + * ETH_DMATxDesc_DP - Disable Pad + * ETH_DMATxDesc_TTSE - Transmit Time Stamp Enable + * ETH_DMATxDesc_TER - Transmit End of Ring + * ETH_DMATxDesc_TCH - Second Address Chained + * ETH_DMATxDesc_TTSS - Tx Time Stamp Status + * ETH_DMATxDesc_IHE - IP Header Error + * ETH_DMATxDesc_ES - Error summary + * ETH_DMATxDesc_JT - Jabber Timeout + * ETH_DMATxDesc_FF - Frame Flushed - DMA/MTL flushed the frame due to SW flush + * ETH_DMATxDesc_PCE - Payload Checksum Error + * ETH_DMATxDesc_LCA - Loss of Carrier - carrier lost during tramsmission + * ETH_DMATxDesc_NC - No Carrier - no carrier signal from the tranceiver + * ETH_DMATxDesc_LCO - Late Collision - transmission aborted due to collision + * ETH_DMATxDesc_EC - Excessive Collision - transmission aborted after 16 collisions + * ETH_DMATxDesc_VF - VLAN Frame + * ETH_DMATxDesc_CC - Collision Count + * ETH_DMATxDesc_ED - Excessive Deferral + * ETH_DMATxDesc_UF - Underflow Error - late data arrival from the memory + * ETH_DMATxDesc_DB - Deferred Bit + * + * @return The new state of ETH_DMATxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) +{ + FlagStatus bitstatus = RESET; + + if((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetDMATxDescCollisionCount + * + * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * + * @param pointer on a DMA Tx descriptor. + * + * @return The Transmit descriptor collision counter value. + */ +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) +{ + return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); +} + +/********************************************************************* + * @fn ETH_SetDMATxDescOwnBit + * + * @brief Set the specified DMA Tx Desc Own bit. + * + * @param DMATxDesc - Pointer on a Tx desc + * + * @return none + */ +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATxDesc_OWN; +} + +/********************************************************************* + * @fn ETH_DMATxDescTransmitITConfig + * + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * + * @param Pointer on a Tx desc. + * NewState - new state of the DMA Tx Desc transmit interrupt. + * + * @return none + */ +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_IC; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_IC); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescFrameSegmentConfig + * + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * + * @param PDMATxDesc - Pointer on a Tx desc. + * ETH_DMATxDesc_FirstSegment - actual Tx desc contain first segment. + * + * @return none + */ +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) +{ + DMATxDesc->Status |= DMATxDesc_FrameSegment; +} + +/********************************************************************* + * @fn ETH_DMATxDescChecksumInsertionConfig + * + * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * DMATxDesc_Checksum - specifies is the DMA Tx desc checksum insertion. + * + * @return none + */ +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) +{ + DMATxDesc->Status |= DMATxDesc_Checksum; +} + +/********************************************************************* + * @fn ETH_DMATxDescCRCCmd + * + * @brief Enables or disables the DMA Tx Desc CRC. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc CRC. + * + * @return none + */ +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); + } + else + { + DMATxDesc->Status |= ETH_DMATxDesc_DC; + } +} + +/********************************************************************* + * @fn ETH_DMATxDescEndOfRingCmd + * + * @brief Enables or disables the DMA Tx Desc end of ring. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * NewState - new state of the specified DMA Tx Desc end of ring. + * + * @return none + */ +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TER; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescSecondAddressChainedCmd + * + * @brief Enables or disables the DMA Tx Desc second address chained. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc second address chained. + * + * @return none + */ +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TCH; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TCH); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescShortFramePaddingCmd + * + * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * NewState - new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @return none + */ +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); + } + else + { + DMATxDesc->Status |= ETH_DMATxDesc_DP; + } +} + +/********************************************************************* + * @fn ETH_DMATxDescTimeStampCmd + * + * @brief Enables or disables the DMA Tx Desc time stamp. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc time stamp. + * + * @return none + */ +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TTSE; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TTSE); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescBufferSizeConfig + * + * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. + * + * @param DMATxDesc - Pointer on a Tx desc. + * BufferSize1 - specifies the Tx desc buffer1 size. + * RxBuff2 - Pointer on the first RxBuffer2 list + * BufferSize2 - specifies the Tx desc buffer2 size (put "0" if not used). + * + * @return none + */ +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) +{ + DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); +} + +/********************************************************************* + * @fn ETH_DMARxDescChainInit + * + * @brief Initializes the DMA Rx descriptors in chain mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * RxBuff - Pointer on the first RxBuffer list. + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none + */ +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (RxBuffCount - 1)) + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_DMARxDescRingInit + * + * @brief Initializes the DMA Rx descriptors in ring mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * RxBuff1 - Pointer on the first RxBuffer1 list. + * RxBuff2 - Pointer on the first RxBuffer2 list + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none + */ +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i * ETH_MAX_PACKET_SIZE]); + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i * ETH_MAX_PACKET_SIZE]); + + if(i == (RxBuffCount - 1)) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + } + + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_GetDMARxDescFlagStatus + * + * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * ETH_DMARxDescFlag - specifies the flag to check. + * ETH_DMARxDesc_OWN - OWN bit: descriptor is owned by DMA engine + * ETH_DMARxDesc_AFM - DA Filter Fail for the rx frame + * ETH_DMARxDesc_ES - Error summary + * ETH_DMARxDesc_DE - Desciptor error: no more descriptors for receive frame + * ETH_DMARxDesc_SAF - SA Filter Fail for the received frame + * ETH_DMARxDesc_LE - Frame size not matching with length field + * ETH_DMARxDesc_OE - Overflow Error: Frame was damaged due to buffer overflow + * ETH_DMARxDesc_VLAN - VLAN Tag: received frame is a VLAN frame + * ETH_DMARxDesc_FS - First descriptor of the frame + * ETH_DMARxDesc_LS - Last descriptor of the frame + * ETH_DMARxDesc_IPV4HCE - IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * ETH_DMARxDesc_LC - Late collision occurred during reception + * ETH_DMARxDesc_FT - Frame type - Ethernet, otherwise 802.3 + * ETH_DMARxDesc_RWT - Receive Watchdog Timeout: watchdog timer expired during reception + * ETH_DMARxDesc_RE - Receive error: error reported by MII interface + * ETH_DMARxDesc_DE - Dribble bit error: frame contains non int multiple of 8 bits + * ETH_DMARxDesc_CE - CRC error + * ETH_DMARxDesc_MAMPCE - Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + * + * @return The new state of ETH_DMARxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) +{ + FlagStatus bitstatus = RESET; + + if((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_SetDMARxDescOwnBit + * + * @brief Set the specified DMA Rx Desc Own bit. + * + * @param DMARxDesc - Pointer on a Rx desc + * + * @return none + */ +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) +{ + DMARxDesc->Status |= ETH_DMARxDesc_OWN; +} + +/********************************************************************* + * @fn ETH_GetDMARxDescFrameLength + * + * @brief Returns the specified DMA Rx Desc frame length. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor + * + * @return The Rx descriptor received frame length. + */ +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) +{ + return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); +} + +/********************************************************************* + * @fn ETH_DMARxDescReceiveITConfig + * + * @brief Enables or disables the specified DMA Rx Desc receive interrupt. + * + * @param DMARxDesc - Pointer on a Rx desc + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_DIC); + } + else + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; + } +} + +/********************************************************************* + * @fn ETH_DMARxDescEndOfRingCmd + * + * @brief Enables or disables the DMA Rx Desc end of ring. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * NewState - new state of the specified DMA Rx Desc end of ring. + * + * @return none + */ +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + else + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RER); + } +} + +/********************************************************************* + * @fn ETH_DMARxDescSecondAddressChainedCmd + * + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * NewState - new state of the specified DMA Rx Desc second address chained. + * + * @return none + */ +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; + } + else + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RCH); + } +} + +/********************************************************************* + * @fn ETH_GetDMARxDescBufferSize + * + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * DMARxDesc_Buffer - specifies the DMA Rx Desc buffer. + * ETH_DMARxDesc_Buffer1 - DMA Rx Desc Buffer1 + * ETH_DMARxDesc_Buffer2 - DMA Rx Desc Buffer2 + * + * @return The Receive descriptor frame length. + */ +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) +{ + if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) + { + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); + } + else + { + return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); + } +} + +/********************************************************************* + * @fn ETH_SoftwareReset + * + * @brief Resets all MAC subsystem internal registers and logic. + * + * @return none + */ +void ETH_SoftwareReset(void) +{ + ETH->DMABMR |= ETH_DMABMR_SR; +} + +/********************************************************************* + * @fn ETH_GetSoftwareResetStatus + * + * @brief Checks whether the ETHERNET software reset bit is set or not. + * + * @return The new state of DMA Bus Mode register SR bit (SET or RESET). + */ +FlagStatus ETH_GetSoftwareResetStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + //printf("ETH->DMABMR is:%08x\n", ETH->DMABMR); + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetlinkStaus + * + * @brief Checks whether the internal 10BASE-T PHY is link or not. + * + * @return Internal 10BASE-T PHY is link or not. + */ +FlagStatus ETH_GetlinkStaus(void) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMASR & 0x80000000) != (uint32_t)RESET) + { + bitstatus = PHY_10BASE_T_LINKED; + } + else + { + bitstatus = PHY_10BASE_T_NOT_LINKED; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetDMAFlagStatus + * + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * + * @param ETH_DMA_FLAG - specifies the flag to check. + * ETH_DMA_FLAG_TST - Time-stamp trigger flag + * ETH_DMA_FLAG_PMT - PMT flag + * ETH_DMA_FLAG_MMC - MMC flag + * ETH_DMA_FLAG_DataTransferError - Error bits 0-data buffer, 1-desc. access + * ETH_DMA_FLAG_ReadWriteError - Error bits 0-write trnsf, 1-read transfr + * ETH_DMA_FLAG_AccessError - Error bits 0-Rx DMA, 1-Tx DMA + * ETH_DMA_FLAG_NIS - Normal interrupt summary flag + * ETH_DMA_FLAG_AIS - Abnormal interrupt summary flag + * ETH_DMA_FLAG_ER - Early receive flag + * ETH_DMA_FLAG_FBE - Fatal bus error flag + * ETH_DMA_FLAG_ET - Early transmit flag + * ETH_DMA_FLAG_RWT - Receive watchdog timeout flag + * ETH_DMA_FLAG_RPS - Receive process stopped flag + * ETH_DMA_FLAG_RBU - Receive buffer unavailable flag + * ETH_DMA_FLAG_R - Receive flag + * ETH_DMA_FLAG_TU - Underflow flag + * ETH_DMA_FLAG_RO - Overflow flag + * ETH_DMA_FLAG_TJT - Transmit jabber timeout flag + * ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag + * ETH_DMA_FLAG_TPS - Transmit process stopped flag + * ETH_DMA_FLAG_T - Transmit flag + * + * @return Internal 10BASE-T PHY is link or not. + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMAClearFlag + * + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * + * @param ETH_DMA_FLAG - specifies the flag to clear. + * ETH_DMA_FLAG_NIS - Normal interrupt summary flag + * ETH_DMA_FLAG_AIS - Abnormal interrupt summary flag + * ETH_DMA_FLAG_ER - Early receive flag + * ETH_DMA_FLAG_FBE - Fatal bus error flag + * ETH_DMA_FLAG_ETI - Early transmit flag + * ETH_DMA_FLAG_RWT - Receive watchdog timeout flag + * ETH_DMA_FLAG_RPS - Receive process stopped flag + * ETH_DMA_FLAG_RBU - Receive buffer unavailable flag + * ETH_DMA_FLAG_R - Receive flag + * ETH_DMA_FLAG_TU - Transmit Underflow flag + * ETH_DMA_FLAG_RO - Receive Overflow flag + * ETH_DMA_FLAG_TJT - Transmit jabber timeout flag + * ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag + * ETH_DMA_FLAG_TPS - Transmit process stopped flag + * ETH_DMA_FLAG_T - Transmit flag + * + * @return none + */ +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) +{ + ETH->DMASR = (uint32_t)ETH_DMA_FLAG; +} + +/********************************************************************* + * @fn ETH_GetDMAITStatus + * + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * + * @param ETH_DMA_IT - specifies the interrupt pending bit to clear. + * ETH_DMA_IT_TST - Time-stamp trigger interrupt + * ETH_DMA_IT_PMT - PMT interrupt + * ETH_DMA_IT_MMC - MMC interrupt + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ET - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Underflow interrupt + * ETH_DMA_IT_RO - Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * + * @return The new state of ETH_DMA_IT (SET or RESET). + */ +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) +{ + ITStatus bitstatus = RESET; + + if((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMAClearITPendingBit + * + * @brief Clears the ETHERNETs DMA IT pending bit. + * + * @param ETH_DMA_IT - specifies the interrupt pending bit to clear. + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ETI - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Transmit Underflow interrupt + * ETH_DMA_IT_RO - Receive Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * + * @return none + */ +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) +{ + ETH->DMASR = (uint32_t)ETH_DMA_IT; +} + +/********************************************************************* + * @fn ETH_GetTransmitProcessState + * + * @brief Returns the ETHERNET DMA Transmit Process State. + * + * @return The new ETHERNET DMA Transmit Process State - + * ETH_DMA_TransmitProcess_Stopped - Stopped - Reset or Stop Tx Command issued + * ETH_DMA_TransmitProcess_Fetching - Running - fetching the Tx descriptor + * ETH_DMA_TransmitProcess_Waiting - Running - waiting for status + * ETH_DMA_TransmitProcess_Reading - unning - reading the data from host memory + * ETH_DMA_TransmitProcess_Suspended - Suspended - Tx Desciptor unavailabe + * ETH_DMA_TransmitProcess_Closing - Running - closing Rx descriptor + */ +uint32_t ETH_GetTransmitProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); +} + +/********************************************************************* + * @fn ETH_GetReceiveProcessState + * + * @brief Returns the ETHERNET DMA Receive Process State. + * + * @return The new ETHERNET DMA Receive Process State: + * ETH_DMA_ReceiveProcess_Stopped - Stopped - Reset or Stop Rx Command issued + * ETH_DMA_ReceiveProcess_Fetching - Running - fetching the Rx descriptor + * ETH_DMA_ReceiveProcess_Waiting - Running - waiting for packet + * ETH_DMA_ReceiveProcess_Suspended - Suspended - Rx Desciptor unavailable + * ETH_DMA_ReceiveProcess_Closing - Running - closing descriptor + * ETH_DMA_ReceiveProcess_Queuing - Running - queuing the recieve frame into host memory + */ +uint32_t ETH_GetReceiveProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); +} + +/********************************************************************* + * @fn ETH_FlushTransmitFIFO + * + * @brief Clears the ETHERNET transmit FIFO. + * + * @return none + */ +void ETH_FlushTransmitFIFO(void) +{ + ETH->DMAOMR |= ETH_DMAOMR_FTF; +} + +/********************************************************************* + * @fn ETH_GetFlushTransmitFIFOStatus + * + * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not. + * + * @return The new state of ETHERNET flush transmit FIFO bit (SET or RESET). + */ +FlagStatus ETH_GetFlushTransmitFIFOStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMATransmissionCmd + * + * @brief Enables or disables the DMA transmission. + * + * @param NewState - new state of the DMA transmission. + * + * @return none + */ +void ETH_DMATransmissionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAOMR |= ETH_DMAOMR_ST; + } + else + { + ETH->DMAOMR &= ~ETH_DMAOMR_ST; + } +} + +/********************************************************************* + * @fn ETH_DMAReceptionCmd + * + * @brief Enables or disables the DMA reception. + * + * @param NewState - new state of the DMA reception. + * + * @return none + */ +void ETH_DMAReceptionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAOMR |= ETH_DMAOMR_SR; + } + else + { + ETH->DMAOMR &= ~ETH_DMAOMR_SR; + } +} + +/********************************************************************* + * @fn ETH_DMAITConfig + * + * @brief Enables or disables the specified ETHERNET DMA interrupts. + * + * @param ETH_DMA_IT - specifies the ETHERNET DMA interrupt sources to be enabled or disabled. + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ET - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Underflow interrupt + * ETH_DMA_IT_RO - Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter + * ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter + * NewState - new state of the specified ETHERNET DMA interrupts. + * + * @return new state of the specified ETHERNET DMA interrupts. + */ +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAIER |= ETH_DMA_IT; + } + else + { + ETH->DMAIER &= (~(uint32_t)ETH_DMA_IT); + } +} + +/********************************************************************* + * @fn ETH_GetDMAOverflowStatus + * + * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * + * @param ETH_DMA_Overflow - specifies the DMA overflow flag to check. + * ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter + * ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter + * + * @return The new state of ETHERNET DMA overflow Flag (SET or RESET). + */ +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetRxOverflowMissedFrameCounter + * + * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. + * + * @return The value of Rx overflow Missed Frame Counter. + */ +uint32_t ETH_GetRxOverflowMissedFrameCounter(void) +{ + return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >> ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT)); +} + +/********************************************************************* + * @fn ETH_GetBufferUnavailableMissedFrameCounter + * + * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. + * + * @return The value of Buffer unavailable Missed Frame Counter. + */ +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) +{ + return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); +} + +/********************************************************************* + * @fn ETH_GetCurrentTxDescStartAddress + * + * @brief Get the ETHERNET DMA DMACHTDR register value. + * + * @return The value of the current Tx desc start address. + */ +uint32_t ETH_GetCurrentTxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHTDR)); +} + +/********************************************************************* + * @fn ETH_GetCurrentRxDescStartAddress + * + * @brief Get the ETHERNET DMA DMACHRDR register value. + * + * @return The value of the current Rx desc start address. + */ +uint32_t ETH_GetCurrentRxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHRDR)); +} + +/********************************************************************* + * @fn ETH_GetCurrentTxBufferAddress + * + * @brief Get the ETHERNET DMA DMACHTBAR register value. + * + * @return The value of the current Tx buffer address. + */ +uint32_t ETH_GetCurrentTxBufferAddress(void) +{ + return (DMATxDescToSet->Buffer1Addr); +} + +/********************************************************************* + * @fn ETH_GetCurrentRxBufferAddress + * + * @brief Get the ETHERNET DMA DMACHRBAR register value. + * + * @return The value of the current Rx buffer address. + */ +uint32_t ETH_GetCurrentRxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHRBAR)); +} + +/********************************************************************* + * @fn ETH_ResumeDMATransmission + * + * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register + * + * @return none + */ +void ETH_ResumeDMATransmission(void) +{ + ETH->DMATPDR = 0; +} + +/********************************************************************* + * @fn ETH_ResumeDMAReception + * + * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register. + * + * @return none + */ +void ETH_ResumeDMAReception(void) +{ + ETH->DMARPDR = 0; +} + +/********************************************************************* + * @fn ETH_ResetWakeUpFrameFilterRegisterPointer + * + * @brief Reset Wakeup frame filter register pointer. + * + * @return none + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; +} + +/********************************************************************* + * @fn ETH_SetWakeUpFrameFilterRegister + * + * @brief Populates the remote wakeup frame registers. + * + * @param Buffer - Pointer on remote WakeUp Frame Filter Register buffer data (8 words). + * + * @return none + */ +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) +{ + uint32_t i = 0; + + for(i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) + { + ETH->MACRWUFFR = Buffer[i]; + } +} + +/********************************************************************* + * @fn ETH_GlobalUnicastWakeUpCmd + * + * @brief Enables or disables any unicast packet filtered by the MAC address. + * + * @param NewState - new state of the MAC Global Unicast Wake-Up. + * + * @return none + */ +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; + } +} + +/********************************************************************* + * @fn ETH_GetPMTFlagStatus + * + * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * + * @param ETH_PMT_FLAG - specifies the flag to check. + * + * @return The new state of ETHERNET PMT Flag (SET or RESET). + */ +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_WakeUpFrameDetectionCmd + * + * @brief Enables or disables the MAC Wake-Up Frame Detection. + * + * @param NewState - new state of the MAC Wake-Up Frame Detection. + * + * @return none + */ +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; + } +} + +/********************************************************************* + * @fn ETH_MagicPacketDetectionCmd + * + * @brief Enables or disables the MAC Magic Packet Detection. + * + * @param NewState - new state of the MAC Magic Packet Detection. + * + * @return none + */ +void ETH_MagicPacketDetectionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; + } +} + +/********************************************************************* + * @fn ETH_PowerDownCmd + * + * @brief Enables or disables the MAC Power Down. + * + * @param NewState - new state of the MAC Power Down. + * + * @return none + */ +void ETH_PowerDownCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; + } +} + +/********************************************************************* + * @fn ETH_MMCCounterFreezeCmd + * + * @brief Enables or disables the MMC Counter Freeze. + * + * @param NewState - new state of the MMC Counter Freeze. + * + * @return none + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR |= ETH_MMCCR_MCF; + } + else + { + ETH->MMCCR &= ~ETH_MMCCR_MCF; + } +} + +/********************************************************************* + * @fn ETH_MMCResetOnReadCmd + * + * @brief Enables or disables the MMC Reset On Read. + * + * @param NewState - new state of the MMC Reset On Read. + * + * @return none + */ +void ETH_MMCResetOnReadCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR |= ETH_MMCCR_ROR; + } + else + { + ETH->MMCCR &= ~ETH_MMCCR_ROR; + } +} + +/********************************************************************* + * @fn ETH_MMCCounterRolloverCmd + * + * @brief Enables or disables the MMC Counter Stop Rollover. + * + * @param NewState - new state of the MMC Counter Stop Rollover. + * + * @return none + */ +void ETH_MMCCounterRolloverCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR &= ~ETH_MMCCR_CSR; + } + else + { + ETH->MMCCR |= ETH_MMCCR_CSR; + } +} + +/********************************************************************* + * @fn ETH_MMCCountersReset + * + * @brief Resets the MMC Counters. + * + * @return none + */ +void ETH_MMCCountersReset(void) +{ + ETH->MMCCR |= ETH_MMCCR_CR; +} + +/********************************************************************* + * @fn ETH_MMCITConfig + * + * @brief Enables or disables the specified ETHERNET MMC interrupts. + * + * @param ETH_MMC_IT - specifies the ETHERNET MMC interrupt. + * ETH_MMC_IT_TGF - When Tx good frame counter reaches half the maximum value. + * ETH_MMC_IT_TGFMSC - When Tx good multi col counter reaches half the maximum value. + * ETH_MMC_IT_TGFSC - When Tx good single col counter reaches half the maximum value. + * ETH_MMC_IT_RGUF - When Rx good unicast frames counter reaches half the maximum value. + * ETH_MMC_IT_RFAE - When Rx alignment error counter reaches half the maximum value. + * ETH_MMC_IT_RFCE - When Rx crc error counter reaches half the maximum value. + * NewState - new state of the specified ETHERNET MMC interrupts. + * + * @return none + */ +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) +{ + if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + ETH_MMC_IT &= 0xEFFFFFFF; + + if(NewState != DISABLE) + { + ETH->MMCRIMR &= (~(uint32_t)ETH_MMC_IT); + } + else + { + ETH->MMCRIMR |= ETH_MMC_IT; + } + } + else + { + if(NewState != DISABLE) + { + ETH->MMCTIMR &= (~(uint32_t)ETH_MMC_IT); + } + else + { + ETH->MMCTIMR |= ETH_MMC_IT; + } + } +} + +/********************************************************************* + * @fn ETH_GetMMCITStatus + * + * @brief Checks whether the specified ETHERNET MMC IT is set or not. + * + * @param ETH_MMC_IT - specifies the ETHERNET MMC interrupt. + * ETH_MMC_IT_TxFCGC - When Tx good frame counter reaches half the maximum value. + * ETH_MMC_IT_TxMCGC - When Tx good multi col counter reaches half the maximum value. + * ETH_MMC_IT_TxSCGC - When Tx good single col counter reaches half the maximum value . + * ETH_MMC_IT_RxUGFC - When Rx good unicast frames counter reaches half the maximum value. + * ETH_MMC_IT_RxAEC - When Rx alignment error counter reaches half the maximum value. + * ETH_MMC_IT_RxCEC - When Rx crc error counter reaches half the maximum value. + * + * @return The value of ETHERNET MMC IT (SET or RESET). + */ +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) +{ + ITStatus bitstatus = RESET; + + if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + if((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetMMCRegister + * + * @brief Get the specified ETHERNET MMC register value. + * + * @param ETH_MMCReg - specifies the ETHERNET MMC register. + * ETH_MMCCR - MMC CR register + * ETH_MMCRIR - MMC RIR register + * ETH_MMCTIR - MMC TIR register + * ETH_MMCRIMR - MMC RIMR register + * ETH_MMCTIMR - MMC TIMR register + * ETH_MMCTGFSCCR - MMC TGFSCCR register + * ETH_MMCTGFMSCCR - MMC TGFMSCCR register + * ETH_MMCTGFCR - MMC TGFCR register + * ETH_MMCRFCECR - MMC RFCECR register + * ETH_MMCRFAECR - MMC RFAECR register + * ETH_MMCRGUFCR - MMC RGUFCRregister + * + * @return The value of ETHERNET MMC Register value. + */ +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) +{ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampAddend + * + * @brief Updated the PTP block for fine correction with the Time Stamp Addend register value. + * + * @return none + */ +void ETH_EnablePTPTimeStampAddend(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampInterruptTrigger + * + * @brief Enable the PTP Time Stamp interrupt trigger + * + * @return none + */ +void ETH_EnablePTPTimeStampInterruptTrigger(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampUpdate + * + * @brief Updated the PTP system time with the Time Stamp Update register value. + * + * @return none + */ +void ETH_EnablePTPTimeStampUpdate(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; +} + +/********************************************************************* + * @fn ETH_InitializePTPTimeStamp + * + * @brief Initialize the PTP Time Stamp. + * + * @return none + */ +void ETH_InitializePTPTimeStamp(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; +} + +/********************************************************************* + * @fn ETH_PTPUpdateMethodConfig + * + * @brief Selects the PTP Update method. + * + * @param UpdateMethod - the PTP Update method. + * + * @return none + */ +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) +{ + if(UpdateMethod != ETH_PTP_CoarseUpdate) + { + ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU; + } + else + { + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); + } +} + +/********************************************************************* + * @fn ETH_PTPTimeStampCmd + * + * @brief Enables or disables the PTP time stamp for transmit and receive frames. + * + * @param NewState - new state of the PTP time stamp for transmit and receive frames. + * + * @return none + */ +void ETH_PTPTimeStampCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->PTPTSCR |= ETH_PTPTSCR_TSE; + } + else + { + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE); + } +} + +/********************************************************************* + * @fn ETH_GetPTPFlagStatus + * + * @brief Checks whether the specified ETHERNET PTP flag is set or not. + * + * @param The new state of ETHERNET PTP Flag (SET or RESET). + * + * @return none + */ +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_SetPTPSubSecondIncrement + * + * @brief Sets the system time Sub-Second Increment value. + * + * @param SubSecondValue - specifies the PTP Sub-Second Increment Register value. + * + * @return none + */ +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) +{ + ETH->PTPSSIR = SubSecondValue; +} + +/********************************************************************* + * @fn ETH_SetPTPTimeStampUpdate + * + * @brief Sets the Time Stamp update sign and values. + * + * @param Sign - specifies the PTP Time update value sign. + * SecondValue - specifies the PTP Time update second value. + * SubSecondValue - specifies the PTP Time update sub-second value. + * + * @return none + */ +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) +{ + ETH->PTPTSHUR = SecondValue; + ETH->PTPTSLUR = Sign | SubSecondValue; +} + +/********************************************************************* + * @fn ETH_SetPTPTimeStampAddend + * + * @brief Sets the Time Stamp Addend value. + * + * @param Value - specifies the PTP Time Stamp Addend Register value. + * + * @return none + */ +void ETH_SetPTPTimeStampAddend(uint32_t Value) +{ + /* Set the PTP Time Stamp Addend Register */ + ETH->PTPTSAR = Value; +} + +/********************************************************************* + * @fn ETH_SetPTPTargetTime + * + * @brief Sets the Target Time registers values. + * + * @param HighValue - specifies the PTP Target Time High Register value. + * LowValue - specifies the PTP Target Time Low Register value. + * + * @return none + */ +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) +{ + ETH->PTPTTHR = HighValue; + ETH->PTPTTLR = LowValue; +} + +/********************************************************************* + * @fn ETH_GetPTPRegister + * + * @brief Get the specified ETHERNET PTP register value. + * + * @param ETH_PTPReg - specifies the ETHERNET PTP register. + * ETH_PTPTSCR - Sub-Second Increment Register + * ETH_PTPSSIR - Sub-Second Increment Register + * ETH_PTPTSHR - Time Stamp High Register + * ETH_PTPTSLR - Time Stamp Low Register + * ETH_PTPTSHUR - Time Stamp High Update Register + * ETH_PTPTSLUR - Time Stamp Low Update Register + * ETH_PTPTSAR - Time Stamp Addend Register + * ETH_PTPTTHR - Target Time High Register + * ETH_PTPTTLR - Target Time Low Register + * + * @return The value of ETHERNET PTP Register value. + */ +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) +{ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); +} + +/********************************************************************* + * @fn ETH_DMAPTPTxDescChainInit + * + * @brief Initializes the DMA Tx descriptors in chain mode with PTP. + * + * @param DMATxDescTab - Pointer on the first Tx desc list. + * DMAPTPTxDescTab - Pointer on the first PTP Tx desc list. + * TxBuff - Pointer on the first TxBuffer list. + * TxBuffCount - Number of the used Tx desc in the list. + * + * @return none. + */ +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, + uint8_t *TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + DMAPTPTxDescToSet = DMAPTPTxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (TxBuffCount - 1)) + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab; + } + + (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr; + (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; + } + + (&DMAPTPTxDescTab[i - 1])->Status = (uint32_t)DMAPTPTxDescTab; + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_DMAPTPRxDescChainInit + * + * @brief Initializes the DMA Rx descriptors in chain mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * DMAPTPRxDescTab - Pointer on the first PTP Rx desc list. + * RxBuff - Pointer on the first RxBuffer list. + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none. + */ +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, + uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + DMAPTPRxDescToGet = DMAPTPRxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (RxBuffCount - 1)) + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + + (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr; + (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; + } + + (&DMAPTPRxDescTab[i - 1])->Status = (uint32_t)DMAPTPRxDescTab; + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_HandlePTPTxPkt + * + * @brief Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values. + * + * @param ppkt - pointer to application packet buffer to transmit. + * FrameLength - Tx Packet size. + * PTPTxTab - Pointer on the first PTP Tx table to store Time stamp values. + * + * @return none. + */ +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) +{ + uint32_t offset = 0, timeout = 0; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + for(offset = 0; offset < FrameLength; offset++) + { + (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset)); + } + + DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF); + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_TBUS; + ETH->DMATPDR = 0; + } + + do + { + timeout++; + } while(!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); + + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + + DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; + *PTPTxTab++ = DMATxDescToSet->Buffer1Addr; + *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Buffer2NextDescAddr); + if(DMAPTPTxDescToSet->Status != 0) + { + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Status); + } + else + { + DMAPTPTxDescToSet++; + } + } + else + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + } + else + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_HandlePTPRxPkt + * + * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values. + * + * @param ppkt - pointer to application packet receive buffer. + * PTPRxTab - Pointer on the first PTP Rx table to store Time stamp values. + * + * @return ETH_ERROR - if there is error in reception. + * framelength - received packet size if packet reception is correct. + */ +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) +{ + uint32_t offset = 0, framelength = 0; + + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + for(offset = 0; offset < framelength; offset++) + { + (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset)); + } + } + else + { + framelength = ETH_ERROR; + } + + if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_RBUS; + ETH->DMARPDR = 0; + } + + *PTPRxTab++ = DMARxDescToGet->Buffer1Addr; + *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr; + DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Buffer2NextDescAddr); + if(DMAPTPRxDescToGet->Status != 0) + { + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Status); + } + else + { + DMAPTPRxDescToGet++; + } + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return (framelength); +} + +/********************************************************************* + * @fn RGMII_TXC_Delay + * + * @brief Delay time. + * + * @return none + */ +void RGMII_TXC_Delay(uint8_t clock_polarity, uint8_t delay_time) +{ + if(clock_polarity) + { + ETH->MACCR |= (uint32_t)(1 << 1); + } + else + { + ETH->MACCR &= ~(uint32_t)(1 << 1); + } + if(delay_time <= 7) + { + ETH->MACCR |= (uint32_t)(delay_time << 29); + } +} diff --git a/libraries/sdk/Peripheral/ch32v30x_eth.h b/libraries/sdk/Peripheral/ch32v30x_eth.h new file mode 100644 index 0000000..d244c2c --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_eth.h @@ -0,0 +1,1332 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_eth.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* ETH firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_ETH_H +#define __CH32V30x_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +#define PHY_10BASE_T_LINKED 1 +#define PHY_10BASE_T_NOT_LINKED 0 + +#define DMA_TPS_Mask ((uint32_t)0x00700000) +#define DMA_RPS_Mask ((uint32_t)0x000E0000) + +/* ETH Init structure definition */ +typedef struct { + uint32_t ETH_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex). + This parameter can be a value of @ref ETH_AutoNegotiation */ + + uint32_t ETH_Watchdog; /* Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref ETH_watchdog */ + + uint32_t ETH_Jabber; /* Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref ETH_Jabber */ + + uint32_t ETH_InterFrameGap; /* Selects the minimum IFG between frames during transmission + This parameter can be a value of @ref ETH_Inter_Frame_Gap */ + + uint32_t ETH_CarrierSense; /* Selects or not the Carrier Sense + This parameter can be a value of @ref ETH_Carrier_Sense */ + + uint32_t ETH_Speed; /* Sets the Ethernet speed: 10/100 Mbps + This parameter can be a value of @ref ETH_Speed */ + + uint32_t ETH_ReceiveOwn; /* Selects or not the ReceiveOwn + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode + This parameter can be a value of @ref ETH_Receive_Own */ + + uint32_t ETH_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode + This parameter can be a value of @ref ETH_Loop_Back_Mode */ + + uint32_t ETH_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref ETH_Duplex_Mode */ + + uint32_t ETH_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. + This parameter can be a value of @ref ETH_Checksum_Offload */ + + uint32_t ETH_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a colision occurs (Half-Duplex mode) + This parameter can be a value of @ref ETH_Retry_Transmission */ + + uint32_t ETH_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping + This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ + + uint32_t ETH_BackOffLimit; /* Selects the BackOff limit value + This parameter can be a value of @ref ETH_Back_Off_Limit */ + + uint32_t ETH_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode) + This parameter can be a value of @ref ETH_Deferral_Check */ + + uint32_t ETH_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering) + This parameter can be a value of @ref ETH_Receive_All */ + + uint32_t ETH_SourceAddrFilter; /* Selects the Source Address Filter mode + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + + uint32_t ETH_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + This parameter can be a value of @ref ETH_Pass_Control_Frames */ + + uint32_t ETH_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames + This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ + + uint32_t ETH_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + + uint32_t ETH_PromiscuousMode; /* Selects or not the Promiscuous Mode + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + + uint32_t ETH_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ + + uint32_t ETH_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ + + uint32_t ETH_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */ + + uint32_t ETH_HashTableLow; /* This field holds the lower 32 bits of Hash table. */ + + uint32_t ETH_PauseTime; /* This field holds the value to be used in the Pause Time field in the + transmit control frame */ + + uint32_t ETH_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames + This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ + + uint32_t ETH_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame + This parameter can be a value of @ref ETH_Pause_Low_Threshold */ + + uint32_t ETH_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address) + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + + uint32_t ETH_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + + uint32_t ETH_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + + uint32_t ETH_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering + This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ + + uint32_t ETH_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */ + + uint32_t ETH_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames + This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ + + uint32_t ETH_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode + This parameter can be a value of @ref ETH_Receive_Store_Forward */ + + uint32_t ETH_FlushReceivedFrame; /* Enables or disables the flushing of received frames + This parameter can be a value of @ref ETH_Flush_Received_Frame */ + + uint32_t ETH_TransmitStoreForward; /* Enables or disables Transmit store and forward mode + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + + uint32_t ETH_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control + This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ + + uint32_t ETH_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames + This parameter can be a value of @ref ETH_Forward_Error_Frames */ + + uint32_t ETH_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ + + uint32_t ETH_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO + This parameter can be a value of @ref ETH_Receive_Threshold_Control */ + + uint32_t ETH_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. + This parameter can be a value of @ref ETH_Second_Frame_Operate */ + + uint32_t ETH_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats + This parameter can be a value of @ref ETH_Address_Aligned_Beats */ + + uint32_t ETH_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers + This parameter can be a value of @ref ETH_Fixed_Burst */ + + uint32_t ETH_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction + This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ + + uint32_t ETH_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction + This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ + + uint32_t ETH_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */ + + uint32_t ETH_DMAArbitration; /* Selects the DMA Tx/Rx arbitration + This parameter can be a value of @ref ETH_DMA_Arbitration */ +}ETH_InitTypeDef; + + + +/* ETH delay.Just for Ethernet */ +#define _eth_delay_ ETH_Delay /* Default _eth_delay_ function with less precise timing */ + +/* definition for Ethernet frame */ +#define ETH_MAX_PACKET_SIZE 1520 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /* Ethernet CRC */ +#define ETH_EXTRA 2 /* Extra bytes in some cases */ +#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ + +/* ETH DMA structure definition */ +typedef struct +{ + uint32_t Status; /* Status */ + uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /* Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ +} ETH_DMADESCTypeDef; + +/** + DMA Tx Desciptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ------------------------------------------------------------------------------------------------ +*/ + + +/* Bit or field definition of TDES0 register (DMA Tx descriptor status register)*/ +#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /* Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /* Last Segment */ +#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /* First Segment */ +#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /* Disable CRC */ +#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /* Disable Padding */ +#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /* Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /* Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /* Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /* IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /* Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /* Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /* Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /* IP Header Error */ +#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /* Jabber Timeout */ +#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /* Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /* No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /* Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /* VLAN Frame */ +#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /* Collision Count */ +#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /* Excessive Deferral */ +#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /* Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /* Deferred Bit */ + +/* Field definition of TDES1 register */ +#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /* Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /* Transmit Buffer1 Size */ + +/* Field definition of TDES2 register */ +#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of TDES3 register */ +#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/** + DMA Rx Desciptor + --------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ---------------------------------------------------------------------------------------------------------------------- +*/ + +/* Bit or field definition of RDES0 register (DMA Rx descriptor status register) */ +#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /* DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /* Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /* Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /* SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /* Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /* VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /* First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /* Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /* IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /* Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /* Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /* CRC error */ +#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/* Bit or field definition of RDES1 register */ +#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /* Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /* Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /* Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /* Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /* Receive Buffer1 Size */ + +/* Field definition of RDES2 register */ +#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of RDES3 register */ +#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/* Timeout threshold of Reading or writing PHY registers */ +#define PHY_READ_TO ((uint32_t)0x004FFFFF) +#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) + +/* Delay time after reset PHY */ +#define PHY_ResetDelay ((uint32_t)0x000FFFFF) + +/* Delay time after configure PHY */ +#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) + +/* PHY basic register */ +#define PHY_BCR 0x0 /*PHY transceiver Basic Control Register */ +#define PHY_BSR 0x01 /*PHY transceiver Basic Status Register?*/ +#define PHY_BMCR PHY_BCR +#define PHY_BMSR PHY_BSR +#define PHY_STATUS 0x10 +#define PHY_MDIX 0x1E + +/* Bit or field definition for PHY basic control register */ +#define PHY_Reset ((uint16_t)0x8000) /* PHY Reset */ +#define PHY_Loopback ((uint16_t)0x4000) /* Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /* Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /* Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /* Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /* Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((uint16_t)0x1000) /* Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /* Restart auto-negotiation function */ +#define PHY_Powerdown ((uint16_t)0x0800) /* Select the power down mode */ +#define PHY_Isolate ((uint16_t)0x0400) /* Isolate PHY from MII */ + +/* Bit or field definition for PHY basic status register */ +#define PHY_AutoNego_Complete ((uint16_t)0x0020) /* Auto-Negotioation process completed */ +#define PHY_Linked_Status ((uint16_t)0x0004) /* Valid link established */ +#define PHY_Jabber_detection ((uint16_t)0x0002) /* Jabber condition detected */ +#define PHY_RMII_Mode ((uint16_t)0x0020) /* RMII */ + + +/* Internal 10BASE-T PHY 50R*4 pull-up resistance enable or disable */ +#define ETH_Internal_Pull_Up_Res_Enable ((uint32_t)0x00100000) +#define ETH_Internal_Pull_Up_Res_Disable ((uint32_t)0x00000000) + +/* MAC autoNegotiation enable or disable */ +#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) +#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) + +/* MAC watchdog enable or disable */ +#define ETH_Watchdog_Enable ((uint32_t)0x00000000) +#define ETH_Watchdog_Disable ((uint32_t)0x00800000) + +/* Bit description - MAC jabber enable or disable */ +#define ETH_Jabber_Enable ((uint32_t)0x00000000) +#define ETH_Jabber_Disable ((uint32_t)0x00400000) + +/* Value of minimum IFG between frames during transmission */ +#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /* minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /* minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /* minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /* minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /* minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */ + +/* MAC carrier sense enable or disable */ +#define ETH_CarrierSense_Enable ((uint32_t)0x00000000) +#define ETH_CarrierSense_Disable ((uint32_t)0x00010000) + +/* MAC speed */ +#define ETH_Speed_10M ((uint32_t)0x00000000) +#define ETH_Speed_100M ((uint32_t)0x00004000) +#define ETH_Speed_1000M ((uint32_t)0x00008000) + +/* MAC receive own enable or disable */ +#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) +#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) + +/* MAC Loopback mode enable or disable */ +#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) +#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) + +/* MAC fullDuplex or halfDuplex */ +#define ETH_Mode_FullDuplex ((uint32_t)0x00000800) +#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) + +/* MAC offload checksum enable or disable */ +#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) +#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) + +/* MAC transmission retry enable or disable */ +#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) +#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) + +/* MAC automatic pad CRC strip enable or disable */ +#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) + +/* MAC backoff limitation */ +#define ETH_BackOffLimit_10 ((uint32_t)0x00000000) +#define ETH_BackOffLimit_8 ((uint32_t)0x00000020) +#define ETH_BackOffLimit_4 ((uint32_t)0x00000040) +#define ETH_BackOffLimit_1 ((uint32_t)0x00000060) + +/* MAC deferral check enable or disable */ +#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) +#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) + +/* Bit description : MAC receive all frame enable or disable */ +#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) +#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) + +/* MAC backoff limitation */ +#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) +#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) + +/* MAC Pass control frames */ +#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ + +/* MAC broadcast frames reception */ +#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) + +/* MAC destination address filter */ +#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) + +/* MAC Promiscuous mode enable or disable */ +#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) +#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) + +/* MAC multicast frames filter */ +#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) +#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) + +/* MAC unicast frames filter */ +#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) + +/* Bit description : MAC zero quanta pause */ +#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) + +/* Field description : MAC pause low threshold */ +#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ + +/* MAC unicast pause frame detect enable or disable*/ +#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) + +/* MAC receive flow control frame enable or disable */ +#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) + +/* MAC transmit flow control enable or disable */ +#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) +#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) + +/* MAC VLAN tag comparison */ +#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) +#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) + +/* MAC flag */ +#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /* Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /* MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /* MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /* MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /* PMT flag (on MAC) */ + +/* MAC interrupt */ +#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /* Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /* MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /* MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /* MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /* PMT interrupt (on MAC) */ + +/* MAC address */ +#define ETH_MAC_Address0 ((uint32_t)0x00000000) +#define ETH_MAC_Address1 ((uint32_t)0x00000008) +#define ETH_MAC_Address2 ((uint32_t)0x00000010) +#define ETH_MAC_Address3 ((uint32_t)0x00000018) + +/* MAC address filter select */ +#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) +#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) + +/* MAC address mask */ +#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ + + +/******************************************************************************/ +/* */ +/* MAC Descriptor Register */ +/* */ +/******************************************************************************/ + +/* DMA descriptor segment */ +#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /* Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /* First Segment */ + +/* DMA descriptor checksum setting */ +#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /* Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /* IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + +/* DMA RX & TX buffer */ +#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /* DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /* DMA Rx Desc Buffer2 */ + + +/******************************************************************************/ +/* */ +/* ETH DMA Register */ +/* */ +/******************************************************************************/ + +/* DMA drop TCPIP checksum error frame enable or disable */ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) + +/* DMA receive store forward enable or disable */ +#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) + +/* DMA flush received frame enable or disable */ +#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) + +/* DMA transmit store forward enable or disable */ +#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) +#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) + +/* DMA transmit threshold control */ +#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ + +/* DMA forward error frames */ +#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) + +/* DMA forward undersized good frames enable or disable */ +#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) + +/* DMA receive threshold control */ +#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ + +/* DMA second frame operate enable or disable */ +#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) +#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) + +/* Address aligned beats enable or disable */ +#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) + +/* DMA Fixed burst enable or disable */ +#define ETH_FixedBurst_Enable ((uint32_t)0x00010000) +#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) + + +/* RX DMA burst length */ +#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ + + +/* TX DMA burst length */ +#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ + +/* DMA arbitration_round robin */ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) + +/* DMA interrupt FALG */ +#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /* Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /* Early receive flag */ +#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /* Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /* Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /* Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /* Receive flag */ +#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /* Underflow flag */ +#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /* Overflow flag */ +#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /* Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /* Transmit flag */ + +/* DMA interrupt */ +#define ETH_DMA_IT_PHYLINK ((uint32_t)0x80000000) /* Internal PHY link status change interrupt */ +#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /* Early receive interrupt */ +#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /* Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /* Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /* Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((uint32_t)0x00000040) /* Receive interrupt */ +#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /* Underflow interrupt */ +#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /* Overflow interrupt */ +#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /* Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((uint32_t)0x00000001) /* Transmit interrupt */ + +/* DMA transmit process */ +#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ + +/* DMA receive Process */ +#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ + +/* DMA overflow */ +#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ + + +/********************************************************************************* +* Ethernet PMT defines +**********************************************************************************/ + +/* PMT flag */ +#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ + +/********************************************************************************* +* Ethernet MMC defines +**********************************************************************************/ + +/* MMC TX interrupt flag */ +#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /* When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /* When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /* When Tx good single col counter reaches half the maximum value */ + +/* MMC RX interrupt flag */ +#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /* When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /* When Rx crc error counter reaches half the maximum value */ + + +/* MMC description */ +#define ETH_MMCCR ((uint32_t)0x00000100) /* MMC CR register */ +#define ETH_MMCRIR ((uint32_t)0x00000104) /* MMC RIR register */ +#define ETH_MMCTIR ((uint32_t)0x00000108) /* MMC TIR register */ +#define ETH_MMCRIMR ((uint32_t)0x0000010C) /* MMC RIMR register */ +#define ETH_MMCTIMR ((uint32_t)0x00000110) /* MMC TIMR register */ +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /* MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /* MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((uint32_t)0x00000168) /* MMC TGFCR register */ +#define ETH_MMCRFCECR ((uint32_t)0x00000194) /* MMC RFCECR register */ +#define ETH_MMCRFAECR ((uint32_t)0x00000198) /* MMC RFAECR register */ +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /* MMC RGUFCR register */ + + +/********************************************************************************* +* Ethernet PTP defines +**********************************************************************************/ + +/* PTP fine update method or coarse Update method */ +#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /* Fine Update method */ +#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /* Coarse Update method */ + + +/* PTP time stamp control */ +#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /* Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /* Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /* Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /* Time Stamp Initialize */ + +/* PTP positive/negative time value */ +#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /* Positive time value */ +#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /* Negative time value */ + + +/******************************************************************************/ +/* */ +/* PTP Register */ +/* */ +/******************************************************************************/ +#define ETH_PTPTSCR ((uint32_t)0x00000700) /* PTP TSCR register */ +#define ETH_PTPSSIR ((uint32_t)0x00000704) /* PTP SSIR register */ +#define ETH_PTPTSHR ((uint32_t)0x00000708) /* PTP TSHR register */ +#define ETH_PTPTSLR ((uint32_t)0x0000070C) /* PTP TSLR register */ +#define ETH_PTPTSHUR ((uint32_t)0x00000710) /* PTP TSHUR register */ +#define ETH_PTPTSLUR ((uint32_t)0x00000714) /* PTP TSLUR register */ +#define ETH_PTPTSAR ((uint32_t)0x00000718) /* PTP TSAR register */ +#define ETH_PTPTTHR ((uint32_t)0x0000071C) /* PTP TTHR register */ +#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ + +#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ + #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ + + +/******************************************************************************/ +/* */ +/* ETH MAC Register */ +/* */ +/******************************************************************************/ +#define ETH_MACCR_WD ((unsigned int)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((unsigned int)0x00400000) /* Jabber disable */ +#define ETH_MACCR_IFG ((unsigned int)0x000E0000) /* Inter-frame gap */ +#define ETH_MACCR_IFG_96Bit ((unsigned int)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ + #define ETH_MACCR_IFG_88Bit ((unsigned int)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ + #define ETH_MACCR_IFG_80Bit ((unsigned int)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ + #define ETH_MACCR_IFG_72Bit ((unsigned int)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ + #define ETH_MACCR_IFG_64Bit ((unsigned int)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ + #define ETH_MACCR_IFG_56Bit ((unsigned int)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ + #define ETH_MACCR_IFG_48Bit ((unsigned int)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ + #define ETH_MACCR_IFG_40Bit ((unsigned int)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((unsigned int)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((unsigned int)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((unsigned int)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((unsigned int)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((unsigned int)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((unsigned int)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((unsigned int)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((unsigned int)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((unsigned int)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before reschedulinga transmission attempt during retries after a collision: 0 =< r <2^k */ + #define ETH_MACCR_BL_10 ((unsigned int)0x00000000) /* k = min (n, 10) */ + #define ETH_MACCR_BL_8 ((unsigned int)0x00000020) /* k = min (n, 8) */ + #define ETH_MACCR_BL_4 ((unsigned int)0x00000040) /* k = min (n, 4) */ + #define ETH_MACCR_BL_1 ((unsigned int)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((unsigned int)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((unsigned int)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((unsigned int)0x00000004) /* Receiver enable */ + +#define ETH_MACFFR_RA ((unsigned int)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((unsigned int)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((unsigned int)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((unsigned int)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((unsigned int)0x000000C0) /* Pass control frames: 3 cases */ + #define ETH_MACFFR_PCF_BlockAll ((unsigned int)0x00000040) /* MAC filters all control frames from reaching the application */ + #define ETH_MACFFR_PCF_ForwardAll ((unsigned int)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ + #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((unsigned int)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((unsigned int)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((unsigned int)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((unsigned int)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((unsigned int)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((unsigned int)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((unsigned int)0x00000001) /* Promiscuous mode */ + +#define ETH_MACHTHR_HTH ((unsigned int)0xFFFFFFFF) /* Hash table high */ +#define ETH_MACHTLR_HTL ((unsigned int)0xFFFFFFFF) /* Hash table low */ + +#define ETH_MACMIIAR_PA ((unsigned int)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((unsigned int)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((unsigned int)0x0000001C) /* CR clock range: 6 cases */ + #define ETH_MACMIIAR_CR_Div42 ((unsigned int)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ + #define ETH_MACMIIAR_CR_Div16 ((unsigned int)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ETH_MACMIIAR_CR_Div26 ((unsigned int)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((unsigned int)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((unsigned int)0x00000001) /* MII busy */ +#define ETH_MACMIIDR_MD ((unsigned int)0x0000FFFF) /* MII data: read/write data from/to PHY */ +#define ETH_MACFCR_PT ((unsigned int)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((unsigned int)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((unsigned int)0x00000030) /* Pause low threshold: 4 cases */ + #define ETH_MACFCR_PLT_Minus4 ((unsigned int)0x00000000) /* Pause time minus 4 slot times */ + #define ETH_MACFCR_PLT_Minus28 ((unsigned int)0x00000010) /* Pause time minus 28 slot times */ + #define ETH_MACFCR_PLT_Minus144 ((unsigned int)0x00000020) /* Pause time minus 144 slot times */ + #define ETH_MACFCR_PLT_Minus256 ((unsigned int)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((unsigned int)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((unsigned int)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((unsigned int)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((unsigned int)0x00000001) /* Flow control busy/backpressure activate */ + +#define ETH_MACVLANTR_VLANTC ((unsigned int)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((unsigned int)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +#define ETH_MACRWUFFR_D ((unsigned int)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. +Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ + +/* +Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask +Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask +Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask +Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask +Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command +Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset +Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 +Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +#define ETH_MACPMTCSR_WFFRPR ((unsigned int)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((unsigned int)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((unsigned int)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((unsigned int)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((unsigned int)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((unsigned int)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((unsigned int)0x00000001) /* Power Down */ + +#define ETH_MACSR_TSTS ((unsigned int)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((unsigned int)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((unsigned int)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((unsigned int)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((unsigned int)0x00000008) /* PMT status */ + +#define ETH_MACIMR_TSTIM ((unsigned int)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((unsigned int)0x00000008) /* PMT interrupt mask */ + +#define ETH_MACA0HR_MACA0H ((unsigned int)0x0000FFFF) /* MAC address0 high */ + +#define ETH_MACA0LR_MACA0L ((unsigned int)0xFFFFFFFF) /* MAC address0 low */ + +#define ETH_MACA1HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((unsigned int)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ + #define ETH_MACA1HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA1HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA1HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA1HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA1HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA1HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((unsigned int)0x0000FFFF) /* MAC address1 high */ + +#define ETH_MACA1LR_MACA1L ((unsigned int)0xFFFFFFFF) /* MAC address1 low */ + +#define ETH_MACA2HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ + +#define ETH_MACA2HR_MACA2H ((unsigned int)0x0000FFFF) /* MAC address1 high */ +#define ETH_MACA2LR_MACA2L ((unsigned int)0xFFFFFFFF) /* MAC address2 low */ + +#define ETH_MACA3HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ + #define ETH_MACA3HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA3HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA3HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA3HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA3HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA3HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((unsigned int)0x0000FFFF) /* MAC address3 high */ +#define ETH_MACA3LR_MACA3L ((unsigned int)0xFFFFFFFF) /* MAC address3 low */ + +///******************************************************************************/ +///* +///* ETH MMC Register +///* +///******************************************************************************/ +#define ETH_MMCCR_MCFHP ((unsigned int)0x00000020) /* MMC counter Full-Half preset */ +#define ETH_MMCCR_MCP ((unsigned int)0x00000010) /* MMC counter preset */ +#define ETH_MMCCR_MCF ((unsigned int)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((unsigned int)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((unsigned int)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((unsigned int)0x00000001) /* Counters Reset */ + +#define ETH_MMCRIR_RGUFS ((unsigned int)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((unsigned int)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((unsigned int)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +#define ETH_MMCTIR_TGFS ((unsigned int)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((unsigned int)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((unsigned int)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +#define ETH_MMCRIMR_RGUFM ((unsigned int)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((unsigned int)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((unsigned int)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +#define ETH_MMCTIMR_TGFM ((unsigned int)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((unsigned int)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((unsigned int)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +#define ETH_MMCTGFSCCR_TGFSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +#define ETH_MMCTGFMSCCR_TGFMSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +#define ETH_MMCTGFCR_TGFC ((unsigned int)0xFFFFFFFF) /* Number of good frames transmitted. */ + +#define ETH_MMCRFCECR_RFCEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +#define ETH_MMCRFAECR_RFAEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +#define ETH_MMCRGUFCR_RGUFC ((unsigned int)0xFFFFFFFF) /* Number of good unicast frames received. */ + +///******************************************************************************/ +///* +///* ETH Precise Clock Protocol Register +///* +///******************************************************************************/ +#define ETH_PTPTSCR_TSCNT ((unsigned int)0x00030000) /* Time stamp clock node type */ +#define ETH_PTPTSSR_TSSMRME ((unsigned int)0x00008000) /* Time stamp snapshot for message relevant to master enable */ +#define ETH_PTPTSSR_TSSEME ((unsigned int)0x00004000) /* Time stamp snapshot for event message enable */ +#define ETH_PTPTSSR_TSSIPV4FE ((unsigned int)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTPTSSR_TSSIPV6FE ((unsigned int)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTPTSSR_TSSPTPOEFE ((unsigned int)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTPTSSR_TSPTPPSV2E ((unsigned int)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ +#define ETH_PTPTSSR_TSSSR ((unsigned int)0x00000200) /* Time stamp Sub-seconds rollover */ +#define ETH_PTPTSSR_TSSARFE ((unsigned int)0x00000100) /* Time stamp snapshot for all received frames enable */ + +#define ETH_PTPTSCR_TSARU ((unsigned int)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((unsigned int)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((unsigned int)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((unsigned int)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((unsigned int)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((unsigned int)0x00000001) /* Time stamp enable */ + +#define ETH_PTPSSIR_STSSI ((unsigned int)0x000000FF) /* System time Sub-second increment value */ + +#define ETH_PTPTSHR_STS ((unsigned int)0xFFFFFFFF) /* System Time second */ + +#define ETH_PTPTSLR_STPNS ((unsigned int)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((unsigned int)0x7FFFFFFF) /* System Time sub-seconds */ + +#define ETH_PTPTSHUR_TSUS ((unsigned int)0xFFFFFFFF) /* Time stamp update seconds */ + +#define ETH_PTPTSLUR_TSUPNS ((unsigned int)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((unsigned int)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +#define ETH_PTPTSAR_TSA ((unsigned int)0xFFFFFFFF) /* Time stamp addend */ + +#define ETH_PTPTTHR_TTSH ((unsigned int)0xFFFFFFFF) /* Target time stamp high */ + +#define ETH_PTPTTLR_TTSL ((unsigned int)0xFFFFFFFF) /* Target time stamp low */ + +#define ETH_PTPTSSR_TSTTR ((unsigned int)0x00000020) /* Time stamp target time reached */ +#define ETH_PTPTSSR_TSSO ((unsigned int)0x00000010) /* Time stamp seconds overflow */ + +///******************************************************************************/ +///* +///* ETH DMA Register +///* +///******************************************************************************/ +#define ETH_DMABMR_AAB ((unsigned int)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((unsigned int)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((unsigned int)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((unsigned int)0x007E0000) /* RxDMA PBL */ + #define ETH_DMABMR_RDP_1Beat ((unsigned int)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ + #define ETH_DMABMR_RDP_2Beat ((unsigned int)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ + #define ETH_DMABMR_RDP_4Beat ((unsigned int)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_8Beat ((unsigned int)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_16Beat ((unsigned int)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_32Beat ((unsigned int)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_4Beat ((unsigned int)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_4xPBL_8Beat ((unsigned int)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_4xPBL_16Beat ((unsigned int)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_4xPBL_32Beat ((unsigned int)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_64Beat ((unsigned int)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ + #define ETH_DMABMR_RDP_4xPBL_128Beat ((unsigned int)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((unsigned int)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_1_1 ((unsigned int)0x00000000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_2_1 ((unsigned int)0x00004000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_3_1 ((unsigned int)0x00008000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_4_1 ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((unsigned int)0x00003F00) /* Programmable burst length */ + #define ETH_DMABMR_PBL_1Beat ((unsigned int)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ + #define ETH_DMABMR_PBL_2Beat ((unsigned int)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ + #define ETH_DMABMR_PBL_4Beat ((unsigned int)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_8Beat ((unsigned int)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_16Beat ((unsigned int)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_32Beat ((unsigned int)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_4Beat ((unsigned int)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_4xPBL_8Beat ((unsigned int)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_4xPBL_16Beat ((unsigned int)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_4xPBL_32Beat ((unsigned int)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_64Beat ((unsigned int)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ + #define ETH_DMABMR_PBL_4xPBL_128Beat ((unsigned int)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_EDE ((unsigned int)0x00000080) /* Enhanced Descriptor Enable */ +#define ETH_DMABMR_DSL ((unsigned int)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((unsigned int)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((unsigned int)0x00000001) /* Software reset */ + +#define ETH_DMATPDR_TPD ((unsigned int)0xFFFFFFFF) /* Transmit poll demand */ + +#define ETH_DMARPDR_RPD ((unsigned int)0xFFFFFFFF) /* Receive poll demand */ + +#define ETH_DMARDLAR_SRL ((unsigned int)0xFFFFFFFF) /* Start of receive list */ + +#define ETH_DMATDLAR_STL ((unsigned int)0xFFFFFFFF) /* Start of transmit list */ + +#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ + #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ + +#define ETH_DMAOMR_DTCEFD ((unsigned int)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((unsigned int)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((unsigned int)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((unsigned int)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((unsigned int)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((unsigned int)0x0001C000) /* Transmit threshold control */ + #define ETH_DMAOMR_TTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ + #define ETH_DMAOMR_TTC_128Bytes ((unsigned int)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ + #define ETH_DMAOMR_TTC_192Bytes ((unsigned int)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ + #define ETH_DMAOMR_TTC_256Bytes ((unsigned int)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ + #define ETH_DMAOMR_TTC_40Bytes ((unsigned int)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ + #define ETH_DMAOMR_TTC_32Bytes ((unsigned int)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ + #define ETH_DMAOMR_TTC_24Bytes ((unsigned int)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ + #define ETH_DMAOMR_TTC_16Bytes ((unsigned int)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((unsigned int)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((unsigned int)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((unsigned int)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((unsigned int)0x00000018) /* receive threshold control */ + #define ETH_DMAOMR_RTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ + #define ETH_DMAOMR_RTC_32Bytes ((unsigned int)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ + #define ETH_DMAOMR_RTC_96Bytes ((unsigned int)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ + #define ETH_DMAOMR_RTC_128Bytes ((unsigned int)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((unsigned int)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((unsigned int)0x00000002) /* Start/stop receive */ + +#define ETH_DMAIER_NISE ((unsigned int)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((unsigned int)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((unsigned int)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((unsigned int)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((unsigned int)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((unsigned int)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((unsigned int)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((unsigned int)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((unsigned int)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((unsigned int)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((unsigned int)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((unsigned int)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((unsigned int)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((unsigned int)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((unsigned int)0x00000001) /* Transmit interrupt enable */ + +#define ETH_DMAMFBOCR_OFOC ((unsigned int)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((unsigned int)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((unsigned int)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((unsigned int)0x0000FFFF) /* Number of frames missed by the controller */ + +#define ETH_DMACHTDR_HTDAP ((unsigned int)0xFFFFFFFF) /* Host transmit descriptor address pointer */ +#define ETH_DMACHRDR_HRDAP ((unsigned int)0xFFFFFFFF) /* Host receive descriptor address pointer */ +#define ETH_DMACHTBAR_HTBAP ((unsigned int)0xFFFFFFFF) /* Host transmit buffer address pointer */ +#define ETH_DMACHRBAR_HRBAP ((unsigned int)0xFFFFFFFF) /* Host receive buffer address pointer */ + + +#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ + +/* ETHERNET MACMIIAR register Mask */ +#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) + +/* ETHERNET MACCR register Mask */ +#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) + +/* ETHERNET MACFCR register Mask */ +#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) + +/* ETHERNET DMAOMR register Mask */ +#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) + +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8 + +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 + +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 + +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 + +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET errors */ +#define ETH_ERROR ((uint32_t)0) +#define ETH_SUCCESS ((uint32_t)1) + + +void ETH_DeInit(void); +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); +void ETH_SoftwareReset(void); +FlagStatus ETH_GetSoftwareResetStatus(void); +FlagStatus ETH_GetlinkStaus (void); +void ETH_Start(void); +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength); +void delay_clk (uint32_t nCount); +void printf_dmasr (void); +void print_dmasr_tbus(void); +void print_dmasr_rps(void); +void print_dmasr_tps(void); +uint32_t ETH_HandleRxPkt(uint8_t *ppkt); +uint32_t ETH_GetRxPktSize(void); +void ETH_DropRxPkt(void); +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg); +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue); +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState); + +void ETH_MACTransmissionCmd(FunctionalState NewState); +void ETH_MACReceptionCmd(FunctionalState NewState); +FlagStatus ETH_GetFlowControlBusyStatus(void); +void ETH_InitiatePauseControlFrame(void); +void ETH_BackPressureActivationCmd(FunctionalState NewState); +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr); +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr); +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); + +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount); +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount); +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment); +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount); +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); + +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); +uint32_t ETH_GetTransmitProcessState(void); +uint32_t ETH_GetReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +FlagStatus ETH_GetFlushTransmitFIFOStatus(void); +void ETH_DMATransmissionCmd(FunctionalState NewState); +void ETH_DMAReceptionCmd(FunctionalState NewState); +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); +uint32_t ETH_GetRxOverflowMissedFrameCounter(void); +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); +uint32_t ETH_GetCurrentTxDescStartAddress(void); +uint32_t ETH_GetCurrentRxDescStartAddress(void); +uint32_t ETH_GetCurrentTxBufferAddress(void); +uint32_t ETH_GetCurrentRxBufferAddress(void); +void ETH_ResumeDMATransmission(void); +void ETH_ResumeDMAReception(void); + +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); +void ETH_MagicPacketDetectionCmd(FunctionalState NewState); +void ETH_PowerDownCmd(FunctionalState NewState); + +void ETH_MMCCounterFreezeCmd(FunctionalState NewState); +void ETH_MMCResetOnReadCmd(FunctionalState NewState); +void ETH_MMCCounterRolloverCmd(FunctionalState NewState); +void ETH_MMCCountersReset(void); +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); + +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab); +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab); +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +void ETH_EnablePTPTimeStampAddend(void); +void ETH_EnablePTPTimeStampInterruptTrigger(void); +void ETH_EnablePTPTimeStampUpdate(void); +void ETH_InitializePTPTimeStamp(void); +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod); +void ETH_PTPTimeStampCmd(FunctionalState NewState); +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG); +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue); +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue); +void ETH_SetPTPTimeStampAddend(uint32_t Value); +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue); +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg); +void RGMII_TXC_Delay(uint8_t clock_polarity,uint8_t delay_time); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/libraries/sdk/Peripheral/ch32v30x_exti.c b/libraries/sdk/Peripheral/ch32v30x_exti.c new file mode 100644 index 0000000..afeb0ab --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_exti.c @@ -0,0 +1,180 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_exti.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the EXTI firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +***************************************************************************************/ +#include "ch32v30x_exti.h" + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x000FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/libraries/sdk/Peripheral/ch32v30x_exti.h b/libraries/sdk/Peripheral/ch32v30x_exti.h new file mode 100644 index 0000000..2b2d0c3 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_exti.h @@ -0,0 +1,90 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_exti.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* EXTI firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_EXTI_H +#define __CH32V30x_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD/USBFS OTG + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBHS Wakeup event */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/libraries/sdk/Peripheral/ch32v30x_flash.c b/libraries/sdk/Peripheral/ch32v30x_flash.c new file mode 100644 index 0000000..0a5750c --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_flash.c @@ -0,0 +1,981 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_flash.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the FLASH firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +***************************************************************************************/ +#include "ch32v30x_flash.h" + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FAST_LOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BER32 ((uint32_t)0x00040000) +#define CR_BER64 ((uint32_t)0x00080000) +#define CR_PG_STRT ((uint32_t)0x00200000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WR_BSY ((uint32_t)0x00000002) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00005000) + +/********************************************************************* + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program Erase Controller. + * + * @return none + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_UnlockBank1 + * + * @brief Unlocks the FLASH Bank1 Program Erase Controller. + * equivalent to FLASH_Unlock function. + * + * @return none + */ +void FLASH_UnlockBank1(void) +{ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return none + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/********************************************************************* + * @fn FLASH_LockBank1 + * + * @brief Locks the FLASH Bank1 Program Erase Controller. + * + * @return none + */ +void FLASH_LockBank1(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/********************************************************************* + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page(page size 4KB). + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EraseAllBank1Pages + * + * @brief Erases all Bank1 FLASH pages. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank1Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + return status; +} + +/********************************************************************* + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + uint32_t Address = 0x1FFFF800; + __IO uint8_t i; + + FLASH_Status status = FLASH_COMPLETE; + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= CR_OPTER_Reset; + FLASH->CTLR |= CR_OPTPG_Set; + OB->RDPR = (uint16_t)rdptmp; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + + /* Write 0xFF */ + FLASH->CTLR |= CR_OPTPG_Set; + + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Address + 2 * i) = 0x00FF; + while(FLASH->STATR & SR_BSY) + ; + } + + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramWord + * + * @brief Programs a word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + + *(__IO uint16_t *)Address = (uint16_t)Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + tmp = Address + 2; + *(__IO uint16_t *)tmp = Data >> 16; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + else + { + FLASH->CTLR &= CR_PG_Reset; + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramHalfWord + * + * @brief Programs a half word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + *(__IO uint16_t *)Address = Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramOptionByteData + * + * @brief Programs a half word at a specified Option Byte Data address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[((Address - 0x1FFFF800) / 2)] = ((((uint16_t) ~(Data)) << 8) | ((uint16_t)Data)); + + FLASH->CTLR |= CR_OPTPG_Set; + + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + + FLASH->CTLR &= ~CR_OPTPG_Set; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Sectors - specifies the address of the pages to be write protected. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + FLASH_Sectors = (uint32_t)(~FLASH_Sectors); + WRP0_Data = (uint16_t)(FLASH_Sectors & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Sectors & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Sectors & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Sectors & WRP3_Mask) >> 24); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[4] = WRP0_Data; + pbuf[5] = WRP1_Data; + pbuf[6] = WRP2_Data; + pbuf[7] = WRP3_Data; + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_ReadOutProtection + * + * @brief Enables or disables the read out protection. + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + if(NewState == DISABLE) + pbuf[0] = 0x5AA5; + else + pbuf[0] = 0x00FF; + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. + * + * @param OB_IWDG - Selects the IWDG mode + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STOP - Reset event when entering STOP mode. + * OB_STOP_NoRST - No reset generated when entering in STOP + * OB_STOP_RST - Reset generated when entering in STOP + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY + * OB_STDBY_RST - Reset generated when entering in STANDBY + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt + * FLASH_IT_EOP - FLASH end of operation Interrupt + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_PGERR - FLASH Program error flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_PGERR - FLASH Program error flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + FLASH->STATR = FLASH_FLAG; +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + Page_Address &= 0xFFFFFF00; + + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_ER; +} + +/********************************************************************* + * @fn FLASH_EraseBlock_32K_Fast + * + * @brief Erases a specified FLASH Block (1Block = 32KByte). + * + * @param Block_Address - The block address to be erased. + * + * @return none + */ +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) +{ + Block_Address &= 0xFFFF8000; + + FLASH->CTLR |= CR_BER32; + FLASH->ADDR = Block_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_BER32; +} + +/********************************************************************* + * @fn FLASH_EraseBlock_64K_Fast + * + * @brief Erases a specified FLASH Block (1Block = 64KByte). + * + * @param Block_Address - The block address to be erased. + * + * @return none + */ +void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address) +{ + Block_Address &= 0xFFFF0000; + + FLASH->CTLR |= CR_BER64; + FLASH->ADDR = Block_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_BER64; +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf) +{ + uint8_t size = 64; + + Page_Address &= 0xFFFFFF00; + + FLASH->CTLR |= CR_PAGE_PG; + while(FLASH->STATR & SR_BSY) + ; + while(FLASH->STATR & SR_WR_BSY) + ; + + while(size) + { + *(uint32_t *)Page_Address = *(uint32_t *)pbuf; + Page_Address += 4; + pbuf += 1; + size -= 1; + while(FLASH->STATR & SR_WR_BSY) + ; + } + + FLASH->CTLR |= CR_PG_STRT; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_Access_Clock_Cfg + * + * @brief Config FLASH Access Clock(Need to unlock ) + * + * @param FLASH_Access_CLK - + * FLASH_Access_SYSTEM_HALF - System clock/2 + * FLASH_Access_SYSTEM - System clock + * + * @return none + */ +void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK) +{ + FLASH->CTLR &= ~(1 << 25); + FLASH->CTLR |= FLASH_Access_CLK; +} + +/********************************************************************* + * @fn FLASH_Enhance_Mode + * + * @brief Read FLASH Enhance Mode + * + * @param + * Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return none + */ +void FLASH_Enhance_Mode(FunctionalState NewState) +{ + if(NewState) + { + FLASH->CTLR |= (1 << 24); + } + else + { + FLASH->CTLR &= ~(1 << 24); + FLASH->CTLR |= (1 << 22); + } +} + diff --git a/libraries/sdk/Peripheral/ch32v30x_flash.h b/libraries/sdk/Peripheral/ch32v30x_flash.h new file mode 100644 index 0000000..1ae39d5 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_flash.h @@ -0,0 +1,144 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_flash.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the FLASH +* firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_FLASH_H +#define __CH32V30x_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + + +/* Write Protect */ +#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */ + +#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /* FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/* FLASH_Access_CLK */ +#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Access Clock = SYSTEM/2 */ +#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* FLASH Access Clock = SYSTEM */ + + +/*Functions used for all devices*/ +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); +void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t* pbuf); +void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK); +void FLASH_Enhance_Mode(FunctionalState NewState); + +/* New function used for all devices */ +void FLASH_UnlockBank1(void); +void FLASH_LockBank1(void); +FLASH_Status FLASH_EraseAllBank1Pages(void); +FLASH_Status FLASH_GetBank1Status(void); +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); + +#ifdef __cplusplus +} +#endif + + +#endif + diff --git a/libraries/sdk/Peripheral/ch32v30x_fsmc.c b/libraries/sdk/Peripheral/ch32v30x_fsmc.c new file mode 100644 index 0000000..6da3b53 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_fsmc.c @@ -0,0 +1,501 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_fsmc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the FSMC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_fsmc.h" +#include "ch32v30x_rcc.h" + +/* FSMC BCRx Mask */ +#define BCR_MBKEN_Set ((uint32_t)0x00000001) +#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_Set ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_Set ((uint32_t)0x00000004) +#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_Set ((uint32_t)0x00000040) +#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) +#define PCR_MemoryType_NAND ((uint32_t)0x00000008) + +/********************************************************************* + * @fn FSMC_NORSRAMDeInit + * + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * + * @param FSMC_Bank- + * FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1. + * + * @return none + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/********************************************************************* + * @fn FSMC_NANDDeInit + * + * @brief Deinitializes the FSMC NAND Banks registers to their default + * reset values. + * + * @param FSMC_Bank - + * FSMC_Bank2_NAND - FSMC Bank2 NAND. + * + * @return none + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } +} + +/********************************************************************* + * @fn FSMC_NORSRAMInit + * + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * + * @param SMC_NORSRAMInitStruct:pointer to a FSMC_NORSRAMInitTypeDef + * structure that contains the configuration information for the FSMC NOR/SRAM + * specified Banks. + * + * @return none + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct) +{ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; + } + + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank + 1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/********************************************************************* + * @fn FSMC_NANDInit + * + * @brief Initializes the FSMC NAND Banks according to the specified + * parameters in the FSMC_NANDInitStruct. + * + * @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef + * structure that contains the configuration information for the FSMC + * NAND specified Banks. + * + * @return none + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MemoryType_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } +} + +/********************************************************************* + * @fn FSMC_NORSRAMStructInit + * + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * + * @param FSMC_NORSRAMInitStruct - pointer to a FSMC_NORSRAMInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct) +{ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/********************************************************************* + * @fn FSMC_NANDStructInit + * + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * + * @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct) +{ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/********************************************************************* + * @fn FSMC_NORSRAMCmd + * + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1 + * FSMC_Bank1_NORSRAM2 - FSMC Bank1 NOR/SRAM2 + * FSMC_Bank1_NORSRAM3 - FSMC Bank1 NOR/SRAM3 + * FSMC_Bank1_NORSRAM4 - FSMC Bank1 NOR/SRAM4 + * NewStateENABLE or DISABLE. + * + * @return none + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; + } + else + { + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; + } +} + +/********************************************************************* + * @fn FSMC_NANDCmd + * + * @brief Enables or disables the specified NAND Memory Bank. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_Bank3_NAND - FSMC Bank3 NAND + * NewStat - ENABLE or DISABLE. + * + * @return none + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; + } + } + else + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; + } + } +} + +/********************************************************************* + * @fn FSMC_NANDECCCmd + * + * @brief Enables or disables the FSMC NAND ECC feature. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; + } + } + else + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; + } + } +} + +/********************************************************************* + * @fn FSMC_GetECC + * + * @brief Returns the error correction code register value. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * NewState - ENABLE or DISABLE. + * + * @return eccval - The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + eccval = FSMC_Bank2->ECCR2; + } + + return (eccval); +} + +/********************************************************************* + * @fn FSMC_ITConfig + * + * @brief Enables or disables the specified FSMC interrupts. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_IT - specifies the FSMC interrupt sources to be enabled or disabled. + * FSMC_IT_RisingEdge - Rising edge detection interrupt. + * FSMC_IT_Level - Level edge detection interrupt. + * FSMC_IT_FallingEdge - Falling edge detection interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + } + else + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; + } + } +} + +/********************************************************************* + * @fn FSMC_GetFlagStatus + * + * @brief Checks whether the specified FSMC flag is set or not. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_FLAG - specifies the flag to check. + * FSMC_FLAG_RisingEdge - Rising egde detection Flag. + * FSMC_FLAG_Level - Level detection Flag. + * FSMC_FLAG_FallingEdge - Falling egde detection Flag. + * FSMC_FLAG_FEMPT - Fifo empty Flag. + * NewState - ENABLE or DISABLE. + * + * @return FlagStatus - The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + + if((tmpsr & FSMC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn FSMC_ClearFlag + * + * @brief Clears the FSMC's pending flags. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_FLAG - specifies the flag to check. + * FSMC_FLAG_RisingEdge - Rising egde detection Flag. + * FSMC_FLAG_Level - Level detection Flag. + * FSMC_FLAG_FallingEdge - Falling egde detection Flag. + * + * @return none + */ +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } +} + +/********************************************************************* + * @fn FSMC_GetITStatus + * + * @brief Checks whether the specified FSMC interrupt has occurred or not. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_IT - specifies the FSMC interrupt source to check. + * FSMC_IT_RisingEdge - Rising edge detection interrupt. + * FSMC_IT_Level - Level edge detection interrupt. + * FSMC_IT_FallingEdge - Falling edge detection interrupt. + * + * @return ITStatus - The new state of FSMC_IT (SET or RESET). + */ +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + if((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn FSMC_ClearITPendingBit + * + * @brief Clears the FSMC's interrupt pending bits. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_IT - specifies the FSMC interrupt source to check. + * FSMC_IT_RisingEdge - Rising edge detection interrupt. + * FSMC_IT_Level - Level edge detection interrupt. + * FSMC_IT_FallingEdge - Falling edge detection interrupt. + * + * @return none + */ +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } +} diff --git a/libraries/sdk/Peripheral/ch32v30x_fsmc.h b/libraries/sdk/Peripheral/ch32v30x_fsmc.h new file mode 100644 index 0000000..33dcc60 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_fsmc.h @@ -0,0 +1,287 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_fsmc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the FSMC +* firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_FSMC_H +#define __CH32V30x_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#include "ch32v30x.h" + + +/* FSMC Init structure definition */ +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /* Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /* Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /* Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /* Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note: It is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /* Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /* Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The value of this parameter depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /* Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + + +typedef struct +{ + uint32_t FSMC_Bank; /* Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /* Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /* Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /* Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_AsynchronousWait; /* Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FSMC_AsynchronousWait */ + + uint32_t FSMC_WaitSignalPolarity; /* Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WrapMode; /* Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t FSMC_WaitSignalActive; /* Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /* Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /* Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /* Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /* Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /* Timing Parameters for write and read access if the ExtendedMode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /* Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + + +typedef struct +{ + uint32_t FSMC_SetupTime; /* Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /* Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /* Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /* Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + + +typedef struct +{ + uint32_t FSMC_Bank; /* Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /* Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /* Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /* Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /* Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /* Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /* FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + + +/* FSMC_NORSRAM_Bank */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) + +/* FSMC_NAND_Bank */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) + +/* FSMC_Data_Address_Bus_Multiplexing */ +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) + +/* FSMC_Memory_Type */ +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) + +/* FSMC_Data_Width */ +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) + +/* FSMC_Burst_Access_Mode */ +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) + +/* FSMC_AsynchronousWait */ +#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) + +/* FSMC_Wait_Signal_Polarity */ +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) + +/* FSMC_Wrap_Mode */ +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) + +/* FSMC_Wait_Timing */ +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) + +/* FSMC_Write_Operation */ +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) + +/* FSMC_Wait_Signal */ +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) + +/* FSMC_Extended_Mode */ +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +/* FSMC_Write_Burst */ +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) + +/* FSMC_Access_Mode */ +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) + +/* FSMC_Wait_feature */ +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) + +/* FSMC_ECC */ +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) + +/* FSMC_ECC_Page_Size */ +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) + +/* FSMC_Interrupt_sources */ +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) + +/* FSMC_Flags */ +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) + + +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/sdk/Peripheral/ch32v30x_gpio.c b/libraries/sdk/Peripheral/ch32v30x_gpio.c new file mode 100644 index 0000000..169646f --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_gpio.c @@ -0,0 +1,566 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_gpio.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the GPIO firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_gpio.h" +#include "ch32v30x_rcc.h" + +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if(GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } + + if(GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CFGHR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CFGHR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return The output port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->INDR); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->OUTDR); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BSHR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * BitVal - specifies the value to be written to the selected bit. + * Bit_SetL - to clear the port pin. + * Bit_SetH - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = GPIO_Pin; + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_EventOutputConfig + * + * @brief Selects the GPIO pin used as Event output. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * GPIO_PinSource - specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + + tmpreg = AFIO->ECR; + tmpreg &= ECR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->ECR = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EventOutputCmd + * + * @brief Enables or disables the Event Output. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + if(NewState) + { + AFIO->ECR |= (1 << 7); + } + else + { + AFIO->ECR &= ~(1 << 7); + } +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping + * GPIO_Remap_I2C1 - I2C1 Alternate Function mapping + * GPIO_Remap_USART1 - USART1 Alternate Function mapping + * GPIO_Remap_USART2 - USART2 Alternate Function mapping + * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping + * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping + * GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping + * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping + * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping + * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap_PD01 - PD01 Alternate Function mapping + * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping + * GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping + * GPIO_Remap_ETH - Ethernet remapping + * GPIO_Remap_CAN2 - CAN2 remapping + * GPIO_Remap_MII_RMII_SEL - MII or RMII selection + * GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST + * GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled + * GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP) + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected + * to TIM2 Internal Trigger 1 for calibration + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) + * GPIO_Remap_TIM8 - TIM8 Alternate Function mapping + * GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping + * GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping + * GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping + * GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping + * GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping + * GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping + * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping + * GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping + * GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping + * GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping + * GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping + * GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping + * GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping + * GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping + * GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping + * GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->PCFR2; + } + else + { + tmpreg = AFIO->PCFR1; + } + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + /* Clear bit */ + if((GPIO_Remap & 0x80000000) == 0x80000000) + { /* PCFR2 */ + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */ + { + tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10); + tmpreg &= ~tmp1; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + } + else /* [31:0] 1bit */ + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + } + } + else + { /* PCFR1 */ + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */ + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else /* [31:0] 1bit */ + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); + } + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->PCFR2 = tmpreg; + } + else + { + AFIO->PCFR1 = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/********************************************************************* + * @fn GPIO_ETH_MediaInterfaceConfig + * + * @brief Selects the Ethernet media interface. + * + * @param GPIO_ETH_MediaInterface - specifies the Media Interface mode. + * GPIO_ETH_MediaInterface_MII - MII mode + * GPIO_ETH_MediaInterface_RMII - RMII mode + * + * @return none + */ +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) +{ + if(GPIO_ETH_MediaInterface) + { + AFIO->PCFR1 |= (1 << 23); + } + else + { + AFIO->PCFR1 &= ~(1 << 23); + } +} diff --git a/libraries/sdk/Peripheral/ch32v30x_gpio.h b/libraries/sdk/Peripheral/ch32v30x_gpio.h new file mode 100644 index 0000000..1dd7ad1 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_gpio.h @@ -0,0 +1,197 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_gpio.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* GPIO firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_GPIO_H +#define __CH32V30x_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; + +/* Configuration Mode enumeration */ +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +/* PCFR1 */ +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */ +#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */ +#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */ +#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected + to TIM2 Internal Trigger 1 for calibration + (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ + +/* PCFR2 */ +#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */ +#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */ +#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */ +#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */ +#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */ + + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +/* Ethernet_Media_Interface */ +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) + + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_i2c.c b/libraries/sdk/Peripheral/ch32v30x_i2c.c new file mode 100644 index 0000000..17da0e4 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_i2c.c @@ -0,0 +1,972 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_i2c.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the I2C firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_i2c.h" +#include "ch32v30x_rcc.h" + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } + else + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + I2Cx->RTR = freqrange + 1; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * I2C_Register_RTR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_SMBusAlertConfig + * + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_SMBusAlert - specifies SMBAlert pin level. + * I2C_SMBusAlert_Low - SMBAlert pin driven low. + * I2C_SMBusAlert_High - SMBAlert pin driven high. + * + * @return none + */ +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert) +{ + if(I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + I2Cx->CTLR1 |= I2C_SMBusAlert_Low; + } + else + { + I2Cx->CTLR1 &= I2C_SMBusAlert_High; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EV2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EV2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EV2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EV3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EV3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EV3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EV3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EV4. + * I2C_EVENT_MASTER_MODE_SELECT - EV5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EV6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EV6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EV7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EV8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EV8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EV9. + * + * @return none + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). + * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return none + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_SMBALERT - SMBus Alert flag. + * I2C_IT_TIMEOUT - Timeout or Tlow error flag. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_SMBALERT - SMBus Alert interrupt. + * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} diff --git a/libraries/sdk/Peripheral/ch32v30x_i2c.h b/libraries/sdk/Peripheral/ch32v30x_i2c.h new file mode 100644 index 0000000..d3723c5 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_i2c.h @@ -0,0 +1,211 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_i2c.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* I2C firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_I2C_H +#define __CH32V30x_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); + + +/**************************************************************************************** +* I2C State Monitoring Functions +****************************************************************************************/ + +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_iwdg.c b/libraries/sdk/Peripheral/ch32v30x_iwdg.c new file mode 100644 index 0000000..7c66893 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_iwdg.c @@ -0,0 +1,120 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_iwdg.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the IWDG firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_iwdg.h" + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} diff --git a/libraries/sdk/Peripheral/ch32v30x_iwdg.h b/libraries/sdk/Peripheral/ch32v30x_iwdg.h new file mode 100644 index 0000000..0276d85 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_iwdg.h @@ -0,0 +1,56 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_iwdg.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* IWDG firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_IWDG_H +#define __CH32V30x_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_opa.c b/libraries/sdk/Peripheral/ch32v30x_opa.c new file mode 100644 index 0000000..f157794 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_opa.c @@ -0,0 +1,84 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_opa.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the OPA firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +***************************************************************************************/ +#include "ch32v30x_opa.h" + +#define OPA_MASK ((uint32_t)0x000F) +#define OPA_Total_NUM 4 + +/********************************************************************* + * @fn OPA_DeInit + * + * @brief Deinitializes the OPA peripheral registers to their default + * reset values. + * + * @return none + */ +void OPA_DeInit(void) +{ + OPA->CR = 0; +} + +/********************************************************************* + * @fn OPA_Init + * + * @brief Initializes the OPA peripheral according to the specified + * parameters in the OPA_InitStruct. + * + * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) +{ + uint32_t tmp = 0; + tmp = OPA->CR; + tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); + tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); + OPA->CR = tmp; +} + +/********************************************************************* + * @fn OPA_StructInit + * + * @brief Fills each OPA_StructInit member with its reset value. + * + * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) +{ + OPA_InitStruct->Mode = OUT_IO; + OPA_InitStruct->PSEL = CHP0; + OPA_InitStruct->NSEL = CHN0; + OPA_InitStruct->OPA_NUM = OPA1; +} + +/********************************************************************* + * @fn OPA_Cmd + * + * @brief Enables or disables the specified OPA peripheral. + * + * @param OPA_NUM - Select OPA + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM)); + } + else + { + OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM)); + } +} diff --git a/libraries/sdk/Peripheral/ch32v30x_opa.h b/libraries/sdk/Peripheral/ch32v30x_opa.h new file mode 100644 index 0000000..4fd5f01 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_opa.h @@ -0,0 +1,75 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_opa.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* OPA firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_OPA_H +#define __CH32V30x_OPA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +#define OPA_PSEL_OFFSET 3 +#define OPA_NSEL_OFFSET 2 +#define OPA_MODE_OFFSET 1 + + +/* OPA member enumeration */ +typedef enum +{ + OPA1=0, + OPA2, + OPA3, + OPA4 +}OPA_Num_TypeDef; + +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0=0, + CHP1 +}OPA_PSEL_TypeDef; + +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0=0, + CHN1 +}OPA_NSEL_TypeDef; + +/* OPA Mode enumeration */ +typedef enum +{ + OUT_IO_ADC=0, + OUT_IO +}OPA_Mode_TypeDef; + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ +}OPA_InitTypeDef; + + +void OPA_DeInit(void); +void OPA_Init(OPA_InitTypeDef* OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct); +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/libraries/sdk/Peripheral/ch32v30x_pwr.c b/libraries/sdk/Peripheral/ch32v30x_pwr.c new file mode 100644 index 0000000..a36907d --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_pwr.c @@ -0,0 +1,321 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_pwr.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the PWR firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +********************************************************************************/ +#include "ch32v30x_pwr.h" +#include "ch32v30x_rcc.h" + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_BackupAccessCmd + * + * @brief Enables or disables access to the RTC and backup registers. + * + * @param NewState - new state of the access to the RTC and backup registers, + * This parameter can be: ENABLE or DISABLE. + * + * @return none + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 8); + } + else + { + PWR->CTLR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_PVDCmd + * + * @brief Enables or disables the Power Voltage Detector(PVD). + * + * @param NewState - new state of the PVD(ENABLE or DISABLE). + * + * @return none + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 4); + } + else + { + PWR->CTLR &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_2V2 - PVD detection level set to 2.2V + * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V + * PWR_PVDLevel_2V4 - PVD detection level set to 2.4V + * PWR_PVDLevel_2V5 - PVD detection level set to 2.5V + * PWR_PVDLevel_2V6 - PVD detection level set to 2.6V + * PWR_PVDLevel_2V7 - PVD detection level set to 2.7V + * PWR_PVDLevel_2V8 - PVD detection level set to 2.8V + * PWR_PVDLevel_2V9 - PVD detection level set to 2.9V + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_WakeUpPinCmd + * + * @brief Enables or disables the WakeUp Pin functionality. + * + * @param NewState - new state of the WakeUp Pin functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CSR |= (1 << 8); + } + else + { + PWR->CSR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_EnterSTOPMode + * + * @brief Enters STOP mode. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_ON - STOP mode with regulator ON + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @return none + */ +void PWR_EnterSTANDBYMode(void) +{ + PWR->CTLR |= PWR_CTLR_CWUF; + PWR->CTLR |= PWR_CTLR_PDDS; + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * PWR_FLAG_PVDO - PVD Output + * + * @return none + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn PWR_ClearFlag + * + * @brief Clears the PWR's pending flags. + * + * @param PWR_FLAG - specifies the flag to clear. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * + * @return none + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + PWR->CTLR |= PWR_FLAG << 2; +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM + * + * @brief Enters STANDBY mode with RAM data retention function on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby w power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + //2K+30K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + //2K+30K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} diff --git a/libraries/sdk/Peripheral/ch32v30x_pwr.h b/libraries/sdk/Peripheral/ch32v30x_pwr.h new file mode 100644 index 0000000..3fc9329 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_pwr.h @@ -0,0 +1,64 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_pwr.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the PWR +* firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_PWR_H +#define __CH32V30x_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* PVD_detection_level */ +#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) +#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) +#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) +#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) + +/* Regulator_state_is_STOP_mode */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); +void PWR_EnterSTANDBYMode_RAM(void); +void PWR_EnterSTANDBYMode_RAM_LV(void); +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/libraries/sdk/Peripheral/ch32v30x_rcc.c b/libraries/sdk/Peripheral/ch32v30x_rcc.c new file mode 100644 index 0000000..63ce4e3 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_rcc.c @@ -0,0 +1,1424 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rcc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the RCC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_rcc.h" + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) /* 103 */ +#define CFGR0_PLL_Mask_1 ((uint32_t)0xFFC2FFFF) /* 107 */ + +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* CFGR2 register bit mask */ +#define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) +#define CFGR2_PREDIV1 ((uint32_t)0x0000000F) +#define CFGR2_PREDIV2 ((uint32_t)0x000000F0) +#define CFGR2_PLL2MUL ((uint32_t)0x00000F00) +#define CFGR2_PLL3MUL ((uint32_t)0x0000F000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + +#ifdef CH32V30x_D8C + RCC->CFGR0 &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR0 &= (uint32_t)0xF0FF0000; +#endif + + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + +#ifdef CH32V30x_D8C + RCC->CTLR &= (uint32_t)0xEBFFFFFF; + RCC->INTR = 0x00FF0000; + RCC->CFGR2 = 0x00000000; +#else + RCC->INTR = 0x009F0000; +#endif +} + +/********************************************************************* + * @fn RCC_HSEConfig + * + * @brief Configures the External High Speed oscillator (HSE). + * + * @param RCC_HSE - + * RCC_HSE_OFF - HSE oscillator OFF. + * RCC_HSE_ON - HSE oscillator ON. + * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. + * + * @return none + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + RCC->CTLR &= CTLR_HSEON_Reset; + RCC->CTLR &= CTLR_HSEBYP_Reset; + + switch(RCC_HSE) + { + case RCC_HSE_ON: + RCC->CTLR |= CTLR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_WaitForHSEStartUp + * + * @brief Waits for HSE start-up. + * + * @return SUCCESS - HSE oscillator is stable and ready to use. + * ERROR - HSE oscillator not yet ready. + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + return (status); +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 0); + } + else + { + RCC->CTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_PLLConfig + * + * @brief Configures the PLL clock source and multiplication factor. + * + * @param RCC_PLLSource - specifies the PLL entry clock source. + * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 + * selected as PLL clock entry. + * RCC_PLLSource_PREDIV1 - PREDIV1 clock selected as PLL clock + * entry. + * RCC_PLLMul - specifies the PLL multiplication factor. + * This parameter can be RCC_PLLMul_x where x:[2,16]. + * For CH32V307 - + * RCC_PLLMul_18_EXTEN + * RCC_PLLMul_3_EXTEN + * RCC_PLLMul_4_EXTEN + * RCC_PLLMul_5_EXTEN + * RCC_PLLMul_6_EXTEN + * RCC_PLLMul_7_EXTEN + * RCC_PLLMul_8_EXTEN + * RCC_PLLMul_9_EXTEN + * RCC_PLLMul_10_EXTEN + * RCC_PLLMul_11_EXTEN + * RCC_PLLMul_12_EXTEN + * RCC_PLLMul_13_EXTEN + * RCC_PLLMul_14_EXTEN + * RCC_PLLMul_6_5_EXTEN + * RCC_PLLMul_15_EXTEN + * RCC_PLLMul_16_EXTEN + * For other CH32V30x - + * RCC_PLLMul_2 + * RCC_PLLMul_3 + * RCC_PLLMul_4 + * RCC_PLLMul_5 + * RCC_PLLMul_6 + * RCC_PLLMul_7 + * RCC_PLLMul_8 + * RCC_PLLMul_9 + * RCC_PLLMul_10 + * RCC_PLLMul_11 + * RCC_PLLMul_12 + * RCC_PLLMul_13 + * RCC_PLLMul_14 + * RCC_PLLMul_15 + * RCC_PLLMul_16 + * RCC_PLLMul_18 + * + * @return none + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + + if(((*(uint32_t *)0x1FFFF70C) & (1 << 14)) != (1 << 14)) + { /* for other CH32V30x */ + tmpreg &= CFGR0_PLL_Mask; + } + else + { /* for CH32V307 */ + tmpreg &= CFGR0_PLL_Mask_1; + } + + tmpreg |= RCC_PLLSource | RCC_PLLMul; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLLCmd + * + * @brief Enables or disables the PLL. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 24); + } + else + { + RCC->CTLR &= ~(1 << 24); + } +} + +/********************************************************************* + * @fn RCC_SYSCLKConfig + * + * @brief Configures the system clock (SYSCLK). + * + * @param RCC_SYSCLKSource - specifies the clock source used as system clock. + * RCC_SYSCLKSource_HSI - HSI selected as system clock. + * RCC_SYSCLKSource_HSE - HSE selected as system clock. + * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. + * + * @return none + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_SW_Mask; + tmpreg |= RCC_SYSCLKSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetSYSCLKSource + * + * @brief Returns the clock source used as system clock. + * + * @return 0x00 - HSI used as system clock. + * 0x04 - HSE used as system clock. + * 0x08 - PLL used as system clock. + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the AHB clock (HCLK). + * + * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. + * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. + * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. + * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. + * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. + * RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK1Config + * + * @brief Configures the Low Speed APB clock (PCLK1). + * + * @param RCC_HCLK - defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB1 clock = HCLK. + * RCC_HCLK_Div2 - APB1 clock = HCLK/2. + * RCC_HCLK_Div4 - APB1 clock = HCLK/4. + * RCC_HCLK_Div8 - APB1 clock = HCLK/8. + * RCC_HCLK_Div16 - APB1 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE1_Reset_Mask; + tmpreg |= RCC_HCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK2Config + * + * @brief Configures the High Speed APB clock (PCLK2). + * + * @param RCC_HCLK - defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB1 clock = HCLK. + * RCC_HCLK_Div2 - APB1 clock = HCLK/2. + * RCC_HCLK_Div4 - APB1 clock = HCLK/4. + * RCC_HCLK_Div8 - APB1 clock = HCLK/8. + * RCC_HCLK_Div16 - APB1 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE2_Reset_Mask; + tmpreg |= RCC_HCLK << 3; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_ITConfig + * + * @brief Enables or disables the specified RCC interrupts. + * + * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/********************************************************************* + * @fn RCC_ADCCLKConfig + * + * @brief Configures the ADC clock (ADCCLK). + * + * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. + * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. + * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. + * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. + * + * @return none + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_ADCPRE_Reset_Mask; + tmpreg |= RCC_PCLK2; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_LSEConfig + * + * @brief Configures the External Low Speed oscillator (LSE). + * + * @param RCC_LSE - specifies the new state of the LSE. + * RCC_LSE_OFF - LSE oscillator OFF. + * RCC_LSE_ON - LSE oscillator ON. + * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. + * + * @return none + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; + + switch(RCC_LSE) + { + case RCC_LSE_ON: + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_LSICmd + * + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_LSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->RSTSCKR |= (1 << 0); + } + else + { + RCC->RSTSCKR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_RTCCLKConfig + * + * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * + * @param RCC_RTCCLKSource - specifies the RTC clock source. + * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. + * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. + * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. + * + * @return none + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + RCC->BDCTLR |= RCC_RTCCLKSource; +} + +/********************************************************************* + * @fn RCC_RTCCLKCmd + * + * @brief This function must be used only after the RTC clock was selected + * using the RCC_RTCCLKConfig function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1 << 15); + } + else + { + RCC->BDCTLR &= ~(1 << 15); + } +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0, Pll_6_5 = 0; + + tmp = RCC->CFGR0 & CFGR0_SWS_Mask; + + switch(tmp) + { + case 0x00: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + + case 0x04: + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: + pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; + pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; + + pllmull = (pllmull >> 18) + 2; + + if(((*(uint32_t *)0x1FFFF70C) & (1 << 14)) != (1 << 14)) + { /* for other CH32V30x */ + if(pllmull == 17) + pllmull = 18; + } + else + { /* for CH32V307 */ + if(pllmull == 2) + pllmull = 18; + if(pllmull == 15) + { + pllmull = 13; /* *6.5 */ + Pll_6_5 = 1; + } + if(pllmull == 16) + pllmull = 15; + if(pllmull == 17) + pllmull = 16; + } + + if(pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) + { + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE)*pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + } + else + { + if((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) + { + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; + } + } + + if(Pll_6_5 == 1) + RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency / 2); + + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/********************************************************************* + * @fn RCC_AHBPeriphClockCmd + * + * @brief Enables or disables the AHB peripheral clock. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. + * RCC_AHBPeriph_DMA1. + * RCC_AHBPeriph_DMA2. + * RCC_AHBPeriph_SRAM. + * RCC_AHBPeriph_CRC. + * RCC_AHBPeriph_FSMC + * RCC_AHBPeriph_RNG + * RCC_AHBPeriph_SDIO + * RCC_AHBPeriph_USBHS + * RCC_AHBPeriph_OTG_FS + * RCC_AHBPeriph_DVP + * RCC_AHBPeriph_ETH_MAC + * RCC_AHBPeriph_ETH_MAC_Tx + * RCC_AHBPeriph_ETH_MAC_Rx + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->AHBPCENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCENR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphClockCmd + * + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_ADC2 + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_TIM8 + * RCC_APB2Periph_USART1. + * RCC_APB2Periph_TIM9 + * RCC_APB2Periph_TIM10 + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PCENR |= RCC_APB2Periph; + } + else + { + RCC->APB2PCENR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_TIM5 + * RCC_APB1Periph_TIM6 + * RCC_APB1Periph_TIM7 + * RCC_APB1Periph_UART6 + * RCC_APB1Periph_UART7 + * RCC_APB1Periph_UART8 + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_SPI3. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_UART4 + * RCC_APB1Periph_UART5 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * RCC_APB1Periph_DAC. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PCENR |= RCC_APB1Periph; + } + else + { + RCC->APB1PCENR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphResetCmd + * + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_ADC2 + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_TIM8 + * RCC_APB2Periph_USART1. + * RCC_APB2Periph_TIM9 + * RCC_APB2Periph_TIM10 + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PRSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2PRSTR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphResetCmd + * + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_TIM5 + * RCC_APB1Periph_TIM6 + * RCC_APB1Periph_TIM7 + * RCC_APB1Periph_UART6 + * RCC_APB1Periph_UART7 + * RCC_APB1Periph_UART8 + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_SPI3. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_UART4 + * RCC_APB1Periph_UART5 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * RCC_APB1Periph_DAC. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PRSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1PRSTR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_BackupResetCmd + * + * @brief Forces or releases the Backup domain reset. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1 << 16); + } + else + { + RCC->BDCTLR &= ~(1 << 16); + } +} + +/********************************************************************* + * @fn RCC_ClockSecuritySystemCmd + * + * @brief Enables or disables the Clock Security System. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 19); + } + else + { + RCC->CTLR &= ~(1 << 19); + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * RCC_MCO_HSE - HSE oscillator clock selected. + * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. + * RCC_MCO_PLL2CLK - PLL2 clock selected + * RCC_MCO_PLL3CLK_Div2 - PLL3 clock divided by 2 selected + * RCC_MCO_XT1 - External 3-25 MHz oscillator clock selected + * RCC_MCO_PLL3CLK - PLL3 clock selected + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_HSERDY - HSE oscillator clock ready. + * RCC_FLAG_PLLRDY - PLL clock ready. + * RCC_FLAG_PLL2RDY - PLL2 clock ready. + * RCC_FLAG_PLL3RDY - PLL3 clock ready. + * RCC_FLAG_LSERDY - LSE oscillator clock ready. + * RCC_FLAG_LSIRDY - LSI oscillator clock ready. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if(tmp == 1) + { + statusreg = RCC->CTLR; + } + else if(tmp == 2) + { + statusreg = RCC->BDCTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + +/********************************************************************* + * @fn RCC_GetITStatus + * + * @brief Checks whether the specified RCC interrupt has occurred or not. + * + * @param RCC_IT - specifies the RCC interrupt source to check. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_PLL2RDY - PLL2 ready interrupt. + * RCC_IT_PLL3RDY - PLL3 ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return ITStatus - SET or RESET. + */ + +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + if((RCC->INTR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearITPendingBit + * + * @brief Clears the RCC's interrupt pending bits. + * + * @param RCC_IT - specifies the interrupt pending bit to clear. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_PLL2RDY - PLL2 ready interrupt. + * RCC_IT_PLL3RDY - PLL3 ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return none + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT; +} + +/********************************************************************* + * @fn RCC_PREDIV1Config + * + * @brief Configures the PREDIV1 division factor. + * + * @param RCC_PREDIV1_Source - specifies the PREDIV1 clock source. + * RCC_PREDIV1_Source_HSE - HSE selected as PREDIV1 clock + * RCC_PREDIV1_Source_PLL2 - PLL2 selected as PREDIV1 clock + * RCC_PREDIV1_Div - specifies the PREDIV1 clock division factor. + * This parameter can be RCC_PREDIV1_Divx where x[1,16] + * + * @return none + */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); + tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PREDIV2Config + * + * @brief Configures the PREDIV2 division factor. + * + * @param RCC_PREDIV2_Div - specifies the PREDIV2 clock division factor. + * This parameter can be RCC_PREDIV2_Divx where x:[1,16] + * + * @return none + */ +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~CFGR2_PREDIV2; + tmpreg |= RCC_PREDIV2_Div; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLL2Config + * + * @brief Configures the PLL2 multiplication factor. + * + * @param RCC_PLL2Mul - specifies the PLL2 multiplication factor. + * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} + * + * @return none + */ +void RCC_PLL2Config(uint32_t RCC_PLL2Mul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~CFGR2_PLL2MUL; + tmpreg |= RCC_PLL2Mul; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLL2Cmd + * + * @brief Enables or disables the PLL2. + * + * @param NewState - new state of the PLL2. This parameter can be + * ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLL2Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 26); + } + else + { + RCC->CTLR &= ~(1 << 26); + } +} + +/********************************************************************* + * @fn RCC_PLL3Config + * + * @brief Configures the PLL3 multiplication factor. + * + * @param RCC_PLL3Mul - specifies the PLL2 multiplication factor. + * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} + * + * @return none + */ +void RCC_PLL3Config(uint32_t RCC_PLL3Mul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~CFGR2_PLL3MUL; + tmpreg |= RCC_PLL3Mul; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLL3Cmd + * + * @brief Enables or disables the PLL3. + * + * @param NewState - new state of the PLL2. This parameter can be + * ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLL3Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 28); + } + else + { + RCC->CTLR &= ~(1 << 28); + } +} + +/********************************************************************* + * @fn RCC_OTGFSCLKConfig + * + * @brief Configures the USB OTG FS clock (OTGFSCLK). + * + * @param RCC_OTGFSCLKSource - specifies the USB OTG FS clock source. + * RCC_OTGFSCLKSource_PLLCLK_Div1 - PLL clock divided by 1 + * selected as USB OTG FS clock source + * RCC_OTGFSCLKSource_PLLCLK_Div2 - PLL clock divided by 2 + * selected as USB OTG FS clock source + * RCC_OTGFSCLKSource_PLLCLK_Div3 - PLL clock divided by 3 + * selected as USB OTG FS clock source + * + * @return none + */ +void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) +{ + RCC->CFGR0 &= ~(3 << 22); + RCC->CFGR0 |= RCC_OTGFSCLKSource << 22; +} + +/********************************************************************* + * @fn RCC_I2S2CLKConfig + * + * @brief Configures the I2S2 clock source(I2S2CLK). + * + * @param RCC_I2S2CLKSource - specifies the I2S2 clock source. + * RCC_I2S2CLKSource_SYSCLK - system clock selected as I2S2 clock entry + * RCC_I2S2CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S2 clock entry + * + * @return none + */ +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) +{ + RCC->CFGR2 &= ~(1 << 17); + RCC->CFGR2 |= RCC_I2S2CLKSource << 17; +} + +/********************************************************************* + * @fn RCC_I2S3CLKConfig + * + * @brief Configures the I2S3 clock source(I2S2CLK). + * + * @param RCC_I2S3CLKSource - specifies the I2S3 clock source. + * RCC_I2S3CLKSource_SYSCLK - system clock selected as I2S3 clock entry + * RCC_I2S3CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S3 clock entry + * + * @return none + */ +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) +{ + RCC->CFGR2 &= ~(1 << 18); + RCC->CFGR2 |= RCC_I2S3CLKSource << 18; +} + +/********************************************************************* + * @fn RCC_AHBPeriphResetCmd + * + * @brief Forces or releases AHB peripheral reset. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to reset. + * RCC_AHBPeriph_OTG_FS + * RCC_AHBPeriph_ETH_MAC + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_ADCCLKADJcmd + * + * @brief Enable ADC clock duty cycle adjustment. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ADCCLKADJcmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->CFGR0 |= (1 << 31); + } + else + { + RCC->CFGR0 &= ~(1 << 31); + } +} + +/********************************************************************* + * @fn RCC_RNGCLKConfig + * + * @brief Configures the RNG clock source. + * + * @param RCC_RNGCLKSource - specifies the RNG clock source. + * RCC_RNGCLKSource_SYSCLK - system clock selected as RNG clock entry + * RCC_RNGCLKSource_PLL3_VCO - PLL3 VCO clock selected as RNG clock entry + * + * @return none + */ +void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource) +{ + RCC->CFGR2 &= ~(1 << 19); + RCC->CFGR2 |= RCC_RNGCLKSource << 19; +} + +/********************************************************************* + * @fn RCC_ETH1GCLKConfig + * + * @brief Configures the ETH1G clock source. + * + * @param RCC_RNGCLKSource - specifies the ETH1G clock source. + * RCC_ETH1GCLKSource_PLL2_VCO - system clock selected as ETH1G clock entry + * RCC_ETH1GCLKSource_PLL3_VCO - PLL3 VCO clock selected as ETH1G clock entry + * RCC_ETH1GCLKSource_PB1_IN - GPIO PB1 input clock selected as ETH1G clock entry + * + * @return none + */ +void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource) +{ + RCC->CFGR2 &= ~(3 << 20); + RCC->CFGR2 |= RCC_ETH1GCLKSource << 20; +} + +/********************************************************************* + * @fn RCC_ETH1G_125Mcmd + * + * @brief Enable ETH1G 125M. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ETH1G_125Mcmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->CFGR2 |= (1 << 22); + } + else + { + RCC->CFGR2 &= ~(1 << 22); + } +} + +/********************************************************************* + * @fn RCC_USBHSConfig + * + * @brief Configures the USBHS clock. + * + * @param RCC_USBHS - defines the USBHS clock divider. + * RCC_USBPLL_Div1 - USBHS clock = USBPLL. + * RCC_USBPLL_Div2 - USBHS clock = USBPLL/2. + * RCC_USBPLL_Div3 - USBHS clock = USBPLL/3. + * RCC_USBPLL_Div4 - USBHS clock = USBPLL/4. + * RCC_USBPLL_Div5 - USBHS clock = USBPLL/5. + * RCC_USBPLL_Div6 - USBHS clock = USBPLL/6. + * RCC_USBPLL_Div7 - USBHS clock = USBPLL/7. + * RCC_USBPLL_Div8 - USBHS clock = USBPLL/8. + * + * @return none + */ +void RCC_USBHSConfig(uint32_t RCC_USBHS) +{ + RCC->CFGR2 &= ~(7 << 24); + RCC->CFGR2 |= RCC_USBHS << 24; +} + +/********************************************************************* + * @fn RCC_USBHSPLLCLKConfig + * + * @brief Configures the USBHSPLL clock source. + * + * @param RCC_HSBHSPLLCLKSource - specifies the USBHSPLL clock source. + * RCC_HSBHSPLLCLKSource_HSE - HSE clock selected as USBHSPLL clock entry + * RCC_HSBHSPLLCLKSource_HSI - HSI clock selected as USBHSPLL clock entry + * + * @return none + */ +void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource) +{ + RCC->CFGR2 &= ~(1 << 27); + RCC->CFGR2 |= RCC_USBHSPLLCLKSource << 27; +} + +/********************************************************************* + * @fn RCC_USBHSPLLCKREFCLKConfig + * + * @brief Configures the USBHSPLL reference clock. + * + * @param RCC_USBHSPLLCKREFCLKSource - Select reference clock. + * RCC_USBHSPLLCKREFCLK_3M - reference clock 3Mhz. + * RCC_USBHSPLLCKREFCLK_4M - reference clock 4Mhz. + * RCC_USBHSPLLCKREFCLK_8M - reference clock 8Mhz. + * RCC_USBHSPLLCKREFCLK_5M - reference clock 5Mhz. + * + * @return none + */ +void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource) +{ + RCC->CFGR2 &= ~(3 << 28); + RCC->CFGR2 |= RCC_USBHSPLLCKREFCLKSource << 28; +} + +/********************************************************************* + * @fn RCC_USBHSPHYPLLALIVEcmd + * + * @brief Enable USBHS PHY control. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->CFGR2 |= (1 << 30); + } + else + { + RCC->CFGR2 &= ~(1 << 30); + } +} + +/********************************************************************* + * @fn RCC_USBCLK48MConfig + * + * @brief Configures the USB clock 48MHz source. + * + * @param RCC_USBCLK48MSource - specifies the USB clock 48MHz source. + * RCC_USBCLK48MCLKSource_PLLCLK - PLLCLK clock selected as USB clock 48MHz clock entry + * RCC_USBCLK48MCLKSource_USBPHY - USBPHY clock selected as USB clock 48MHz clock entry + * + * @return none + */ +void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource) +{ + RCC->CFGR2 &= ~(1 << 31); + RCC->CFGR2 |= RCC_USBCLK48MSource << 31; +} diff --git a/libraries/sdk/Peripheral/ch32v30x_rcc.h b/libraries/sdk/Peripheral/ch32v30x_rcc.h new file mode 100644 index 0000000..1acccde --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_rcc.h @@ -0,0 +1,456 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rcc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the RCC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_RCC_H +#define __CH32V30x_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) + +#ifdef CH32V30x_D8 +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + +#else +#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) + +#endif + +/* PLL_multiplication_factor */ +#ifdef CH32V30x_D8 +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) +#define RCC_PLLMul_18 ((uint32_t)0x003C0000) + +#else +#define RCC_PLLMul_18_EXTEN ((uint32_t)0x00000000) +#define RCC_PLLMul_3_EXTEN ((uint32_t)0x00040000) +#define RCC_PLLMul_4_EXTEN ((uint32_t)0x00080000) +#define RCC_PLLMul_5_EXTEN ((uint32_t)0x000C0000) +#define RCC_PLLMul_6_EXTEN ((uint32_t)0x00100000) +#define RCC_PLLMul_7_EXTEN ((uint32_t)0x00140000) +#define RCC_PLLMul_8_EXTEN ((uint32_t)0x00180000) +#define RCC_PLLMul_9_EXTEN ((uint32_t)0x001C0000) +#define RCC_PLLMul_10_EXTEN ((uint32_t)0x00200000) +#define RCC_PLLMul_11_EXTEN ((uint32_t)0x00240000) +#define RCC_PLLMul_12_EXTEN ((uint32_t)0x00280000) +#define RCC_PLLMul_13_EXTEN ((uint32_t)0x002C0000) +#define RCC_PLLMul_14_EXTEN ((uint32_t)0x00300000) +#define RCC_PLLMul_6_5_EXTEN ((uint32_t)0x00340000) +#define RCC_PLLMul_15_EXTEN ((uint32_t)0x00380000) +#define RCC_PLLMul_16_EXTEN ((uint32_t)0x003C0000) + +#endif + +/* PREDIV1_division_factor */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) +#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) +#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) +#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) +#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) +#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) +#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) +#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) +#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) +#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) +#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) +#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) +#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) +#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) +#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) +#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) + +#endif + +/* PREDIV1_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) +#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) + +#endif + +/* PREDIV2_division_factor */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) +#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) +#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) +#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) +#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) +#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) +#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) +#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) +#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) +#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) +#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) +#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) +#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) +#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) +#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) +#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) + +#endif + +/* PLL2_multiplication_factor */ +#ifdef CH32V30x_D8C +#define RCC_PLL2Mul_2_5 ((uint32_t)0x00000000) +#define RCC_PLL2Mul_12_5 ((uint32_t)0x00000100) +#define RCC_PLL2Mul_4 ((uint32_t)0x00000200) +#define RCC_PLL2Mul_5 ((uint32_t)0x00000300) +#define RCC_PLL2Mul_6 ((uint32_t)0x00000400) +#define RCC_PLL2Mul_7 ((uint32_t)0x00000500) +#define RCC_PLL2Mul_8 ((uint32_t)0x00000600) +#define RCC_PLL2Mul_9 ((uint32_t)0x00000700) +#define RCC_PLL2Mul_10 ((uint32_t)0x00000800) +#define RCC_PLL2Mul_11 ((uint32_t)0x00000900) +#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) +#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) +#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) +#define RCC_PLL2Mul_15 ((uint32_t)0x00000D00) +#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) +#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) + +#endif + +/* PLL3_multiplication_factor */ +#ifdef CH32V30x_D8C +#define RCC_PLL3Mul_2_5 ((uint32_t)0x00000000) +#define RCC_PLL3Mul_12_5 ((uint32_t)0x00001000) +#define RCC_PLL3Mul_4 ((uint32_t)0x00002000) +#define RCC_PLL3Mul_5 ((uint32_t)0x00003000) +#define RCC_PLL3Mul_6 ((uint32_t)0x00004000) +#define RCC_PLL3Mul_7 ((uint32_t)0x00005000) +#define RCC_PLL3Mul_8 ((uint32_t)0x00006000) +#define RCC_PLL3Mul_9 ((uint32_t)0x00007000) +#define RCC_PLL3Mul_10 ((uint32_t)0x00008000) +#define RCC_PLL3Mul_11 ((uint32_t)0x00009000) +#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) +#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) +#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) +#define RCC_PLL3Mul_15 ((uint32_t)0x0000D000) +#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) +#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) + +#endif + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) + +/* APB1_APB2_clock_source */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +#ifdef CH32V30x_D8C +#define RCC_IT_PLL2RDY ((uint8_t)0x20) +#define RCC_IT_PLL3RDY ((uint8_t)0x40) + +#endif + +/* USB_OTG_FS_clock_source */ +#define RCC_OTGFSCLKSource_PLLCLK_Div1 ((uint8_t)0x00) +#define RCC_OTGFSCLKSource_PLLCLK_Div2 ((uint8_t)0x01) +#define RCC_OTGFSCLKSource_PLLCLK_Div3 ((uint8_t)0x02) + +/* I2S2_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) +#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) + +#endif + +/* I2S3_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) +#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) + +#endif + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) +#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200) +#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) +#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800) +#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) +#define RCC_AHBPeriph_DVP ((uint32_t)0x00002000) +#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) +#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) +#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040) +#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080) +#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +#ifdef CH32V30x_D8C +#define RCC_MCO_PLL2CLK ((uint8_t)0x08) +#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) +#define RCC_MCO_XT1 ((uint8_t)0x0A) +#define RCC_MCO_PLL3CLK ((uint8_t)0x0B) + +#endif + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#ifdef CH32V30x_D8C +#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) +#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) + +#endif + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +/* RNG_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_RNGCLKSource_SYSCLK ((uint32_t)0x00) +#define RCC_RNGCLKSource_PLL3_VCO ((uint32_t)0x01) + +#endif + +/* ETH1G_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_ETH1GCLKSource_PLL2_VCO ((uint32_t)0x00) +#define RCC_ETH1GCLKSource_PLL3_VCO ((uint32_t)0x01) +#define RCC_ETH1GCLKSource_PB1_IN ((uint32_t)0x02) + +#endif + +/* USBFS_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_USBPLL_Div1 ((uint32_t)0x00) +#define RCC_USBPLL_Div2 ((uint32_t)0x01) +#define RCC_USBPLL_Div3 ((uint32_t)0x02) +#define RCC_USBPLL_Div4 ((uint32_t)0x03) +#define RCC_USBPLL_Div5 ((uint32_t)0x04) +#define RCC_USBPLL_Div6 ((uint32_t)0x05) +#define RCC_USBPLL_Div7 ((uint32_t)0x06) +#define RCC_USBPLL_Div8 ((uint32_t)0x07) + +#endif + +/* USBHSPLL_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_HSBHSPLLCLKSource_HSE ((uint32_t)0x00) +#define RCC_HSBHSPLLCLKSource_HSI ((uint32_t)0x01) + +#endif + +/* USBHSPLLCKREF_clock_select */ +#ifdef CH32V30x_D8C +#define RCC_USBHSPLLCKREFCLK_3M ((uint32_t)0x00) +#define RCC_USBHSPLLCKREFCLK_4M ((uint32_t)0x01) +#define RCC_USBHSPLLCKREFCLK_8M ((uint32_t)0x02) +#define RCC_USBHSPLLCKREFCLK_5M ((uint32_t)0x03) + +#endif + +/* OTGUSBCLK48M_clock_source */ +#define RCC_USBCLK48MCLKSource_PLLCLK ((uint32_t)0x00) +#define RCC_USBCLK48MCLKSource_USBPHY ((uint32_t)0x01) + + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); +void RCC_ADCCLKADJcmd(FunctionalState NewState); +void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); +void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource); + +#ifdef CH32V30x_D8C +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); +void RCC_PLL2Config(uint32_t RCC_PLL2Mul); +void RCC_PLL2Cmd(FunctionalState NewState); +void RCC_PLL3Config(uint32_t RCC_PLL3Mul); +void RCC_PLL3Cmd(FunctionalState NewState); +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource); +void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource); +void RCC_ETH1G_125Mcmd(FunctionalState NewState); +void RCC_USBHSConfig(uint32_t RCC_USBHS); +void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource); +void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource); +void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_rng.c b/libraries/sdk/Peripheral/ch32v30x_rng.c new file mode 100644 index 0000000..bd68c07 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_rng.c @@ -0,0 +1,152 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rng.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the RNG firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +********************************************************************************/ +#include "ch32v30x_rng.h" +#include "ch32v30x_rcc.h" + +/********************************************************************* + * @fn RNG_Cmd + * + * @brief Enables or disables the RNG peripheral. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RNG_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RNG->CR |= RNG_CR_RNGEN; + } + else + { + RNG->CR &= ~RNG_CR_RNGEN; + } +} + +/********************************************************************* + * @fn RNG_GetRandomNumber + * + * @brief Returns a 32-bit random number. + * + * @return 32-bit random number. + */ +uint32_t RNG_GetRandomNumber(void) +{ + return RNG->DR; +} + +/********************************************************************* + * @fn RNG_ITConfig + * + * @brief Enables or disables the RNG interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return 32-bit random number. + */ +void RNG_ITConfig(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RNG->CR |= RNG_CR_IE; + } + else + { + RNG->CR &= ~RNG_CR_IE; + } +} + +/********************************************************************* + * @fn RNG_GetFlagStatus + * + * @brief Checks whether the specified RNG flag is set or not. + * + * @param RNG_FLAG - specifies the RNG flag to check. + * RNG_FLAG_DRDY - Data Ready flag. + * RNG_FLAG_CECS - Clock Error Current flag. + * RNG_FLAG_SECS - Seed Error Current flag. + * + * @return 32-bit random number. + */ +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((RNG->SR & RNG_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RNG_ClearFlag + * + * @brief Clears the RNG flags. + * + * @param RNG_FLAG - specifies the flag to clear. + * RNG_FLAG_CECS - Clock Error Current flag. + * RNG_FLAG_SECS - Seed Error Current flag. + * + * @return 32-bit random number. + */ +void RNG_ClearFlag(uint8_t RNG_FLAG) +{ + RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); +} + +/********************************************************************* + * @fn RNG_GetFlagStatus + * + * @brief Checks whether the specified RNG interrupt has occurred or not. + * + * @param RNG_IT - specifies the RNG interrupt source to check. + * RNG_IT_CEI - Clock Error Interrupt. + * RNG_IT_SEI - Seed Error Interrupt. + * + * @return bitstatusSET or RESET. + */ +ITStatus RNG_GetITStatus(uint8_t RNG_IT) +{ + ITStatus bitstatus = RESET; + + if((RNG->SR & RNG_IT) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RNG_ClearITPendingBit + * + * @brief Clears the RNG interrupt pending bit(s). + * + * @param RNG_IT - specifies the RNG interrupt pending bit(s) to clear. + * RNG_IT_CEI - Clock Error Interrupt. + * RNG_IT_SEI - Seed Error Interrupt. + * + * @return None + */ +void RNG_ClearITPendingBit(uint8_t RNG_IT) +{ + RNG->SR = (uint8_t)~RNG_IT; +} diff --git a/libraries/sdk/Peripheral/ch32v30x_rng.h b/libraries/sdk/Peripheral/ch32v30x_rng.h new file mode 100644 index 0000000..99f7cac --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_rng.h @@ -0,0 +1,41 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rng.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* RNG firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_RNG_H +#define __CH32V30x_RNG_H + +#ifdef __cplusplus + extern "C" { +#endif +#include "ch32v30x.h" + + /* RNG_flags_definition*/ +#define RNG_FLAG_DRDY ((uint8_t)0x0001) /* Data ready */ +#define RNG_FLAG_CECS ((uint8_t)0x0002) /* Clock error current status */ +#define RNG_FLAG_SECS ((uint8_t)0x0004) /* Seed error current status */ + +/* RNG_interrupts_definition */ +#define RNG_IT_CEI ((uint8_t)0x20) /* Clock error interrupt */ +#define RNG_IT_SEI ((uint8_t)0x40) /* Seed error interrupt */ + + +void RNG_Cmd(FunctionalState NewState); +uint32_t RNG_GetRandomNumber(void); +void RNG_ITConfig(FunctionalState NewState); +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); +void RNG_ClearFlag(uint8_t RNG_FLAG); +ITStatus RNG_GetITStatus(uint8_t RNG_IT); +void RNG_ClearITPendingBit(uint8_t RNG_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/sdk/Peripheral/ch32v30x_rtc.c b/libraries/sdk/Peripheral/ch32v30x_rtc.c new file mode 100644 index 0000000..09eee43 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_rtc.c @@ -0,0 +1,273 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rtc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the RTC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +********************************************************************************/ +#include "ch32v30x_rtc.h" + +/* RTC_Private_Defines */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ + +/********************************************************************* + * @fn RTC_ITConfig + * + * @brief Enables or disables the specified RTC interrupts. + * + * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. + * RTC_IT_OW - Overflow interrupt + * RTC_IT_ALR - Alarm interrupt + * RTC_IT_SEC - Second interrupt + * + * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RTC->CTLRH |= RTC_IT; + } + else + { + RTC->CTLRH &= (uint16_t)~RTC_IT; + } +} + +/********************************************************************* + * @fn RTC_EnterConfigMode + * + * @brief Enters the RTC configuration mode. + * + * @return none + */ +void RTC_EnterConfigMode(void) +{ + RTC->CTLRL |= RTC_CTLRL_CNF; +} + +/********************************************************************* + * @fn RTC_ExitConfigMode + * + * @brief Exits from the RTC configuration mode. + * + * @return none + */ +void RTC_ExitConfigMode(void) +{ + RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); +} + +/********************************************************************* + * @fn RTC_GetCounter + * + * @brief Gets the RTC counter value + * + * @return RTC counter value + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t high1 = 0, high2 = 0, low = 0; + + high1 = RTC->CNTH; + low = RTC->CNTL; + high2 = RTC->CNTH; + + if(high1 != high2) + { + return (((uint32_t)high2 << 16) | RTC->CNTL); + } + else + { + return (((uint32_t)high1 << 16) | low); + } +} + +/********************************************************************* + * @fn RTC_SetCounter + * + * @brief Sets the RTC counter value. + * + * @param CounterValue - RTC counter new value. + * + * @return RTC counter value + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + RTC->CNTH = CounterValue >> 16; + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetPrescaler + * + * @brief Sets the RTC prescaler value + * + * @param PrescalerValue - RTC prescaler new value + * + * @return none + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + RTC_EnterConfigMode(); + RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetAlarm + * + * @brief Sets the RTC alarm value + * + * @param AlarmValue - RTC alarm new value + * + * @return none + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + RTC->ALRMH = AlarmValue >> 16; + RTC->ALRML = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_GetDivider + * + * @brief Gets the RTC divider value + * + * @return RTC Divider value + */ +uint32_t RTC_GetDivider(void) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; + tmp |= RTC->DIVL; + return tmp; +} + +/********************************************************************* + * @fn RTC_WaitForLastTask + * + * @brief Waits until last write operation on RTC registers has finished + * + * @return none + */ +void RTC_WaitForLastTask(void) +{ + while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_WaitForSynchro + * + * @brief Waits until the RTC registers are synchronized with RTC APB clock + * + * @return none + */ +void RTC_WaitForSynchro(void) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; + while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_GetFlagStatus + * + * @brief Checks whether the specified RTC flag is set or not + * + * @param RTC_FLAG- specifies the flag to check + * RTC_FLAG_RTOFF - RTC Operation OFF flag + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return none + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearFlag + * + * @brief Clears the RTC's pending flags + * + * @param RTC_FLAG - specifies the flag to clear + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return none + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG; +} + +/********************************************************************* + * @fn RTC_GetITStatus + * + * @brief Checks whether the specified RTC interrupt has occurred or not + * + * @param RTC_IT - specifies the RTC interrupts sources to check + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return The new state of the RTC_IT (SET or RESET) + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + + bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); + if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearITPendingBit + * + * @brief Clears the RTC's interrupt pending bits + * + * @param RTC_IT - specifies the interrupt pending bit to clear + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return none + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + RTC->CTLRL &= (uint16_t)~RTC_IT; +} diff --git a/libraries/sdk/Peripheral/ch32v30x_rtc.h b/libraries/sdk/Peripheral/ch32v30x_rtc.h new file mode 100644 index 0000000..60e90ee --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_rtc.h @@ -0,0 +1,54 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rtc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the RTC +* firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_RTC_H +#define __CH32V30x_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* RTC_interrupts_define */ +#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ + +/* RTC_interrupts_flags */ +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ + + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/libraries/sdk/Peripheral/ch32v30x_sdio.c b/libraries/sdk/Peripheral/ch32v30x_sdio.c new file mode 100644 index 0000000..7241dd1 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_sdio.c @@ -0,0 +1,670 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_SDIO.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the SDIO firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_sdio.h" +#include "ch32v30x_rcc.h" + +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/********************************************************************* + * @fn SDIO_DeInit + * + * @brief Deinitializes the SDIO peripheral registers to their default + * reset values. + * + * @return RTC counter value + */ +void SDIO_DeInit(void) +{ + SDIO->POWER = 0x00000000; + SDIO->CLKCR = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DLEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICR = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/********************************************************************* + * @fn SDIO_Init + * + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * + * @param SDIO_InitStruct - pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * + * @return None + */ +void SDIO_Init(SDIO_InitTypeDef *SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = SDIO->CLKCR; + tmpreg &= CLKCR_CLEAR_MASK; + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + SDIO->CLKCR = tmpreg; +} + +/********************************************************************* + * @fn SDIO_StructInit + * + * @brief Fills each SDIO_InitStruct member with its default value. + * + * @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SDIO_StructInit(SDIO_InitTypeDef *SDIO_InitStruct) +{ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/********************************************************************* + * @fn SDIO_ClockCmd + * + * @brief Enables or disables the SDIO Clock. + * + * @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CLKCR |= (1 << 8); + else + SDIO->CLKCR &= ~(1 << 8); +} + +/********************************************************************* + * @fn SDIO_SetPowerState + * + * @brief Sets the power status of the controller. + * + * @param SDIO_PowerState - new state of the Power state. + * SDIO_PowerState_OFF + * SDIO_PowerState_ON + * + * @return none + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + SDIO->POWER &= PWR_PWRCTRL_MASK; + SDIO->POWER |= SDIO_PowerState; +} + +/********************************************************************* + * @fn SDIO_GetPowerState + * + * @brief Gets the power status of the controller. + * + * @param CounterValue - RTC counter new value. + * + * @return power state - + * 0x00 - Power OFF + * 0x02 - Power UP + * 0x03 - Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/********************************************************************* + * @fn SDIO_ITConfig + * + * @brief Enables or disables the SDIO interrupts. + * + * @param DIO_IT - specifies the SDIO interrupt sources to be enabled or disabled. + * SDIO_IT_CCRCFAIL + * SDIO_IT_DCRCFAIL + * SDIO_IT_CTIMEOUT + * SDIO_IT_DTIMEOUT + * SDIO_IT_TXUNDERR + * SDIO_IT_RXOVERR + * SDIO_IT_CMDREND + * SDIO_IT_CMDSENT + * SDIO_IT_DATAEND + * SDIO_IT_STBITERR + * SDIO_IT_DBCKEND + * SDIO_IT_CMDACT + * SDIO_IT_TXACT + * SDIO_IT_RXACT + * SDIO_IT_TXFIFOHE + * SDIO_IT_RXFIFOHF + * SDIO_IT_TXFIFOF + * SDIO_IT_RXFIFOF + * SDIO_IT_TXFIFOE + * SDIO_IT_RXFIFOE + * SDIO_IT_TXDAVL + * SDIO_IT_RXDAVL + * SDIO_IT_SDIOIT + * SDIO_IT_CEATAEND + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SDIO->MASK |= SDIO_IT; + } + else + { + SDIO->MASK &= ~SDIO_IT; + } +} + +/********************************************************************* + * @fn SDIO_DMACmd + * + * @brief Enables or disables the SDIO DMA request. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 3); + else + SDIO->DCTRL &= ~(1 << 3); +} + +/********************************************************************* + * @fn SDIO_SendCommand + * + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct - pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for + * ddthe SDIO command. + * + * @return none + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + + tmpreg = SDIO->CMD; + tmpreg &= CMD_CLEAR_MASK; + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + SDIO->CMD = tmpreg; +} + +/********************************************************************* + * @fn SDIO_CmdStructInit + * + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * + * @param SDIO_CmdInitStruct - pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/********************************************************************* + * @fn SDIO_GetCommandResponse + * + * @brief Returns command index of last command for which response received. + * + * @return Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/********************************************************************* + * @fn SDIO_GetResponse + * + * @brief Returns response received from the card for the last command. + * + * @param SDIO_RESP - Specifies the SDIO response register. + * SDIO_RESP1 - Response Register 1 + * SDIO_RESP2 - Response Register 2 + * SDIO_RESP3 - Response Register 3 + * SDIO_RESP4 - Response Register 4 + * + * @return Returns the command index of the last command response received. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn SDIO_DataConfig + * + * @brief Initializes the SDIO data path according to the specified + * + * @param SDIO_DataInitStruct - pointer to a SDIO_DataInitTypeDef structure that + * contains the configuration information for the SDIO command. + * + * @return none + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef *SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + tmpreg = SDIO->DCTRL; + tmpreg &= DCTRL_CLEAR_MASK; + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + SDIO->DCTRL = tmpreg; +} + +/********************************************************************* + * @fn SDIO_DataStructInit + * + * @brief Fills each SDIO_DataInitStruct member with its default value. + * + * @param SDIO_DataInitStruct - pointer to an SDIO_DataInitTypeDef + * structure which will be initialized. + * + * @return RTC counter value + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef *SDIO_DataInitStruct) +{ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/********************************************************************* + * @fn SDIO_GetDataCounter + * + * @brief Returns number of remaining data bytes to be transferred. + * + * @return Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/********************************************************************* + * @fn SDIO_ReadData + * + * @brief Read one data word from Rx FIFO. + * + * @return Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/********************************************************************* + * @fn SDIO_WriteData + * + * @brief Write one data word to Tx FIFO. + * + * @param Data - 32-bit data word to write. + * + * @return RTC counter value + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/********************************************************************* + * @fn SDIO_GetFIFOCount + * + * @brief Returns the number of words left to be written to or read from FIFO. + * + * @return Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/********************************************************************* + * @fn SDIO_StartSDIOReadWait + * + * @brief Starts the SD I/O Read Wait operation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 8); + else + SDIO->DCTRL &= ~(1 << 8); +} + +/********************************************************************* + * @fn SDIO_StopSDIOReadWait + * + * @brief Stops the SD I/O Read Wait operation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 9); + else + SDIO->DCTRL &= ~(1 << 9); +} + +/********************************************************************* + * @fn SDIO_SetSDIOReadWaitMode + * + * @brief Sets one of the two options of inserting read wait interval. + * + * @param SDIO_ReadWaitMode - SD I/O Read Wait operation mode. + * SDIO_ReadWaitMode_CLK - Read Wait control by stopping SDIOCLK + * SDIO_ReadWaitMode_DATA2 - Read Wait control using SDIO_DATA2 + * + * @return none + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + if(SDIO_ReadWaitMode) + SDIO->DCTRL |= (1 << 10); + else + SDIO->DCTRL &= ~(1 << 10); +} + +/********************************************************************* + * @fn SDIO_SetSDIOOperation + * + * @brief Enables or disables the SD I/O Mode Operation. + * + * @param NewState: ENABLE or DISABLE. + * + * @return none + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 11); + else + SDIO->DCTRL &= ~(1 << 11); +} + +/********************************************************************* + * @fn SDIO_SendSDIOSuspendCmd + * + * @brief Enables or disables the SD I/O Mode suspend command sending. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 11); + else + SDIO->CMD &= ~(1 << 11); +} + +/********************************************************************* + * @fn SDIO_CommandCompletionCmd + * + * @brief Enables or disables the command completion signal. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 12); + else + SDIO->CMD &= ~(1 << 12); +} + +/********************************************************************* + * @fn SDIO_CEATAITCmd + * + * @brief Enables or disables the CE-ATA interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 13); + else + SDIO->CMD &= ~(1 << 13); +} + +/********************************************************************* + * @fn SDIO_SendCEATACmd + * + * @brief Sends CE-ATA command (CMD61). + * + * @param NewState - ENABLE or DISABLE. + * + * @return RTC counter value + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 14); + else + SDIO->CMD &= ~(1 << 14); +} + +/********************************************************************* + * @fn SDIO_GetFlagStatus + * + * @brief Checks whether the specified SDIO flag is set or not. + * + * @param SDIO_FLAG - specifies the flag to check. + * SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed) + * SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed) + * SDIO_FLAG_CTIMEOUT - Command response timeout + * SDIO_FLAG_DTIMEOUT - Data timeout + * SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error + * SDIO_FLAG_RXOVERR - Received FIFO overrun error + * SDIO_FLAG_CMDREND - Command response received (CRC check passed) + * SDIO_FLAG_CMDSENT - Command sent (no response required) + * SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero) + * SDIO_FLAG_STBITERR - Start bit not detected on all data signals + * in wide bus mode. + * SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed) + * SDIO_FLAG_CMDACT - Command transfer in progress + * SDIO_FLAG_TXACT - Data transmit in progress + * SDIO_FLAG_RXACT - Data receive in progress + * SDIO_FLAG_TXFIFOHE - Transmit FIFO Half Empty + * SDIO_FLAG_RXFIFOHF - Receive FIFO Half Full + * SDIO_FLAG_TXFIFOF - Transmit FIFO full + * SDIO_FLAG_RXFIFOF - Receive FIFO full + * SDIO_FLAG_TXFIFOE - Transmit FIFO empty + * SDIO_FLAG_RXFIFOE - Receive FIFO empty + * SDIO_FLAG_TXDAVL - Data available in transmit FIFO + * SDIO_FLAG_RXDAVL - Data available in receive FIFO + * SDIO_FLAG_SDIOIT - SD I/O interrupt received + * SDIO_FLAG_CEATAEND - CE-ATA command completion signal received + * for CMD61 + * + * @return ITStatus - SET or RESET + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn SDIO_ClearFlag + * + * @brief Clears the SDIO's pending flags. + * + * @param SDIO_FLAG - specifies the flag to clear. + * SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed) + * SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed) + * SDIO_FLAG_CTIMEOUT - Command response timeout + * SDIO_FLAG_DTIMEOUT - Data timeout + * SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error + * SDIO_FLAG_RXOVERR - Received FIFO overrun error + * SDIO_FLAG_CMDREND - Command response received (CRC check passed) + * SDIO_FLAG_CMDSENT - Command sent (no response required) + * SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero) + * SDIO_FLAG_STBITERR - Start bit not detected on all data signals + * in wide bus mode + * SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed) + * SDIO_FLAG_SDIOIT - SD I/O interrupt received + * SDIO_FLAG_CEATAEND - CE-ATA command completion signal received for CMD61 + * + * @return none + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + SDIO->ICR = SDIO_FLAG; +} + +/********************************************************************* + * @fn SDIO_GetITStatus + * + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt + * SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt + * SDIO_IT_CTIMEOUT - Command response timeout interrupt + * SDIO_IT_DTIMEOUT - Data timeout interrupt + * SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt + * SDIO_IT_RXOVERR - Received FIFO overrun error interrupt + * SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt + * SDIO_IT_CMDSENT - Command sent (no response required) interrupt + * SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt + * SDIO_IT_STBITERR - Start bit not detected on all data signals in wide + * bus mode interrupt + * SDIO_IT_DBCKEND - Data block sent/received (CRC check passed) interrupt + * SDIO_IT_CMDACT - Command transfer in progress interrupt + * SDIO_IT_TXACT - Data transmit in progress interrupt + * SDIO_IT_RXACT - Data receive in progress interrupt + * SDIO_IT_TXFIFOHE - Transmit FIFO Half Empty interrupt + * SDIO_IT_RXFIFOHF - Receive FIFO Half Full interrupt + * SDIO_IT_TXFIFOF - Transmit FIFO full interrupt + * SDIO_IT_RXFIFOF - Receive FIFO full interrupt + * SDIO_IT_TXFIFOE - Transmit FIFO empty interrupt + * SDIO_IT_RXFIFOE - Receive FIFO empty interrupt + * SDIO_IT_TXDAVL - Data available in transmit FIFO interrupt + * SDIO_IT_RXDAVL - Data available in receive FIFO interrupt + * SDIO_IT_SDIOIT - SD I/O interrupt received interrupt + * SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 interrupt + * + * @return ITStatusSET or RESET + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + if((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn SDIO_ClearITPendingBit + * + * @brief Clears the SDIO's interrupt pending bits. + * + * @param SDIO_IT - specifies the interrupt pending bit to clear. + * SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt + * SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt + * SDIO_IT_CTIMEOUT - Command response timeout interrupt + * SDIO_IT_DTIMEOUT - Data timeout interrupt + * SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt + * SDIO_IT_RXOVERR - Received FIFO overrun error interrupt + * SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt + * SDIO_IT_CMDSENT - Command sent (no response required) interrupt + * SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt + * SDIO_IT_STBITERR - Start bit not detected on all data signals in wide + * bus mode interrupt + * SDIO_IT_SDIOIT - SD I/O interrupt received interrupt + * SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 + * + * @return RTC counter value + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + SDIO->ICR = SDIO_IT; +} diff --git a/libraries/sdk/Peripheral/ch32v30x_sdio.h b/libraries/sdk/Peripheral/ch32v30x_sdio.h new file mode 100644 index 0000000..12d4c4e --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_sdio.h @@ -0,0 +1,254 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_sdio.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the SDIO +* firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_SDIO_H +#define __CH32V30x_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* SDIO Init structure definition */ +typedef struct +{ + uint32_t SDIO_ClockEdge; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /* Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /* Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /* Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /* Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /* Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + + +typedef struct +{ + uint32_t SDIO_Argument; /* Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /* Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /* Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /* Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /* Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /* Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /* Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /* Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /* Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /* Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /* Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + + +/* SDIO_Clock_Edge */ +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) + +/* SDIO_Clock_Bypass */ +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) + +/* SDIO_Clock_Power_Save */ +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) + +/* SDIO_Bus_Wide */ +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) + +/* SDIO_Hardware_Flow_Control */ +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) + +/* SDIO_Power_State */ +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) + +/* SDIO_Interrupt_sources */ +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) + +/* SDIO_Response_Type */ +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) + +/* SDIO_Wait_Interrupt_State */ +#define SDIO_Wait_No ((uint32_t)0x00000000) +#define SDIO_Wait_IT ((uint32_t)0x00000100) +#define SDIO_Wait_Pend ((uint32_t)0x00000200) + +/* SDIO_CPSM_State */ +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) + +/* SDIO_Response_Registers */ +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) + +/* SDIO_Data_Block_Size */ +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) + +/* SDIO_Transfer_Direction */ +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) + +/* SDIO_Transfer_Type */ +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) + +/* SDIO_DPSM_State */ +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) + +/* SDIO_Flags */ +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) + +/* SDIO_Read_Wait_Mode */ +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) + + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/sdk/Peripheral/ch32v30x_spi.c b/libraries/sdk/Peripheral/ch32v30x_spi.c new file mode 100644 index 0000000..105d182 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_spi.c @@ -0,0 +1,646 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_spi.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the SPI firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*********************************************************************************/ +#include "ch32v30x_spi.h" +#include "ch32v30x_rcc.h" + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if(SPIx == SPI2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if(SPIx == SPI3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->I2SCFGR &= SPI_Mode_Select; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn I2S_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * (configured in I2S mode). + * I2S_InitStruct - pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @return none + */ +void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + tmpreg = SPIx->I2SCFGR; + + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + else + { + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + packetlength = 1; + } + else + { + packetlength = 2; + } + + if(((uint32_t)SPIx) == SPI2_BASE) + { + tmp = I2S2_CLOCK_SRC; + } + else + { + tmp = I2S3_CLOCK_SRC; + } + + RCC_GetClocksFreq(&RCC_Clocks); + + sourceclock = RCC_Clocks.SYSCLK_Frequency; + + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + tmp = tmp / 10; + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + i2sodd = (uint16_t)(i2sodd << 8); + } + + if((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + i2sdiv = 2; + i2sodd = 0; + } + + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + SPIx->I2SCFGR = tmpreg; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn I2S_StructInit + * + * @brief Fills each I2S_InitStruct member with its default value. + * + * @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct) +{ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn I2S_Cmd + * + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI/I2S interrupts. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState: ENABLE or DISABLE. + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg: The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI/I2S flag is set or not. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * I2S_FLAG_UDR - Underrun Error flag. + * I2S_FLAG_CHSIDE - Channel Side flag. + * + * @return none + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * + * @return none + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * I2S_IT_UDR - Underrun Error interrupt. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} diff --git a/libraries/sdk/Peripheral/ch32v30x_spi.h b/libraries/sdk/Peripheral/ch32v30x_spi.h new file mode 100644 index 0000000..94391de --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_spi.h @@ -0,0 +1,229 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_spi.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* SPI firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_SPI_H +#define __CH32V30x_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/* I2S Init structure definition */ +typedef struct +{ + + uint16_t I2S_Mode; /* Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB_transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* I2S_Mode */ +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) + +/* I2S_Standard */ +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) + +/* I2S_Data_Format */ +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) + +/* I2S_MCLK_Output */ +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) + +/* I2S_Audio_Frequency */ +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +/* I2S_Clock_Polarity */ +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_tim.c b/libraries/sdk/Peripheral/ch32v30x_tim.c new file mode 100644 index 0000000..182ab10 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_tim.c @@ -0,0 +1,2366 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_tim.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the TIM firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_tim.h" +#include "ch32v30x_rcc.h" + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if(TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if(TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if(TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if(TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if(TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if(TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if(TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CTLR1 = tmpcr1; + TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMABase: DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values (Affects also the I2Ss). + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 4 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) +{ + TIMx->CNT = Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) +{ + TIMx->ATRLR = Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) +{ + TIMx->CH1CVR = Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) +{ + TIMx->CH2CVR = Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) +{ + TIMx->CH3CVR = Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) +{ + TIMx->CH4CVR = Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture3 + * + * @brief Gets the TIMx Input Capture 3 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH3CVR - Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC4NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} diff --git a/libraries/sdk/Peripheral/ch32v30x_tim.h b/libraries/sdk/Peripheral/ch32v30x_tim.h new file mode 100644 index 0000000..0ea77da --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_tim.h @@ -0,0 +1,515 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_tim.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* TIM firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_TIM_H +#define __CH32V30x_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + + +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_usart.c b/libraries/sdk/Peripheral/ch32v30x_usart.c new file mode 100644 index 0000000..b7749ce --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_usart.c @@ -0,0 +1,826 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_usart.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the USART firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_usart.h" +#include "ch32v30x_rcc.h" + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if(USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if(USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if(USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else if(USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + else if(USARTx == UART6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, DISABLE); + } + else if(USARTx == UART7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); + } + else if(USARTx == UART8) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE); + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else + { + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_CTS - CTS change interrupt. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + if(USART_IT == USART_IT_CTS) + { + } + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_OverSampling8Cmd + * + * @brief Enables or disables the USART's 8x oversampling mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_OVER8_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_OVER8_Reset; + } +} + +/********************************************************************* + * @fn USART_OneBitMethodCmd + * + * @brief Enables or disables the USART's one bit sampling method. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_ONEBITE_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_ONEBITE_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_CTS - CTS Change flag. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return none + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(USART_FLAG == USART_FLAG_CTS) + { + } + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_CTS - CTS Change flag. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + if((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) + { + } + + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_CTS - CTS change interrupt. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return none + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + if(USART_IT == USART_IT_CTS) + { + } + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_CTS - CTS change interrupt. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + if(USART_IT == USART_IT_CTS) + { + } + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/libraries/sdk/Peripheral/ch32v30x_usart.h b/libraries/sdk/Peripheral/ch32v30x_usart.h new file mode 100644 index 0000000..f394494 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_usart.h @@ -0,0 +1,195 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_usart.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* USART firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_USART_H +#define __CH32V30x_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + + +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/libraries/sdk/Peripheral/ch32v30x_usbotg_device.c b/libraries/sdk/Peripheral/ch32v30x_usbotg_device.c new file mode 100644 index 0000000..71ccf06 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_usbotg_device.c @@ -0,0 +1,908 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : zf_usb_cdc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the USBOTG firmware functions. +*******************************************************************************/ +#include "stdio.h" + +#include "ch32v30x_rcc.h" +#include "ch32v30x_usbotg_device.h" + + + +/* Global define */ +/* OTH */ +#define pMySetupReqPakHD ((PUSB_SETUP_REQ)EP0_DatabufHD) +#define RepDescSize 62 +#define DevEP0SIZE 8 +#define PID_OUT 0 +#define PID_SOF 1 +#define PID_IN 2 +#define PID_SETUP 3 + +typedef struct{ + UINT8 dataRat[4]; + UINT8 stopBit; + UINT8 parityType; + UINT8 dataBit; +}LINECODINGST; + +/******************************************************************************/ +/* ȫֱ */ +/* Endpoint Buffer */ +__attribute__ ((aligned(4))) UINT8 EP0_DatabufHD[8]; //ep0(64) +__attribute__ ((aligned(4))) UINT8 EP1_DatabufHD[64+64]; //ep1_out(64)+ep1_in(64) +__attribute__ ((aligned(4))) UINT8 EP2_DatabufHD[64+64]; //ep2_out(64)+ep2_in(64) + + +PUINT8 pEP0_RAM_Addr; //ep0(64) +PUINT8 pEP1_RAM_Addr; //ep1_out(64)+ep1_in(64) +PUINT8 pEP2_RAM_Addr; //ep2_out(64)+ep2_in(64) + + +const UINT8 *pDescr; +volatile UINT8 USBHD_Dev_SetupReqCode = 0xFF; /* USB2.0豸Setup */ +volatile UINT16 USBHD_Dev_SetupReqLen = 0x00; /* USB2.0豸Setup */ +volatile UINT8 USBHD_Dev_SetupReqValueH = 0x00; /* USB2.0豸SetupValueֽ */ +volatile UINT8 USBHD_Dev_Config = 0x00; /* USB2.0豸ֵ */ +volatile UINT8 USBHD_Dev_Address = 0x00; /* USB2.0豸ֵַ */ +volatile UINT8 USBHD_Dev_SleepStatus = 0x00; /* USB2.0豸˯״̬ */ +volatile UINT8 USBHD_Dev_EnumStatus = 0x00; /* USB2.0豸ö״̬ */ +volatile UINT8 USBHD_Dev_Endp0_Tog = 0x01; /* USB2.0豸˵0ͬ־ */ +volatile UINT8 USBHD_Dev_Speed = 0x01; /* USB2.0豸ٶ */ + +volatile UINT16 USBHD_Endp1_Up_Flag = 0x00; /* USB2.0豸˵1ϴ״̬: 0:; 1:ϴ; */ +volatile UINT8 USBHD_Endp1_Down_Flag = 0x00; /* USB2.0豸˵1´ɹ־ */ +volatile UINT8 USBHD_Endp1_Down_Len = 0x00; /* USB2.0豸˵1´ */ +volatile BOOL USBHD_Endp1_T_Tog = 0; /* USB2.0豸˵1togλת */ +volatile BOOL USBHD_Endp1_R_Tog = 0; + +volatile UINT16 USBHD_Endp2_Up_Flag = 0x00; /* USB2.0豸˵2ϴ״̬: 0:; 1:ϴ; */ +volatile UINT16 USBHD_Endp2_Up_LoadPtr = 0x00; /* USB2.0豸˵2ϴװƫ */ +volatile UINT8 USBHD_Endp2_Down_Flag = 0x00; /* USB2.0豸˵2´ɹ־ */ + +volatile UINT32V Endp2_send_seq=0x00; +volatile UINT8 DevConfig; +volatile UINT8 SetupReqCode; +volatile UINT16 SetupReqLen; + + +/******************************************************************************/ +/* Device Descriptor */ +//豸һȫ豸 +const UINT8 MyDevDescrHD[] = +{ + 0x12, //豸ȣ18ֽ + 0x01, //ͣ0x01Ϊ豸 + 0x00,0x02, //豸ʹUSB汾Э飬ΪС˽ṹԵֽǰUSB1.1汾Ϊ0x10,0x01USB2.0Ϊ0x00,0x02 + 0x02, //룬CDCΪ0x02CDC豸ָ豸ͣ0x02üӿڣᱻϵͳΪһUSB豸Ӷ豸 + //ָ豸Ϊͨ豸ʹõЭ鶼ָΪ0. + 0x00, //룬bDeviceClassΪ0ʱbDeviceSubClassҲΪ0 + 0x00, //豸ʹõЭ飬ЭUSBЭ涨ֶΪ0ʱʾ豸ʹЭ顣 + + DevEP0SIZE, //˵0ȡֵ8163264˴Ϊ64ֽ + 0x86,0x1a, //ID + 0x22,0x57, //Ʒ豸ID + 0x00,0x01, //豸汾 + 0x01, //̵ֵֵַΪ0ʱʾûгַ + 0x02, //ƷֵֵַΪ0ʱʾûвƷַ + 0x03, //豸кֵֵַΪ0ʱʾûкַ + 0x01, //ܵͨΪ1 +}; + + +/* Configration Descriptor */ +// +const UINT8 MyCfgDescrHD[] = +{ + //ӿڣ + 0x09, //ȣ׼USBΪ9ֽ + 0x02, //ͣΪ0x02 + 0x43,0x00, //ܳȣ67ֽ + 0x02, //ֵ֧Ľӿ2ӿ + 0x01, //ʾõֵ + 0x00, //õֵַ0x00ʾûַ + 0xa0, //豸һЩԣ繩緽ʽͻѵȣ0xA0ʾ豸߹֧Զ̻ + 0x32, //豸Ҫ߻ȡ0x32ʾ100ma + + //Ϊӿ0CDCӿڣӿܵأ븽һ + 0x09, //ӿȣ׼USBӿΪ9ֽ + 0x04, //ͣӿΪ0x04 + 0x00, //ýӿڵıţ0ʼ˴Ϊ0x00 + 0x00, //ýӿڵıñ,ͨΪ0 + 0x01, //ýӿʹõĶ˵0x01ʾʹ1˵㡣ֶΪ0ʾûз0˵㣬ֻʹĬϵĿƶ˵㡣CDCӿֻʹһж˵ + 0x02, //ýӿʹõ࣬0x02ΪCDC + 0x02, //ýӿʹõ࣬ҪʵUSBתڣͱʹAbstract Control Modelģͣ࣬ıΪ0x02 + 0x01, //ýӿʹõЭ飬ʹCommon AT CommandsͨATЭ + 0x00, //ýӿڵֵַ0x00ʾûַ + + + //Ϊӿ + //ҪӿڵĹܣCDCӿڣӿڣ֮ + //Header Functional Descriptor + 0x05, //ùijȣ5ֽ + 0x24, //̶ͣλ0x24CS_INTERFACEı룩 + 0x00, // + 0x10,0x01, //USBͨ豸Эİ汾š˴ΪUSB1.1 + + //(ûӿ) + //Call Management Functional Descriptor + 0x05, //ùijȣ5ֽ + 0x24, //̶ͣλ0x24CS_INTERFACEı룩 + 0x01, // + 0x00, //豸ֻλD0D1壬λΪֵ0D0Ϊ0ʾ豸ԼùΪ1ʾԼ + 0x00, //ʾѡùӿڱţڲʹӿùֶΪ0 + + //Abstract Control Management Functional Descriptor ƹ + 0x04, //ùijȣ4ֽ + 0x24, //̶ͣλ0x24CS_INTERFACEı룩 + 0x02, // + 0x02, //豸D7-4λΪλΪ0֧Set_Line_CodingSet_Control_Line_StateGet_Line_CodingSerial_State֪ͨ + //D0ʾǷ֧Set_Comm_FeatureClear_Comm_FeatureGet_Comm_Feature,Ϊ1ʾ֧֣ + //D1λʾǷ֧Set_Line_CodingSet_Control_Line_StateGet_Line_CodingSerial_State֪ͨΪ1ʾ֧ + //D2ΪʾǷ֧Send_BreakΪ1ʾ֧ + //D3ʾǷ֧Network_Connection֪ͨΪ1ʾ֧ + + //Union Functional Descriptor5ֽڣһӿ֮ĹϵԱΪһܵԪЩӿһΪӿڣΪӽӿ + 0x05, //ùijȣ5ֽ + 0x24, //̶ͣλ0x24CS_INTERFACEı룩 + 0x06, // + 0x00, //ֽΪӿڱţ˴ΪΪ0CDCӿ + 0x01, //ֽΪһӽӿڱţ˴Ϊ1ӿڣֻһӽӿ + + //ӿ0CDCӿڣĶ˵ ˵1 + 0x07, //˵ȣ7ֽ + 0x05, //ͣ˵Ϊ0x05 + 0x81, //ö˵ĵַ0x81ʾ˵1Ϊ + 0x03, //ö˵ԡλD1-0ʾö˵Ĵͣ0Ϊƴ䣬1Ϊʱ䣬2Ϊ䣬3Ϊжϴ + 0x40,0x00, //ö˵ֵ֧ȣ64ֽ + 0xFF, //˵IJѯʱ + + //Ϊӿ1ݽӿڣ ˵2 + //CDCӿڣӿ0Ǹ豸ģĴݴӿڽеġֻʹһӿڣΪ1 + 0x09, //ӿȣ9ֽ + 0x04, //ͣӿΪ0x04 + 0x01, //ýӿڵıţ0ʼ˴Ϊ0x01 + 0x00, //ýӿڵıñ + 0x02, //ýӿʹõĶ˵ýӿҪʹһ˵㣬˵Ϊ2 + 0x0a, //ýӿʹõ࣬0x0aΪCDC + 0x00, //ýӿʹõ + 0x00, //ýӿʹõЭ + 0x00, //ýӿڵֵַ0x00ʾûַ + + //ӿ1ӿڣĶ˵ ˵2 + 0x07, //˵ȣ7ֽ + 0x05, //ͣ˵Ϊ0x05 + 0x02, //ö˵ĵַ0x02ʾ˵2Ϊ + 0x02, //ö˵ԡλD1-0ʾö˵Ĵͣ0Ϊƴ䣬1Ϊʱ䣬2Ϊ䣬3Ϊжϴ + 0x40,0x00, //ö˵ֵ֧ȣ64ֽ + 0x00, //˵IJѯʱ䣬˵Ч + + 0x07, //˵ȣ7ֽ + 0x05, //ͣ˵Ϊ0x05 + 0x82, //ö˵ĵַ0x82ʾ˵2Ϊ + 0x02, //ö˵ԡλD1-0ʾö˵Ĵͣ0Ϊƴ䣬1Ϊʱ䣬2Ϊ䣬3Ϊжϴ + 0x40,0x00, //ö˵ֵ֧ȣ64ֽ + 0x00, //˵IJѯʱ䣬˵Ч //˵ + +}; + +/* USB */ +const UINT8 MyReportDescHD[ ] = +{0x14,0x03,0x32,0x00,0x30,0x00,0x31,0x00,0x37,0x00,0x2D,0x00,0x32,0x00,0x2D,0x00,0x32,0x00,0x35,0x00}; + +/* Language Descriptor */ +const UINT8 MyLangDescrHD[] = +{ + 0x04, 0x03, 0x09, 0x04 +}; + +/* Manufactor Descriptor */ +const UINT8 MyManuInfoHD[] = +{ + 0x0E, 0x03, 'w', 0, 'c', 0, 'h', 0, '.', 0, 'c', 0, 'n', 0 +}; + +/* Product Information */ +const UINT8 MyProdInfoHD[] = +{ + 0x0C, 0x03, 'C', 0, 'H', 0, '3', 0, '0', 0, '7', 0 +}; + +/* USBкַ */ +const UINT8 MySerNumInfoHD[ ] = +{ + /* 0123456789 */ + 22,03,48,0,49,0,50,0,51,0,52,0,53,0,54,0,55,0,56,0,57,0 +}; + +/* USB豸޶ */ +const UINT8 MyUSBQUADescHD[ ] = +{ + 0x0A, 0x06, 0x00, 0x02, 0xFF, 0x00, 0xFF, 0x40, 0x01, 0x00, +}; + +/* USBȫģʽ,ٶ */ +UINT8 TAB_USB_FS_OSC_DESC[ sizeof( MyCfgDescrHD ) ] = +{ + 0x09, 0x07, /* ͨ */ +}; + + +void OTG_FS_IRQHandler(void) __attribute__((interrupt())); + +/******************************************************************************* +* Function Name : USBOTG_FS_DeviceInit +* Description : Initializes USB device. +* Input : None +* Return : None +*******************************************************************************/ +void USBDeviceInit( void ) +{ + USBOTG_FS->BASE_CTRL = 0x00; + + USBOTG_FS->UEP4_1_MOD = USBHD_UEP4_RX_EN|USBHD_UEP4_TX_EN|USBHD_UEP1_RX_EN|USBHD_UEP1_TX_EN; + USBOTG_FS->UEP2_3_MOD = USBHD_UEP2_RX_EN|USBHD_UEP2_TX_EN|USBHD_UEP3_RX_EN|USBHD_UEP3_TX_EN; + USBOTG_FS->UEP5_6_MOD = USBHD_UEP5_RX_EN|USBHD_UEP5_TX_EN|USBHD_UEP6_RX_EN|USBHD_UEP6_TX_EN; + USBOTG_FS->UEP7_MOD = USBHD_UEP7_RX_EN|USBHD_UEP7_TX_EN; + + USBOTG_FS->UEP0_DMA = (UINT32)pEP0_RAM_Addr; + USBOTG_FS->UEP1_DMA = (UINT32)pEP1_RAM_Addr; + USBOTG_FS->UEP2_DMA = (UINT32)pEP2_RAM_Addr; + + + USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK; + USBOTG_FS->UEP1_RX_CTRL = USBHD_UEP_R_RES_ACK; + USBOTG_FS->UEP2_RX_CTRL = USBHD_UEP_R_RES_ACK; + + USBOTG_FS->UEP1_TX_LEN = 8; + USBOTG_FS->UEP2_TX_LEN = 8; + + + USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK; + USBOTG_FS->UEP1_TX_CTRL = USBHD_UEP_T_RES_NAK; + USBOTG_FS->UEP2_TX_CTRL = USBHD_UEP_T_RES_NAK; + + + USBOTG_FS->INT_FG = 0xFF; + USBOTG_FS->INT_EN = USBHD_UIE_SUSPEND | USBHD_UIE_BUS_RST | USBHD_UIE_TRANSFER; + USBOTG_FS->DEV_ADDR = 0x00; + + USBOTG_FS->BASE_CTRL = USBHD_UC_DEV_PU_EN | USBHD_UC_INT_BUSY | USBHD_UC_DMA_EN; + USBOTG_FS->UDEV_CTRL = USBHD_UD_PD_DIS|USBHD_UD_PORT_EN; +} +/******************************************************************************* +* Function Name : USBOTG_RCC_Init +* Description : USBOTG RCC init +* Input : None +* Return : None +*******************************************************************************/ +void USBOTG_RCC_Init( void ) +{ + RCC_USBCLK48MConfig( RCC_USBCLK48MCLKSource_USBPHY ); + RCC_USBHSPLLCLKConfig( RCC_HSBHSPLLCLKSource_HSE ); + RCC_USBHSConfig( RCC_USBPLL_Div2 ); + RCC_USBHSPLLCKREFCLKConfig( RCC_USBHSPLLCKREFCLK_4M ); + RCC_USBHSPHYPLLALIVEcmd( ENABLE ); + RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBHS, ENABLE ); + RCC_AHBPeriphClockCmd( RCC_AHBPeriph_OTG_FS, ENABLE ); + + + +} + + +/**********************************************************/ +UINT8 Ready = 0; +UINT8 UsbConfig; +//UINT8 SetupReqCode; +//UINT16 SetupReqLen; + +//CDC +UINT8 LineCoding[7]={0x00,0xC2,0x01,0x00,0x00,0x00,0x08}; //ʼΪ576001ֹͣλУ飬8λ + +#define SET_LINE_CODING 0x20 //Configures DTE rate, stop-bits, parity, and number-of-character +#define GET_LINE_CODING 0x21 //This request allows the host to find out the currently configured line coding. +#define SET_CONTROL_LINE_STATE 0x22 //This request generates RS-232/V.24 style control signals. +#define UART_REV_LEN 0x40 //ڽջС + +UINT8 Receive_Uart_Buf[UART_REV_LEN]; //ڽջ +volatile UINT8 Uart_Input_Point = 0; //ѭдָ룬߸λҪʼΪ0 +volatile UINT8 Uart_Output_Point = 0; //ѭȡָ룬߸λҪʼΪ0 +volatile UINT8 UartByteCount = 0; //ǰʣȡֽ +volatile UINT8 USBByteCount = 0; //USB˵յ +volatile UINT8 USBBufOutPoint = 0; //ȡָ +volatile UINT8 UpPoint2_Busy = 0; //ϴ˵Ƿæ־ + +const UINT8 *pDescr; + + +/******************************************************************************* +* Function Name : DevEP1_IN_Deal +* Description : Device endpoint1 IN. +* Input : l: IN length(<64B) +* Return : None +*******************************************************************************/ +void DevEP1_IN_Deal( UINT8 l ) +{ + USBOTG_FS->UEP1_TX_LEN = l; + USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL & ~USBHD_UEP_T_RES_MASK)| USBHD_UEP_T_RES_ACK; +} + +/******************************************************************************* +* Function Name : DevEP2_IN_Deal +* Description : Device endpoint2 IN. +* Input : l: IN length(<64B) +* Return : None +*******************************************************************************/ +void DevEP2_IN_Deal( UINT8 l ) +{ + USBOTG_FS->UEP2_TX_LEN = l; + USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL & ~USBHD_UEP_T_RES_MASK)| USBHD_UEP_T_RES_ACK; +} + +/******************************************************************************* +* Function Name : DevEP1_OUT_Deal +* Description : Deal device Endpoint 1 OUT. +* Input : l: Data length. +* Return : None +*******************************************************************************/ +void DevEP1_OUT_Deal( UINT8 l ) +{ + UINT8 i; + + for(i=0; iINT_FG; + + if( intflag & USBHD_UIF_TRANSFER ) + { + switch ( USBOTG_FS->INT_ST & USBHD_UIS_TOKEN_MASK ) + { + + /* SETUP */ + case USBHD_UIS_TOKEN_SETUP: + /* ӡǰUsbsetup */ +// printf( "Setup Req :\n" ); +// printf( "%02X ", pSetupReqPakHD->bRequestType ); +// printf( "%02X ", pSetupReqPakHD->bRequest ); +// printf( "%04X ", pSetupReqPakHD->wValue ); +// printf( "%04X ", pSetupReqPakHD->wIndex ); +// printf( "%04X ", pSetupReqPakHD->wLength ); +// printf( "\n" ); + + USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_TOG|USBHD_UEP_T_RES_NAK; + USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_TOG|USBHD_UEP_R_RES_ACK; + SetupReqLen = pSetupReqPakHD->wLength; + SetupReqCode = pSetupReqPakHD->bRequest; + chtype = pSetupReqPakHD->bRequestType; + len = 0; + errflag = 0; + /* жϵǰDZ׼ */ + if ( ( pSetupReqPakHD->bRequestType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD ) //DZ׼ + { + //CDC + if(SetupReqCode & 0x20) + { + switch( SetupReqCode ) + { + case GET_LINE_CODING: //0x21 currently configured + pDescr = LineCoding; + len = sizeof(LineCoding); + len = SetupReqLen >= DEFAULT_ENDP0_SIZE ? DEFAULT_ENDP0_SIZE : SetupReqLen; // δ䳤 + memcpy(pEP0_DataBuf,pDescr,len); + SetupReqLen -= len; + pDescr += len; + break; + + case SET_CONTROL_LINE_STATE: //0x22 generates RS-232/V.24 style control signals + break; + + case SET_LINE_CODING: //0x20 Configure + break; + + default: + errflag = 0xFF; + } + } + + +// /* ,, */ +// if( pSetupReqPakHD->bRequestType & 0x40 ) +// { +// /* */ +// switch( pSetupReqPakHD->bRequest ) +// { +// default: +// errflag = 0xFF;/* ʧ */ +// break; +// } +// } +// } + + /* жǷ */ + if( errflag != 0xFF ) + { + if( SetupReqLen > len ) + { + SetupReqLen = len; + } + len = ( USBHD_Dev_SetupReqLen >= DevEP0SIZE ) ? DevEP0SIZE : USBHD_Dev_SetupReqLen; + memcpy( EP0_DatabufHD, pDescr, len ); + pDescr += len; + } + } + else + { + /* ׼USB */ + switch( SetupReqCode ) + { + case USB_GET_DESCRIPTOR: + { + switch( ((pSetupReqPakHD->wValue)>>8) ) + { + case USB_DESCR_TYP_DEVICE: + /* ȡ豸 */ + pDescr = MyDevDescrHD; + len = MyDevDescrHD[0]; + break; + + case USB_DESCR_TYP_CONFIG: + /* ȡ */ + pDescr = MyCfgDescrHD; + len = MyCfgDescrHD[2]; + break; + + case USB_DESCR_TYP_STRING: + /* ȡַ */ + switch( (pSetupReqPakHD->wValue)&0xff ) + { + case 0: + /* ַ */ + pDescr = MyLangDescrHD; + len = MyLangDescrHD[0]; + break; + + case 1: + /* USBַ */ + pDescr = MyManuInfoHD; + len = MyManuInfoHD[0]; + break; + + case 2: + /* USBƷַ */ + pDescr = MyProdInfoHD; + len = MyProdInfoHD[0]; + break; + + case 3: + /* USBкַ */ + pDescr = MySerNumInfoHD; + len = sizeof( MySerNumInfoHD ); + break; + + default: + errflag = 0xFF; + break; + } + break; + + case USB_DESCR_TYP_REPORT: + /* USB豸 */ + pDescr = MyReportDescHD; + len = sizeof( MyReportDescHD ); + break; + + case USB_DESCR_TYP_QUALIF: + /* 豸޶ */ + pDescr = ( PUINT8 )&MyUSBQUADescHD[ 0 ]; + len = sizeof( MyUSBQUADescHD ); + break; + + case USB_DESCR_TYP_SPEED: + /* ٶ */ + /* ٶ */ + if( USBHD_Dev_Speed == 0x00 ) + { + /* ȫģʽ */ + memcpy( &TAB_USB_FS_OSC_DESC[ 2 ], &MyCfgDescrHD[ 2 ], sizeof( MyCfgDescrHD ) - 2 ); + pDescr = ( PUINT8 )&TAB_USB_FS_OSC_DESC[ 0 ]; + len = sizeof( TAB_USB_FS_OSC_DESC ); + } + else + { + errflag = 0xFF; + } + break; + + case USB_DESCR_TYP_BOS: + /* BOS */ + /* USB2.0豸֧BOS */ + errflag = 0xFF; + break; + + default : + errflag = 0xff; + break; + + } + + if( SetupReqLen>len ) SetupReqLen = len; + len = (SetupReqLen >= DevEP0SIZE) ? DevEP0SIZE : SetupReqLen; + memcpy( pEP0_DataBuf, pDescr, len ); + pDescr += len; + } + break; + + case USB_SET_ADDRESS: + /* õַ */ + SetupReqLen = (pSetupReqPakHD->wValue)&0xff; + break; + + case USB_GET_CONFIGURATION: + /* ȡֵ */ + pEP0_DataBuf[0] = DevConfig; + if ( SetupReqLen > 1 ) SetupReqLen = 1; + break; + + case USB_SET_CONFIGURATION: + /* ֵ */ + DevConfig = (pSetupReqPakHD->wValue)&0xff; + break; + + case USB_CLEAR_FEATURE: + /* */ + if ( ( pSetupReqPakHD->bRequestType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP ) + { + /* ˵ */ + switch( (pSetupReqPakHD->wIndex)&0xff ) + { + case 0x82: + USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL & ~( USBHD_UEP_T_TOG|USBHD_UEP_T_RES_MASK )) | USBHD_UEP_T_RES_NAK; + break; + + case 0x02: + USBOTG_FS->UEP2_RX_CTRL = (USBOTG_FS->UEP2_RX_CTRL & ~( USBHD_UEP_R_TOG|USBHD_UEP_R_RES_MASK )) | USBHD_UEP_R_RES_ACK; + break; + + case 0x81: + USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL & ~( USBHD_UEP_T_TOG|USBHD_UEP_T_RES_MASK )) | USBHD_UEP_T_RES_NAK; + break; + + case 0x01: + USBOTG_FS->UEP1_RX_CTRL = (USBOTG_FS->UEP1_RX_CTRL & ~( USBHD_UEP_R_TOG|USBHD_UEP_R_RES_MASK )) | USBHD_UEP_R_RES_ACK; + break; + + default: + errflag = 0xFF; + break; + + } + } + else errflag = 0xFF; + break; + + case USB_SET_FEATURE: + /* */ + if( ( pMySetupReqPakHD->bRequestType & 0x1F ) == 0x00 ) + { + /* 豸 */ + if( pMySetupReqPakHD->wValue == 0x01 ) + { + if( MyCfgDescrHD[ 7 ] & 0x20 ) + { + /* ûʹܱ־ */ + USBHD_Dev_SleepStatus = 0x01; + } + else + { + errflag = 0xFF; + } + } + else + { + errflag = 0xFF; + } + } + else if( ( pMySetupReqPakHD->bRequestType & 0x1F ) == 0x02 ) + { + /* ö˵ */ + if( pMySetupReqPakHD->wValue == 0x00 ) + { + /* ָ˵STALL */ + switch( ( pMySetupReqPakHD->wIndex ) & 0xff ) + { + case 0x82: + /* ö˵2 IN STALL */ + USBOTG_FS->UEP2_TX_CTRL = ( USBOTG_FS->UEP2_TX_CTRL &= ~USBHD_UEP_T_RES_MASK ) | USBHD_UEP_T_RES_STALL; + //USBHS->UEP2_CTRL = ( USBHS->UEP2_CTRL & ~USBHS_EP_T_RES_MASK ) | USBHS_EP_T_RES_STALL; + break; + + case 0x02: + /* ö˵2 OUT Stall */ + USBOTG_FS->UEP2_RX_CTRL = ( USBOTG_FS->UEP2_RX_CTRL &= ~USBHD_UEP_R_RES_MASK ) | USBHD_UEP_R_RES_STALL; + //USBHS->UEP2_CTRL = ( USBHS->UEP2_CTRL & ~USBHS_EP_R_RES_MASK ) | USBHS_EP_R_RES_STALL; + break; + + case 0x81: + /* ö˵1 IN STALL */ + USBOTG_FS->UEP1_TX_CTRL = ( USBOTG_FS->UEP1_TX_CTRL &= ~USBHD_UEP_T_RES_MASK ) | USBHD_UEP_T_RES_STALL; + //USBHS->UEP1_CTRL = ( USBHS->UEP1_CTRL & ~USBHS_EP_T_RES_MASK ) | USBHS_EP_T_RES_STALL; + break; + + case 0x01: + /* ö˵1 OUT STALL */ + USBOTG_FS->UEP1_RX_CTRL = ( USBOTG_FS->UEP1_RX_CTRL &= ~USBHD_UEP_R_RES_MASK ) | USBHD_UEP_R_RES_STALL; + //USBHS->UEP1_CTRL = ( USBHS->UEP1_CTRL & ~USBHS_EP_R_RES_MASK ) | USBHS_EP_R_RES_STALL; + break; + + default: + errflag = 0xFF; + break; + } + } + else + { + errflag = 0xFF; + } + } + else + { + errflag = 0xFF; + } + break; + + case USB_GET_INTERFACE: + /* ȡӿ */ + pEP0_DataBuf[0] = 0x00; + if ( SetupReqLen > 1 ) SetupReqLen = 1; + break; + + case USB_SET_INTERFACE: + /* ýӿ */ + EP0_DatabufHD[ 0 ] = 0x00; + if( USBHD_Dev_SetupReqLen > 1 ) + { + USBHD_Dev_SetupReqLen = 1; + } + break; + + case USB_GET_STATUS: + /* ݵǰ˵ʵ״̬Ӧ */ + EP0_DatabufHD[ 0 ] = 0x00; + EP0_DatabufHD[ 1 ] = 0x00; + if( pMySetupReqPakHD->wIndex == 0x81 ) + { + if( ( USBOTG_FS->UEP1_TX_CTRL & USBHD_UEP_T_RES_MASK ) == USBHD_UEP_T_RES_STALL ) + { + EP0_DatabufHD[ 0 ] = 0x01; + } + } + else if( pMySetupReqPakHD->wIndex == 0x01 ) + { + if( ( USBOTG_FS->UEP1_RX_CTRL & USBHD_UEP_R_RES_MASK ) == USBHD_UEP_R_RES_STALL ) + { + EP0_DatabufHD[ 0 ] = 0x01; + } + } + else if( pMySetupReqPakHD->wIndex == 0x82 ) + { + if( ( USBOTG_FS->UEP2_TX_CTRL & USBHD_UEP_T_RES_MASK ) == USBHD_UEP_T_RES_STALL ) + { + EP0_DatabufHD[ 0 ] = 0x01; + } + } + else if( pMySetupReqPakHD->wIndex == 0x02 ) + { + if( ( USBOTG_FS->UEP2_RX_CTRL & USBHD_UEP_R_RES_MASK ) == USBHD_UEP_R_RES_STALL ) + { + EP0_DatabufHD[ 0 ] = 0x01; + } + } + if( USBHD_Dev_SetupReqLen > 2 ) + { + USBHD_Dev_SetupReqLen = 2; + } + break; + + default: + errflag = 0xFF; + break; + } + } + if( errflag == 0xff) + { +// printf("uep0 stall\n"); + USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_TOG|USBHD_UEP_T_RES_STALL; + USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_TOG|USBHD_UEP_R_RES_STALL; + } + else + { + if( chtype & 0x80 ) + { + len = (SetupReqLen>DevEP0SIZE) ? DevEP0SIZE : SetupReqLen; + SetupReqLen -= len; + } + else len = 0; + + USBOTG_FS->UEP0_TX_LEN = len; + USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_TOG|USBHD_UEP_T_RES_ACK; + USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_TOG|USBHD_UEP_R_RES_ACK; + } + break; + + case USBHD_UIS_TOKEN_IN: + switch ( USBOTG_FS->INT_ST & ( USBHD_UIS_TOKEN_MASK | USBHD_UIS_ENDP_MASK ) ) + { + case USBHD_UIS_TOKEN_IN: + switch( SetupReqCode ) + { + case USB_GET_DESCRIPTOR: + len = SetupReqLen >= DevEP0SIZE ? DevEP0SIZE : SetupReqLen; + memcpy( pEP0_DataBuf, pDescr, len ); + SetupReqLen -= len; + pDescr += len; + USBOTG_FS->UEP0_TX_LEN = len; + USBOTG_FS->UEP0_TX_CTRL ^= USBHD_UEP_T_TOG; + break; + + case USB_SET_ADDRESS: + USBOTG_FS->DEV_ADDR = (USBOTG_FS->DEV_ADDR&USBHD_UDA_GP_BIT) | SetupReqLen; + USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK; + USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK; + break; + + default: + USBOTG_FS->UEP0_TX_LEN = 0; + USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK; + USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK; + break; + + } + break; + + case USBHD_UIS_TOKEN_IN | 1: + USBOTG_FS->UEP1_TX_CTRL = (USBHD_UEP1_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK; + USBOTG_FS->UEP1_TX_CTRL ^= USBHD_UEP_T_TOG; + break; + + case USBHD_UIS_TOKEN_IN | 2: + USBOTG_FS->UEP2_TX_CTRL ^= USBHD_UEP_T_TOG; + USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK; + break; + + + default : + break; + + } + break; + + case USBHD_UIS_TOKEN_OUT: + + switch ( USBOTG_FS->INT_ST & ( USBHD_UIS_TOKEN_MASK | USBHD_UIS_ENDP_MASK ) ) + { + case USBHD_UIS_TOKEN_OUT: + switch( SetupReqCode ) + { + case 0x20: + if((((LINECODINGST *)pEP0_DataBuf)->dataRat[0] || ((LINECODINGST *)pEP0_DataBuf)->dataRat[1] || + ((LINECODINGST *)pEP0_DataBuf)->dataRat[2] || ((LINECODINGST *)pEP0_DataBuf)->dataRat[3])) + { + + printf( "\nBaud Rate = %d", + (((LINECODINGST *)pEP0_DataBuf)->dataRat[3] <<24) | + (((LINECODINGST *)pEP0_DataBuf)->dataRat[2] <<16) | + (((LINECODINGST *)pEP0_DataBuf)->dataRat[1] <<8) | + (((LINECODINGST *)pEP0_DataBuf)->dataRat[0])); + } + else + { + printf( "\ndataBit = %d", ((LINECODINGST *)pEP0_DataBuf)->dataBit); + printf( "\nstopBit = %d", ((LINECODINGST *)pEP0_DataBuf)->stopBit); + printf( "\nparityType = %d", ((LINECODINGST *)pEP0_DataBuf)->parityType); + + } + break; + } + + + len = USBOTG_FS->RX_LEN; + break; + + case USBHD_UIS_TOKEN_OUT | 1: + if ( USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK ) + { + USBOTG_FS->UEP1_RX_CTRL ^= USBHD_UEP_R_TOG; + len = USBOTG_FS->RX_LEN; +// printf( "point 1 len %d\n", len ); + DevEP1_OUT_Deal( len ); + } + break; + + case USBHD_UIS_TOKEN_OUT | 2: + if ( USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK ) + { + USBOTG_FS->UEP2_RX_CTRL ^= USBHD_UEP_R_TOG; + len = USBOTG_FS->RX_LEN; +// printf( "point 2 len %d\n", len ); + DevEP2_OUT_Deal( len ); + } + break; + } + + break; + + case USBHD_UIS_TOKEN_SOF: + + break; + + default : + break; + + } + + USBOTG_FS->INT_FG = USBHD_UIF_TRANSFER; + } + else if( intflag & USBHD_UIF_BUS_RST ) + { + USBOTG_FS->DEV_ADDR = 0; + + USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK; + USBOTG_FS->UEP1_RX_CTRL = USBHD_UEP_R_RES_ACK; + USBOTG_FS->UEP2_RX_CTRL = USBHD_UEP_R_RES_ACK; + + USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK; + USBOTG_FS->UEP1_TX_CTRL = USBHD_UEP_T_RES_NAK; + USBOTG_FS->UEP2_TX_CTRL = USBHD_UEP_T_RES_NAK; + + USBOTG_FS->INT_FG |= USBHD_UIF_BUS_RST; + } + else if( intflag & USBHD_UIF_SUSPEND ) + { + if ( USBOTG_FS->MIS_ST & USBHD_UMS_SUSPEND ) {;} + else{;} + USBOTG_FS->INT_FG = USBHD_UIF_SUSPEND; + } + else + { + USBOTG_FS->INT_FG = intflag; + } +} diff --git a/libraries/sdk/Peripheral/ch32v30x_usbotg_device.h b/libraries/sdk/Peripheral/ch32v30x_usbotg_device.h new file mode 100644 index 0000000..5952838 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_usbotg_device.h @@ -0,0 +1,746 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_usbotg_device.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* USBOTG firmware library. +*******************************************************************************/ +#ifndef __CH32V30X_USBOTG_DEVICE_H_ +#define __CH32V30X_USBOTG_DEVICE_H_ + +#include "string.h" + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef VOID +#define VOID void +#endif +#ifndef CONST +#define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif + + +/* USB constant and structure define */ + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 /* reserved PID */ +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* Bit define for USB request type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 /* control IN, device to host */ +#define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */ +#define USB_REQ_TYP_READ 0x80 /* control read, device to host */ +#define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */ +#define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */ +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */ +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#endif + +/* USB request type for hub class request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub class feature selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB descriptor type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB device class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB endpoint type and attributes */ +#ifndef USB_ENDP_TYPE_MASK +#define USB_ENDP_DIR_MASK 0x80 +#define USB_ENDP_ADDR_MASK 0x0F +#define USB_ENDP_TYPE_MASK 0x03 +#define USB_ENDP_TYPE_CTRL 0x00 +#define USB_ENDP_TYPE_ISOCH 0x01 +#define USB_ENDP_TYPE_BULK 0x02 +#define USB_ENDP_TYPE_INTER 0x03 +#endif + +#ifndef USB_DEVICE_ADDR +#define USB_DEVICE_ADDR 0x02 +#endif +#ifndef DEFAULT_ENDP0_SIZE +#define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */ +#endif +#ifndef MAX_PACKET_SIZE +#define MAX_PACKET_SIZE 64 /* maximum packet size */ +#endif +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + +#ifndef __PACKED +#define __PACKED __attribute__((packed)) +#endif + +typedef struct __PACKED _USB_SETUP_REQ { + UINT8 bRequestType; + UINT8 bRequest; + UINT16 wValue; + UINT16 wIndex; + UINT16 wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + + +typedef struct __PACKED _USB_DEVICE_DESCR { + UINT8 bLength; + UINT8 bDescriptorType; + UINT16 bcdUSB; + UINT8 bDeviceClass; + UINT8 bDeviceSubClass; + UINT8 bDeviceProtocol; + UINT8 bMaxPacketSize0; + UINT16 idVendor; + UINT16 idProduct; + UINT16 bcdDevice; + UINT8 iManufacturer; + UINT8 iProduct; + UINT8 iSerialNumber; + UINT8 bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + + +typedef struct __PACKED _USB_CONFIG_DESCR { + UINT8 bLength; + UINT8 bDescriptorType; + UINT16 wTotalLength; + UINT8 bNumInterfaces; + UINT8 bConfigurationValue; + UINT8 iConfiguration; + UINT8 bmAttributes; + UINT8 MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + + +typedef struct __PACKED _USB_INTERF_DESCR { + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 bInterfaceNumber; + UINT8 bAlternateSetting; + UINT8 bNumEndpoints; + UINT8 bInterfaceClass; + UINT8 bInterfaceSubClass; + UINT8 bInterfaceProtocol; + UINT8 iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + + +typedef struct __PACKED _USB_ENDPOINT_DESCR { + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 bEndpointAddress; + UINT8 bmAttributes; + UINT16 wMaxPacketSize; + UINT8 bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + + +typedef struct __PACKED _USB_CONFIG_DESCR_LONG { + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[1]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + + +typedef struct __PACKED _USB_HUB_DESCR { + UINT8 bDescLength; + UINT8 bDescriptorType; + UINT8 bNbrPorts; + UINT8 wHubCharacteristicsL; + UINT8 wHubCharacteristicsH; + UINT8 bPwrOn2PwrGood; + UINT8 bHubContrCurrent; + UINT8 DeviceRemovable; + UINT8 PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + + +typedef struct __PACKED _USB_HID_DESCR { + UINT8 bLength; + UINT8 bDescriptorType; + UINT16 bcdHID; + UINT8 bCountryCode; + UINT8 bNumDescriptors; + UINT8 bDescriptorTypeX; + UINT8 wDescriptorLengthL; + UINT8 wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + + +typedef struct __PACKED _UDISK_BOC_CBW {/* command of BulkOnly USB-FlashDisk */ + UINT32 mCBW_Sig; + UINT32 mCBW_Tag; + UINT32 mCBW_DataLen; /* uppest byte of data length, always is 0 */ + UINT8 mCBW_Flag; /* transfer direction and etc. */ + UINT8 mCBW_LUN; + UINT8 mCBW_CB_Len; /* length of command block */ + UINT8 mCBW_CB_Buf[16]; /* command block buffer */ +} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; + + +typedef struct __PACKED _UDISK_BOC_CSW {/* status of BulkOnly USB-FlashDisk */ + UINT32 mCBW_Sig; + UINT32 mCBW_Tag; + UINT32 mCSW_Residue; /* return: remainder bytes */ /* uppest byte of remainder length, always is 0 */ + UINT8 mCSW_Status; /* return: result status */ +} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; + + +/* Ժ궨 */ +#define USE_SYS_CLK 0 +//#define USBHD_HOST 0 +//#define USB_OTG 0 + +/******************************************************************************/ +/* USBOTG_FS DEVICE USB_CONTROL */ +/* BASE USB_CTRL */ +#define USBHD_BASE_CTRL (USBOTG_FS->BASE_CTRL) // USB base control +#define USBHD_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define USBHD_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps +#define USBHD_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable +#define USBHD_UC_SYS_CTRL1 0x20 // USB system control high bit +#define USBHD_UC_SYS_CTRL0 0x10 // USB system control low bit +#define USBHD_UC_SYS_CTRL_MASK 0x30 // bit mask of USB system control +// UC_HOST_MODE & UC_SYS_CTRL1 & UC_SYS_CTRL0: USB system control +// 0 00: disable USB device and disable internal pullup resistance +// 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance +// 0 1x: enable USB device and enable internal pullup resistance +// 1 00: enable USB host and normal status +// 1 01: enable USB host and force UDP/UDM output SE0 state +// 1 10: enable USB host and force UDP/UDM output J state +// 1 11: enable USB host and force UDP/UDM output resume or K state +#define USBHD_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define USBHD_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define USBHD_UC_CLR_ALL 0x02 // force clear FIFO and count of USB +#define USBHD_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB +/* DEVICE USB_CTRL */ +#define USBHD_UDEV_CTRL (USBOTG_FS->UDEV_CTRL) // USB device physical prot control +#define USBHD_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBHD_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBHD_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBHD_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBHD_UD_GP_BIT 0x02 // general purpose bit +#define USBHD_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable +/* USB INT EN */ +#define USBHD_INT_EN (USBOTG_FS->INT_EN) // USB interrupt enable +#define USBHD_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode +#define USBHD_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode +#define USBHD_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow +#define USBHD_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define USBHD_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define USBHD_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion +#define USBHD_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define USBHD_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode +/* USB_DEV_ADDR */ +#define USBHD_DEV_ADDR (USBOTG_FS->DEV_ADDR) // USB device address +#define USBHD_UDA_GP_BIT 0x80 // general purpose bit +#define USBHD_USB_ADDR_MASK 0x7F // bit mask for USB device address +/* USBOTG_FS DEVICE USB_STATUS */ +/* USB_MIS_ST */ +#define USBHD_MIS_ST (USBOTG_FS->MIS_ST) // USB miscellaneous status +#define USBHD_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status +#define USBHD_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host +#define USBHD_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBHD_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) +#define USBHD_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status +#define USBHD_UMS_SUSPEND 0x04 // RO, indicate USB suspend status +#define USBHD_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host +#define USBHD_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host +/* USB_INT_FG */ +#define USBHD_INT_FG (USBOTG_FS->INT_FG) // USB interrupt flag +#define USBHD_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBHD_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBHD_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBHD_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBHD_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBHD_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBHD_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBHD_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBHD_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear +/* USB_INT_ST */ +#define USBHD_INT_ST (USBOTG_FS->INT_ST) // USB interrupt flag +#define USBHD_UIS_IS_SETUP 0x80 // RO, indicate current USB transfer is setup received for USB device mode +#define USBHD_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define USBHD_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBHD_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode +#define USBHD_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode +#define USBHD_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBHD_UIS_TOKEN_OUT 0x00 +#define USBHD_UIS_TOKEN_SOF 0x10 +#define USBHD_UIS_TOKEN_IN 0x20 +#define USBHD_UIS_TOKEN_SETUP 0x30 +// UIS_TOKEN1 & UIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBHD_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +/* USB_RX_LEN */ +#define USBHD_RX_LEN (USBOTG_FS->Rx_Len) // USB receiving length +/* USB_BUF_MOD */ +#define USBHD_UEP4_1_MOD (USBOTG_FS->UEP4_1_MOD) // endpoint 4/1 mode +#define USBHD_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBHD_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBHD_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// UEPn_RX_EN & UEPn_TX_EN & UEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes +// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes +// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes +// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes +#define USBHD_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBHD_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +// UEP4_RX_EN & UEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA +// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes +// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes +// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes + +#define USBHD_UEP2_3_MOD (USBOTG_FS->UEP2_3_MOD) // endpoint 2/3 mode +#define USBHD_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBHD_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBHD_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBHD_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBHD_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBHD_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +#define USBHD_UEP5_6_MOD (USBOTG_FS->UEP5_6_MOD) // endpoint 5/6 mode +#define USBHD_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBHD_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBHD_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBHD_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBHD_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBHD_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +#define USBHD_UEP7_MOD (USBOTG_FS->UEP7_MOD) // endpoint 7 mode +#define USBHD_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBHD_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBHD_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 +/* USB_DMA */ +#define USBHD_UEP0_DMA (USBOTG_FS->UEP0_DMA) // endpoint 0 DMA buffer address +#define USBHD_UEP1_DMA (USBOTG_FS->UEP1_DMA) // endpoint 1 DMA buffer address +#define USBHD_UEP2_DMA (USBOTG_FS->UEP2_DMA) // endpoint 2 DMA buffer address +#define USBHD_UEP3_DMA (USBOTG_FS->UEP3_DMA) // endpoint 3 DMA buffer address +#define USBHD_UEP4_DMA (USBOTG_FS->UEP4_DMA) // endpoint 4 DMA buffer address +#define USBHD_UEP5_DMA (USBOTG_FS->UEP5_DMA) // endpoint 5 DMA buffer address +#define USBHD_UEP6_DMA (USBOTG_FS->UEP6_DMA) // endpoint 6 DMA buffer address +#define USBHD_UEP7_DMA (USBOTG_FS->UEP7_DMA) // endpoint 7 DMA buffer address +/* USB_EP_CTRL */ +#define USBHD_UEP0_T_LEN (USBOTG_FS->UEP0_TX_LEN) // endpoint 0 transmittal length +#define USBHD_UEP0_TX_CTRL (USBOTG_FS->UEP0_TX_CTRL) // endpoint 0 control +#define USBHD_UEP0_RX_CTRL (USBOTG_FS->UEP0_RX_CTRL) // endpoint 0 control + +#define USBHD_UEP1_T_LEN (USBOTG_FS->UEP1_TX_LEN) // endpoint 1 transmittal length +#define USBHD_UEP1_TX_CTRL (USBOTG_FS->UEP1_TX_CTRL) // endpoint 1 control +#define USBHD_UEP1_RX_CTRL (USBOTG_FS->UEP1_RX_CTRL) // endpoint 1 control + +#define USBHD_UEP2_T_LEN (USBOTG_FS->UEP2_TX_LEN) // endpoint 2 transmittal length +#define USBHD_UEP2_TX_CTRL (USBOTG_FS->UEP2_TX_CTRL) // endpoint 2 control +#define USBHD_UEP2_RX_CTRL (USBOTG_FS->UEP2_RX_CTRL) // endpoint 2 control + +#define USBHD_UEP3_T_LEN (USBOTG_FS->UEP3_TX_LEN) // endpoint 3 transmittal length +#define USBHD_UEP3_TX_CTRL (USBOTG_FS->UEP3_TX_CTRL) // endpoint 3 control +#define USBHD_UEP3_RX_CTRL (USBOTG_FS->UEP3_RX_CTRL) // endpoint 3 control + +#define USBHD_UEP4_T_LEN (USBOTG_FS->UEP4_TX_LEN) // endpoint 4 transmittal length +#define USBHD_UEP4_TX_CTRL (USBOTG_FS->UEP4_TX_CTRL) // endpoint 4 control +#define USBHD_UEP4_RX_CTRL (USBOTG_FS->UEP4_RX_CTRL) // endpoint 4 control + +#define USBHD_UEP5_T_LEN (USBOTG_FS->UEP5_TX_LEN) // endpoint 5 transmittal length +#define USBHD_UEP5_TX_CTRL (USBOTG_FS->UEP5_TX_CTRL) // endpoint 5 control +#define USBHD_UEP5_RX_CTRL (USBOTG_FS->UEP5_RX_CTRL) // endpoint 5 control + +#define USBHD_UEP6_T_LEN (USBOTG_FS->UEP6_TX_LEN) // endpoint 6 transmittal length +#define USBHD_UEP6_TX_CTRL (USBOTG_FS->UEP6_TX_CTRL) // endpoint 6 control +#define USBHD_UEP6_RX_CTRL (USBOTG_FS->UEP6_RX_CTRL) // endpoint 6 control + +#define USBHD_UEP7_T_LEN (USBOTG_FS->UEP7_TX_LEN) // endpoint 7 transmittal length +#define USBHD_UEP7_TX_CTRL (USBOTG_FS->UEP7_TX_CTRL) // endpoint 7 control +#define USBHD_UEP7_RX_CTRL (USBOTG_FS->UEP7_RX_CTRL) // endpoint 7 control + +#define USBHD_UEP_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBHD_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBHD_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + +#define USBHD_UEP_R_RES1 0x02 // handshake response type high bit for USB endpoint X receiving (OUT) +#define USBHD_UEP_R_RES0 0x01 // handshake response type low bit for USB endpoint X receiving (OUT) +#define USBHD_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBHD_UEP_R_RES_ACK 0x00 +#define USBHD_UEP_R_RES_TOUT 0x01 +#define USBHD_UEP_R_RES_NAK 0x02 +#define USBHD_UEP_R_RES_STALL 0x03 +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +#define USBHD_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) +#define USBHD_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) +#define USBHD_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBHD_UEP_T_RES_ACK 0x00 +#define USBHD_UEP_T_RES_TOUT 0x01 +#define USBHD_UEP_T_RES_NAK 0x02 +#define USBHD_UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: TALL (error) + +#ifdef USBHD_HOST +/* USBOTG_FS HOST CONTROL&CFG */ +/* HOST USB_CTRL */ +#define USBHD_UHOST_CTRL (USBOTG_FS->UDEV_CTRL) // USB host physical prot control +#define USBHD_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBHD_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBHD_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBHD_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBHD_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBHD_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached +/* USB_INT_ST */ +#define USBHD_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received +/* USB_BUF_MOD */ +#define USBHD_UH_EP_MOD USBHD_UEP2_3_MOD //host endpoint mode +#define USBHD__UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBHD__UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// UH_EP_TX_EN & UH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define USBHD_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBHD_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// UH_EP_RX_EN & UH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes +/* USB_DMA */ +#define USBHD_UH_RX_DMA USBHD_UEP2_DMA // host rx endpoint buffer high address +#define USBHD_UH_TX_DMA USBHD_UEP3_DMA // host tx endpoint buffer high address +/* USB_HOST_SETUP */ +#define USBHD_UH_SETUP (*((PUINT16V)(0x50000036))) // host aux setup +#define USBHD_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub +#define USBHD_UH_SOF_EN 0x04 // USB host automatic SOF enable +#define USBHD_UH_EP_PID USBHD_UEP2_T_LEN // host endpoint and PID +#define USBHD_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBHD_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + +#define USBHD_UH_RX_CTRL USBHD_UEP2_RX_CTRL // host receiver endpoint control +#define USBHD_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBHD_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBHD_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +#define USBHD_UH_RX_CTRL USBHD_UEP2_RX_CTRL // host receiver endpoint control +#define USBHD_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBHD_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBHD_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions +#define USBHD_UH_TX_LEN USBHD_UEP3_T_LEN // host transmittal endpoint transmittal length + +#define USBHD_UH_TX_CTRL USBHD_UEP3_TX_CTRL // host transmittal endpoint control +#define USBHD_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBHD_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define USBHD_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions +#endif +#ifdef USB_OTG +#define USB_OTG_CR (USBOTG_FS->OTG_CR) // usb otg control +#define USB_OTG_CR_SESS 0x20 // usb otg control,Ựƽʹ +#define USB_OTG_CR_VBUS 0x10 // usb otg control,VBUSƽʹ +#define USB_OTG_CR_OTG_EN 0x08 // usb otg control,OTGʹ +#define USB_OTG_CR_IDPU 0x04 // usb otg control,ID +#define USB_OTG_CR_CHARGEVBUS 0x02 // usb otg control,VBUS +#define USB_OTG_CR_DISCHARGEVBUS 0x01 // usb otg control,VBUSŵ + +#define USB_OTG_SR (USBOTG_FS->OTG_CR) // usb otg status +#define USB_OTG_SR_VBUS_VLD 0x01 // usb otg status,A豸VBUSƽЧ +#define USB_OTG_SR_SESS_VLD 0x02 // usb otg status,ỰЧƽЧ־ +#define USB_OTG_SR_SESS_END 0x04 // usb otg status,ỰƽЧ־ +#define USB_OTG_SR_ID_DIG 0x08 // usb otg status,IDƽ +#endif + + +/******************************************************************************/ +/* USBHS PHY Clock Config (RCC_CFGR2) ʹUSBHS PHYʱӵ£ҪõЩ궨 */ +#ifndef USBHS_EXIST +#define USB_48M_CLK_SRC_MASK (1<<31) +#define USB_48M_CLK_SRC_SYS (0<<31) +#define USB_48M_CLK_SRC_PHY (1<<31) + +#define USBHS_PLL_ALIVE (1<<30) + +#define USBHS_PLL_CKREF_MASK (3<<28) +#define USBHS_PLL_CKREF_3M (0<<28) +#define USBHS_PLL_CKREF_4M (1<<28) +#define USBHS_PLL_CKREF_8M (2<<28) +#define USBHS_PLL_CKREF_5M (3<<28) + +#define USBHS_PLL_SRC_MASK (1<<27) +#define USBHS_PLL_SRC_HSE (0<<27) +#define USBHS_PLL_SRC_HSI (1<<27) + +#define USBHS_PLL_SRC_PRE_MASK (7<<24) +#define USBHS_PLL_SRC_PRE_DIV1 (0<<24) +#define USBHS_PLL_SRC_PRE_DIV2 (1<<24) +#define USBHS_PLL_SRC_PRE_DIV3 (2<<24) +#define USBHS_PLL_SRC_PRE_DIV4 (3<<24) +#define USBHS_PLL_SRC_PRE_DIV5 (4<<24) +#define USBHS_PLL_SRC_PRE_DIV6 (5<<24) +#define USBHS_PLL_SRC_PRE_DIV7 (6<<24) + +/* ˵С */ +#define DEF_USB_FS_EP_SIZE 64 +#endif + +/*ʹsysclkʱӵ£ҪõЩ궨 */ +#define RCC_USBFS_CLK_DIV_1 (0<<22) +#define RCC_USBFS_CLK_DIV_2 (1<<22) +#define RCC_USBFS_CLK_DIV_3 (2<<22) +#define RCC_USBFS_CLK_SRC (1<<31) + +/******************************************************************************/ +/* */ +extern PUINT8 pEP0_RAM_Addr; //ep0(64) +extern PUINT8 pEP1_RAM_Addr; //ep1_out(64)+ep1_in(64) +extern PUINT8 pEP2_RAM_Addr; //ep2_out(64)+ep2_in(64) +extern PUINT8 pEP3_RAM_Addr; //ep3_out(64)+ep3_in(64) +extern PUINT8 pEP4_RAM_Addr; //ep4_out(64)+ep4_in(64) +extern PUINT8 pEP5_RAM_Addr; //ep5_out(64)+ep5_in(64) +extern PUINT8 pEP6_RAM_Addr; //ep6_out(64)+ep6_in(64) +extern PUINT8 pEP7_RAM_Addr; //ep7_out(64)+ep7_in(64) + +extern volatile UINT16 USBHD_Endp1_Up_Flag; /* USB2.0豸˵1ϴ״̬: 0:; 1:ϴ; */ +extern volatile UINT8 USBHD_Endp1_Down_Flag; /* USB2.0豸˵1´ɹ־ */ +extern volatile UINT8 USBHD_Endp1_Down_Len; /* USB2.0豸˵1´ */ +extern volatile BOOL USBHD_Endp1_T_Tog; /* USB2.0豸˵1togλת */ +extern volatile BOOL USBHD_Endp1_R_Tog; + +extern volatile UINT16 USBHD_Endp2_Up_Flag; /* USB2.0豸˵2ϴ״̬: 0:; 1:ϴ; */ +extern volatile UINT16 USBHD_Endp2_Up_LoadPtr; /* USB2.0豸˵2ϴװƫ */ +extern volatile UINT8 USBHD_Endp2_Down_Flag; /* USB2.0豸˵2´ɹ־ */ + +/******************************************************************************/ +/* DMAַͻغ궨 */ +#define pSetupReqPakHD ((PUSB_SETUP_REQ)pEP0_RAM_Addr) +#define pEP0_DataBuf (pEP0_RAM_Addr) + +#define pEP1_OUT_DataBuf (pEP1_RAM_Addr) +#define pEP1_IN_DataBuf (pEP1_RAM_Addr+64) + +#define pEP2_OUT_DataBuf (pEP2_RAM_Addr) +#define pEP2_IN_DataBuf (pEP2_RAM_Addr+64) + +/******************************************************************************/ +/* ˵״̬ȡ궨 */ +#define EP1_GetINSta() (R8_UEP1_CTRL&UEP_T_RES_NAK) +#define EP2_GetINSta() (R8_UEP2_CTRL&UEP_T_RES_NAK) +#define EP3_GetINSta() (R8_UEP3_CTRL&UEP_T_RES_NAK) + + +/******************************************************************************/ +/* */ +extern UINT8 EP0_DatabufHD[8]; //ep0(64) +extern UINT8 EP1_DatabufHD[64+64]; //ep1_out(64)+ep1_in(64) +extern UINT8 EP2_DatabufHD[64+64]; //ep2_out(64)+ep2_in(64) ˵ + +extern void DevEP2_IN_Deal( UINT8 l ); +extern void USBOTG_RCC_Init( void ); +extern void USBDeviceInit( void ); +#endif diff --git a/libraries/sdk/Peripheral/ch32v30x_wwdg.c b/libraries/sdk/Peripheral/ch32v30x_wwdg.c new file mode 100644 index 0000000..fad4677 --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_wwdg.c @@ -0,0 +1,139 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_wwdg.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the WWDG firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +**********************************************************************************/ +#include "ch32v30x_wwdg.h" +#include "ch32v30x_rcc.h" + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/libraries/sdk/Peripheral/ch32v30x_wwdg.h b/libraries/sdk/Peripheral/ch32v30x_wwdg.h new file mode 100644 index 0000000..610582f --- /dev/null +++ b/libraries/sdk/Peripheral/ch32v30x_wwdg.h @@ -0,0 +1,42 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_wwdg.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the WWDG +* firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_WWDG_H +#define __CH32V30x_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/libraries/sdk/Startup/startup_ch32v30x_D8C.S b/libraries/sdk/Startup/startup_ch32v30x_D8C.S new file mode 100644 index 0000000..e7c2f4a --- /dev/null +++ b/libraries/sdk/Startup/startup_ch32v30x_D8C.S @@ -0,0 +1,393 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : startup_ch32v30x_D8C.s +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : CH32V307x-CH32V305x vector table for eclipse toolchain. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + + .section .init,"ax",@progbits + .global _start + .align 1 +_start: + j handle_reset + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00100073 + .section .vector,"ax",@progbits + .align 1 +_vector_base: + .option norvc; + .word _start + .word 0 + .word NMI_Handler /* NMI */ + .word HardFault_Handler /* Hard Fault */ + .word 0 + .word Ecall_M_Mode_Handler /* Ecall M Mode */ + .word 0 + .word 0 + .word Ecall_U_Mode_Handler /* Ecall U Mode */ + .word Break_Point_Handler /* Break Point */ + .word 0 + .word 0 + .word SysTick_Handler /* SysTick */ + .word 0 + .word SW_Handler /* SW */ + .word 0 + /* External Interrupts */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word TAMPER_IRQHandler /* TAMPER */ + .word RTC_IRQHandler /* RTC */ + .word FLASH_IRQHandler /* Flash */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line 0 */ + .word EXTI1_IRQHandler /* EXTI Line 1 */ + .word EXTI2_IRQHandler /* EXTI Line 2 */ + .word EXTI3_IRQHandler /* EXTI Line 3 */ + .word EXTI4_IRQHandler /* EXTI Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /* ADC1_2 */ + .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ + .word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ + .word TIM8_UP_IRQHandler /* TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word RNG_IRQHandler /* RNG */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word ETH_IRQHandler /* ETH */ + .word ETH_WKUP_IRQHandler /* ETH WakeUp */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* OTGFS */ + .word USBHSWakeup_IRQHandler /* USBHS Wakeup */ + .word USBHS_IRQHandler /* USBHS */ + .word DVP_IRQHandler /* DVP */ + .word UART6_IRQHandler /* UART6 */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word TIM9_BRK_IRQHandler /* TIM9 Break */ + .word TIM9_UP_IRQHandler /* TIM9 Update */ + .word TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */ + .word TIM9_CC_IRQHandler /* TIM9 Capture Compare */ + .word TIM10_BRK_IRQHandler /* TIM10 Break */ + .word TIM10_UP_IRQHandler /* TIM10 Update */ + .word TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */ + .word TIM10_CC_IRQHandler /* TIM10 Capture Compare */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */ + .word DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */ + .word DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */ + .word DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ + + .option rvc; + + .section .text.vector_handler, "ax", @progbits + .weak NMI_Handler /* NMI */ + .weak HardFault_Handler /* Hard Fault */ + .weak Ecall_M_Mode_Handler /* Ecall M Mode */ + .weak Ecall_U_Mode_Handler /* Ecall U Mode */ + .weak Break_Point_Handler /* Break Point */ + .weak SysTick_Handler /* SysTick */ + .weak SW_Handler /* SW */ + .weak WWDG_IRQHandler /* Window Watchdog */ + .weak PVD_IRQHandler /* PVD through EXTI Line detect */ + .weak TAMPER_IRQHandler /* TAMPER */ + .weak RTC_IRQHandler /* RTC */ + .weak FLASH_IRQHandler /* Flash */ + .weak RCC_IRQHandler /* RCC */ + .weak EXTI0_IRQHandler /* EXTI Line 0 */ + .weak EXTI1_IRQHandler /* EXTI Line 1 */ + .weak EXTI2_IRQHandler /* EXTI Line 2 */ + .weak EXTI3_IRQHandler /* EXTI Line 3 */ + .weak EXTI4_IRQHandler /* EXTI Line 4 */ + .weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .weak ADC1_2_IRQHandler /* ADC1_2 */ + .weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ + .weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ + .weak CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .weak CAN1_SCE_IRQHandler /* CAN1 SCE */ + .weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .weak TIM1_BRK_IRQHandler /* TIM1 Break */ + .weak TIM1_UP_IRQHandler /* TIM1 Update */ + .weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .weak TIM2_IRQHandler /* TIM2 */ + .weak TIM3_IRQHandler /* TIM3 */ + .weak TIM4_IRQHandler /* TIM4 */ + .weak I2C1_EV_IRQHandler /* I2C1 Event */ + .weak I2C1_ER_IRQHandler /* I2C1 Error */ + .weak I2C2_EV_IRQHandler /* I2C2 Event */ + .weak I2C2_ER_IRQHandler /* I2C2 Error */ + .weak SPI1_IRQHandler /* SPI1 */ + .weak SPI2_IRQHandler /* SPI2 */ + .weak USART1_IRQHandler /* USART1 */ + .weak USART2_IRQHandler /* USART2 */ + .weak USART3_IRQHandler /* USART3 */ + .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .weak TIM8_BRK_IRQHandler /* TIM8 Break */ + .weak TIM8_UP_IRQHandler /* TIM8 Update */ + .weak TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .weak TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .weak RNG_IRQHandler /* RNG */ + .weak FSMC_IRQHandler /* FSMC */ + .weak SDIO_IRQHandler /* SDIO */ + .weak TIM5_IRQHandler /* TIM5 */ + .weak SPI3_IRQHandler /* SPI3 */ + .weak UART4_IRQHandler /* UART4 */ + .weak UART5_IRQHandler /* UART5 */ + .weak TIM6_IRQHandler /* TIM6 */ + .weak TIM7_IRQHandler /* TIM7 */ + .weak DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .weak DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .weak DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .weak DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .weak DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .weak ETH_IRQHandler /* ETH */ + .weak ETH_WKUP_IRQHandler /* ETH WakeUp */ + .weak CAN2_TX_IRQHandler /* CAN2 TX */ + .weak CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .weak CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .weak CAN2_SCE_IRQHandler /* CAN2 SCE */ + .weak OTG_FS_IRQHandler /* OTGFS */ + .weak USBHSWakeup_IRQHandler /* USBHS Wakeup */ + .weak USBHS_IRQHandler /* USBHS */ + .weak DVP_IRQHandler /* DVP */ + .weak UART6_IRQHandler /* UART6 */ + .weak UART7_IRQHandler /* UART7 */ + .weak UART8_IRQHandler /* UART8 */ + .weak TIM9_BRK_IRQHandler /* TIM9 Break */ + .weak TIM9_UP_IRQHandler /* TIM9 Update */ + .weak TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */ + .weak TIM9_CC_IRQHandler /* TIM9 Capture Compare */ + .weak TIM10_BRK_IRQHandler /* TIM10 Break */ + .weak TIM10_UP_IRQHandler /* TIM10 Update */ + .weak TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */ + .weak TIM10_CC_IRQHandler /* TIM10 Capture Compare */ + .weak DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .weak DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .weak DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */ + .weak DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */ + .weak DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */ + .weak DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ + +NMI_Handler: 1: j 1b +HardFault_Handler: 1: j 1b +Ecall_M_Mode_Handler: 1: j 1b +Ecall_U_Mode_Handler: 1: j 1b +Break_Point_Handler: 1: j 1b +SysTick_Handler: 1: j 1b +SW_Handler: 1: j 1b +WWDG_IRQHandler: 1: j 1b +PVD_IRQHandler: 1: j 1b +TAMPER_IRQHandler: 1: j 1b +RTC_IRQHandler: 1: j 1b +FLASH_IRQHandler: 1: j 1b +RCC_IRQHandler: 1: j 1b +EXTI0_IRQHandler: 1: j 1b +EXTI1_IRQHandler: 1: j 1b +EXTI2_IRQHandler: 1: j 1b +EXTI3_IRQHandler: 1: j 1b +EXTI4_IRQHandler: 1: j 1b +DMA1_Channel1_IRQHandler: 1: j 1b +DMA1_Channel2_IRQHandler: 1: j 1b +DMA1_Channel3_IRQHandler: 1: j 1b +DMA1_Channel4_IRQHandler: 1: j 1b +DMA1_Channel5_IRQHandler: 1: j 1b +DMA1_Channel6_IRQHandler: 1: j 1b +DMA1_Channel7_IRQHandler: 1: j 1b +ADC1_2_IRQHandler: 1: j 1b +USB_HP_CAN1_TX_IRQHandler: 1: j 1b +USB_LP_CAN1_RX0_IRQHandler: 1: j 1b +CAN1_RX1_IRQHandler: 1: j 1b +CAN1_SCE_IRQHandler: 1: j 1b +EXTI9_5_IRQHandler: 1: j 1b +TIM1_BRK_IRQHandler: 1: j 1b +TIM1_UP_IRQHandler: 1: j 1b +TIM1_TRG_COM_IRQHandler: 1: j 1b +TIM1_CC_IRQHandler: 1: j 1b +TIM2_IRQHandler: 1: j 1b +TIM3_IRQHandler: 1: j 1b +TIM4_IRQHandler: 1: j 1b +I2C1_EV_IRQHandler: 1: j 1b +I2C1_ER_IRQHandler: 1: j 1b +I2C2_EV_IRQHandler: 1: j 1b +I2C2_ER_IRQHandler: 1: j 1b +SPI1_IRQHandler: 1: j 1b +SPI2_IRQHandler: 1: j 1b +USART1_IRQHandler: 1: j 1b +USART2_IRQHandler: 1: j 1b +USART3_IRQHandler: 1: j 1b +EXTI15_10_IRQHandler: 1: j 1b +RTCAlarm_IRQHandler: 1: j 1b +USBWakeUp_IRQHandler: 1: j 1b +TIM8_BRK_IRQHandler: 1: j 1b +TIM8_UP_IRQHandler: 1: j 1b +TIM8_TRG_COM_IRQHandler: 1: j 1b +TIM8_CC_IRQHandler: 1: j 1b +RNG_IRQHandler: 1: j 1b +FSMC_IRQHandler: 1: j 1b +SDIO_IRQHandler: 1: j 1b +TIM5_IRQHandler: 1: j 1b +SPI3_IRQHandler: 1: j 1b +UART4_IRQHandler: 1: j 1b +UART5_IRQHandler: 1: j 1b +TIM6_IRQHandler: 1: j 1b +TIM7_IRQHandler: 1: j 1b +DMA2_Channel1_IRQHandler: 1: j 1b +DMA2_Channel2_IRQHandler: 1: j 1b +DMA2_Channel3_IRQHandler: 1: j 1b +DMA2_Channel4_IRQHandler: 1: j 1b +DMA2_Channel5_IRQHandler: 1: j 1b +ETH_IRQHandler: 1: j 1b +ETH_WKUP_IRQHandler: 1: j 1b +CAN2_TX_IRQHandler: 1: j 1b +CAN2_RX0_IRQHandler: 1: j 1b +CAN2_RX1_IRQHandler: 1: j 1b +CAN2_SCE_IRQHandler: 1: j 1b +OTG_FS_IRQHandler: 1: j 1b +USBHSWakeup_IRQHandler: 1: j 1b +USBHS_IRQHandler: 1: j 1b +DVP_IRQHandler: 1: j 1b +UART6_IRQHandler: 1: j 1b +UART7_IRQHandler: 1: j 1b +UART8_IRQHandler: 1: j 1b +TIM9_BRK_IRQHandler: 1: j 1b +TIM9_UP_IRQHandler: 1: j 1b +TIM9_TRG_COM_IRQHandler: 1: j 1b +TIM9_CC_IRQHandler: 1: j 1b +TIM10_BRK_IRQHandler: 1: j 1b +TIM10_UP_IRQHandler: 1: j 1b +TIM10_TRG_COM_IRQHandler: 1: j 1b +TIM10_CC_IRQHandler: 1: j 1b +DMA2_Channel6_IRQHandler: 1: j 1b +DMA2_Channel7_IRQHandler: 1: j 1b +DMA2_Channel8_IRQHandler: 1: j 1b +DMA2_Channel9_IRQHandler: 1: j 1b +DMA2_Channel10_IRQHandler: 1: j 1b +DMA2_Channel11_IRQHandler: 1: j 1b + + + .section .text.handle_reset,"ax",@progbits + .weak handle_reset + .align 1 +handle_reset: +.option push +.option norelax + la gp, __global_pointer$ +.option pop +1: + la sp, _eusrstack +2: + /* Load data section from flash to RAM */ + la a0, _data_lma + la a1, _data_vma + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: + /* Clear bss section */ + la a0, _sbss + la a1, _ebss + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: + li t0, 0x1f + csrw 0xbc0, t0 + + /* Enable nested and hardware stack */ + /* 8жǶ */ + li t0, 0x1f + csrw 0x804, t0 + + /* Enable floating point and interrupt */ + /* ʹûģʽ */ + li t0, 0x6088 + /* + ʹܻģʽ + li t0, 0x7888 + */ + csrs mstatus, t0 + + la t0, _vector_base + ori t0, t0, 3 + csrw mtvec, t0 + + #jal SystemInit + la t0, main + csrw mepc, t0 + mret + + diff --git a/libraries/zf_common/zf_common_clock.c b/libraries/zf_common/zf_common_clock.c new file mode 100644 index 0000000..f72bcf8 --- /dev/null +++ b/libraries/zf_common/zf_common_clock.c @@ -0,0 +1,167 @@ +/********************************************************************************************************************* + * CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ + * Copyright (c) 2022 SEEKFREE ɿƼ + * + * ļCH32V307VCT6 Դһ + * + * CH32V307VCT6 Դ + * Ըᷢ GPLGNU General Public License GNUͨù֤ + * GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ + * + * Դķϣܷãδκεı֤ + * ûԻʺض;ı֤ + * ϸμ GPL + * + * ӦյԴͬʱյһ GPL ĸ + * ûУ + * + * ע + * Դʹ GPL3.0 Դ֤Э Ϊİ汾 + * Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ + * ֤ libraries ļ ļµ LICENSE ļ + * ӭλʹò ޸ʱ뱣ɿƼİȨ + * + * ļ zf_common_clock + * ˾ ɶɿƼ޹˾ + * 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ + * MounRiver Studio V1.8.1 + * ƽ̨ CH32V307VCT6 + * https://seekfree.taobao.com/ + * + * ޸ļ¼ + * ע + * 2022-09-15 W first version + ********************************************************************************************************************/ + +#include "ch32v30x.h" +#include "zf_common_function.h" +#include "zf_common_interrupt.h" + +#include "zf_common_clock.h" + +uint32 system_clock = SYSTEM_CLOCK_144M; // ϵͳʱϢ + +//------------------------------------------------------------------------------------------------------------------- +// ʱӻָʼ ڲ +// ˵ void +// ز void +//------------------------------------------------------------------------------------------------------------------- +void clock_reset(void) +{ + RCC->CTLR |= (uint32) 0x00000001; //ʹHSI + RCC->CFGR0 &= (uint32) 0xF8FF0000; + RCC->CTLR &= (uint32) 0xFEF6FFFF; + RCC->CTLR &= (uint32) 0xFFFBFFFF; + RCC->CFGR0 &= (uint32) 0xFF80FFFF; + RCC->INTR = (uint32) 0x009F0000; // жϲλ +} + +//------------------------------------------------------------------------------------------------------------------- +// ʱ +// ˵ clock ʱƵ Ƽʹ zf_common_clock.h system_clock_enum ѡ +// ز void +//------------------------------------------------------------------------------------------------------------------- +void clock_set_freq(uint32 clock) +{ + clock_reset(); + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t) RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t) 0x01; + } + else + { + HSEStatus = (uint32_t) 0x00; + } + + if (HSEStatus == (uint32_t) 0x01) + { + +// /* Enable Prefetch Buffer */ +// FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; ((uint8_t)0x10) +// +// /* Flash 2 wait state */ +// FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); ((uint8_t)0x03) +// FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; ((uint8_t)0x02) + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t) RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t) RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t) RCC_PPRE1_DIV1; + + /* PLL configuration: PLLCLK = HSE * ? = ? MHz */ + RCC->CFGR0 &= (uint32) ((uint32) ~(RCC_PLLSRC | RCC_PLLXTPRE + | RCC_PLLMULL)); + + if (clock == SYSTEM_CLOCK_144M) + RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE + | RCC_PLLMULL18_EXTEN); + else if (clock == SYSTEM_CLOCK_120M) + RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE + | RCC_PLLMULL15_EXTEN); + else if (clock == SYSTEM_CLOCK_96M) + RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE + | RCC_PLLMULL12_EXTEN); + else if (clock == SYSTEM_CLOCK_72M) + RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE + | RCC_PLLMULL9_EXTEN); + else if (clock == SYSTEM_CLOCK_48M) + RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE + | RCC_PLLMULL6_EXTEN); + else if (clock == SYSTEM_CLOCK_24M) + RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE + | RCC_PLLMULL3_EXTEN); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t) ((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t) RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + while(1); + // ⲿȶȱʧ ʱʧ + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +//------------------------------------------------------------------------------------------------------------------- +// ʱӳʼ +// ˵ clock ʱƵ Ƽʹ zf_common_clock.h system_clock_enum ѡ +// ز void +// ʹʾ clock_init(SYSTEM_CLOCK_144M); // ʼʱΪ 144MHz +//------------------------------------------------------------------------------------------------------------------- +void clock_init(uint32 clock) +{ + + system_clock = clock; // ¼ʱƵ + clock_reset(); + clock_set_freq(clock); + + interrupt_init(); + + +} diff --git a/libraries/zf_common/zf_common_clock.h b/libraries/zf_common/zf_common_clock.h new file mode 100644 index 0000000..82ac500 --- /dev/null +++ b/libraries/zf_common/zf_common_clock.h @@ -0,0 +1,61 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_common_clock +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + + +#ifndef _zf_common_clock_h_ +#define _zf_common_clock_h_ + +#include "ch32v30x.h" +#include "zf_common_typedef.h" + +#define BOARD_XTAL_FREQ 8000000 // Ƶ ԼõIJƵʾ޸ UM 巶ΧΪ 4-24Mhz +//#define XTAL_STARTUP_TIMEOUT 0x0800 // ȴʱʱ + +typedef enum +{ + SYSTEM_CLOCK_XTAL = BOARD_XTAL_FREQ, // ʹþƵΪʱƵ + SYSTEM_CLOCK_24M = 24000000, // 24Mhz + SYSTEM_CLOCK_48M = 48000000, // 48Mhz + SYSTEM_CLOCK_72M = 72000000, // 72Mhz + SYSTEM_CLOCK_96M = 96000000, // 96Mhz + SYSTEM_CLOCK_120M = 120000000, // 120Mhz + SYSTEM_CLOCK_144M = 144000000, // 144Mhz +}system_clock_enum; + +extern uint32 system_clock; // ȫֱ ϵͳʱϢ +void clock_reset(void); +void clock_init (uint32 clock); // ʱӳʼ +void clock_set_freq(uint32 clock); // ϵͳƵ +#endif diff --git a/libraries/zf_common/zf_common_debug.c b/libraries/zf_common/zf_common_debug.c new file mode 100644 index 0000000..3eb82d7 --- /dev/null +++ b/libraries/zf_common/zf_common_debug.c @@ -0,0 +1,471 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_common_debug +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + + +#include "zf_driver_uart.h" +#include "zf_common_interrupt.h" +#include "zf_common_fifo.h" + +#include "zf_common_debug.h" + +#if DEBUG_UART_USE_INTERRUPT // debug uart ж +uint8 debug_uart_buffer[DEBUG_RING_BUFFER_LEN]; // ݴ +uint8 debug_uart_data; +#endif + +fifo_struct debug_uart_fifo; + +static debug_output_struct debug_output_info; +static volatile uint8 zf_debug_init_flag = 0; +static volatile uint8 zf_debug_assert_enable = 1; + +//------------------------------------------------------------------------------------------------------------------- +// debug ʱ 120MHz һʱ ƬҪݸʱ +// ˵ pass жǷ񴥷 +// ˵ *file ļ +// ˵ line Ŀ +// ز void +//------------------------------------------------------------------------------------------------------------------- +static void debug_delay (void) +{ + vuint32 loop_1 = 0, loop_2 = 0; + for(loop_1 = 0; loop_1 <= 0xFF; loop_1 ++) + for(loop_2 = 0; loop_2 <= 0xFFFF; loop_2 ++) + __NOP(); +} + + +//------------------------------------------------------------------------------------------------------------------- +// debug ҪǷֹԺźάֶӲʧ +// ˵ void +// ز void +// ʹʾ debug_protective_handler(); +// עϢ ļڲ ûùע Ҳ޸ +//------------------------------------------------------------------------------------------------------------------- +static void debug_protective_handler (void) +{ + // δ +} + +//------------------------------------------------------------------------------------------------------------------- +// debug ӿ ˲ֲû +// ˵ *str Ҫַ +// ز void +// ʹʾ debug_uart_str_output("Log message"); +// עϢ ļڲ ûùע Ҳ޸ +//------------------------------------------------------------------------------------------------------------------- +static void debug_uart_str_output (const char *str) +{ + uart_write_string(DEBUG_UART_INDEX, str); +} + +//------------------------------------------------------------------------------------------------------------------- +// debug ӿ +// ˵ *type log +// ˵ *file ļ +// ˵ line Ŀ +// ˵ *str Ϣ +// ز void +// ʹʾ debug_output("Log message", file, line, str); +// עϢ ļڲ ûùע Ҳ޸ +//------------------------------------------------------------------------------------------------------------------- +static void debug_output (char *type, char *file, int line, char *str) +{ + char *file_str; + vuint16 i = 0, j = 0; + vint16 len_origin = 0; + vint16 show_len = 0; + vint16 show_line_index = 0; + len_origin = strlen(file); + + char output_buffer[256]; + char file_path_buffer[64]; + + if(debug_output_info.type_index) + { + debug_output_info.output_screen_clear(); + } + + if(zf_debug_init_flag) + { + if(debug_output_info.type_index) + { + // Ҫнļ· + // <· ֻһĿ¼ src/main.c> + // line : xxxx + debug_output_info.output_screen(0, show_line_index ++, type); + + file_str = file; + len_origin = strlen(file); + show_len = (debug_output_info.display_x_max / debug_output_info.font_x_size); + + while(*file_str++ != '\0'); + + // ֻȡһĿ¼ ļ̷Ŀ¼ MDK Ĺ̸Ŀ¼ ͻֱǰĿ¼ + for(j = 0; (j < 2) && (len_origin >= 0); len_origin --) // '/' + { + file_str --; + if((*file_str == '/') || (*file_str == 0x5C)) + { + j ++; + } + } + + // ļ·浽 + if(len_origin >= 0) + { + file_str ++; + sprintf(output_buffer, "file: %s", file_str); + } + else + { + if(0 == j) + { + sprintf(output_buffer, "file: mdk/%s", file_str); + } + else + { + sprintf(output_buffer, "file: %s", file_str); + } + } + + // Ļʾ· + for(i = 0; i < ((strlen(output_buffer) / show_len) + 1); i ++) + { + for(j = 0; j < show_len; j ++) + { + if(strlen(output_buffer) < (j + i * show_len)) + { + break; + } + file_path_buffer[j] = output_buffer[j + i * show_len]; + } + + file_path_buffer[j] = '\0'; // ĩβ\0 + + debug_output_info.output_screen(0, debug_output_info.font_y_size * show_line_index ++, file_path_buffer); + } + + // Ļʾк + sprintf(output_buffer, "line: %d", line); + debug_output_info.output_screen(0, debug_output_info.font_y_size * show_line_index ++, output_buffer); + + // Ļʾ Log еĻ + if(NULL != str) + { + for(i = 0; i < ((strlen(str) / show_len) + 1); i ++) + { + for(j = 0; j < show_len; j ++) + { + if(strlen(str) < (j + i * show_len)) + { + break; + } + file_path_buffer[j] = str[j + i * show_len]; + } + + file_path_buffer[j] = '\0'; // ĩβ\0 + + debug_output_info.output_screen(0, debug_output_info.font_y_size * show_line_index ++, file_path_buffer); + } + } + } + else + { + char output_buffer[256]; + memset(output_buffer, 0, 256); + debug_output_info.output_uart(type); + if(NULL != str) + { + sprintf(output_buffer, "\r\nfile %s line %d: %s.\r\n", file, line, str); + } + else + { + sprintf(output_buffer, "\r\nfile %s line %d.\r\n", file, line); + } + debug_output_info.output_uart(output_buffer); + } + } +} + + +//------------------------------------------------------------------------------------------------------------------- +// Դڷͻ +// ˵ *buff ݴŵָ +// ˵ len Ҫ͵ij +// ز uint32 ʣδ͵ij +// ʹʾ +// עϢ Ҫ DEBUG_UART_USE_INTERRUPT 궨ſʹ +//------------------------------------------------------------------------------------------------------------------- +uint32 debug_send_buffer(const uint8 *buff, uint32 len) +{ + uart_write_buffer(DEBUG_UART_INDEX, buff, len); + return 0; +} + + + +//------------------------------------------------------------------------------------------------------------------- +// ȡ debug λ +// ˵ *buff ݴŵָ +// ˵ len Ҫȡij +// ز uint32 ݵʵʳ +// ʹʾ +// עϢ Ҫ DEBUG_UART_USE_INTERRUPT 궨ſʹ +//------------------------------------------------------------------------------------------------------------------- +uint32 debug_read_ring_buffer (uint8 *buff, uint32 len) +{ + fifo_read_buffer(&debug_uart_fifo, buff, &len, FIFO_READ_AND_CLEAN); + return len; +} + +#if DEBUG_UART_USE_INTERRUPT // ֻôжϲű +//------------------------------------------------------------------------------------------------------------------- +// debug жϴ isr.c жӦжϷ +// ˵ void +// ز void +// ʹʾ debug_interrupr_handler(); +// עϢ Ҫ DEBUG_UART_USE_INTERRUPT 궨ſʹ +// ұĬϷ UART1 Ĵڽжϴ +//------------------------------------------------------------------------------------------------------------------- +void debug_interrupr_handler (void) +{ + if(zf_debug_init_flag) + { + uart_query_byte(DEBUG_UART_INDEX, &debug_uart_data); // ȡ + fifo_write_buffer(&debug_uart_fifo, &debug_uart_data, 1); // FIFO + } +} + +#endif + +//------------------------------------------------------------------------- // printf ض ˲ֲû +//------------------------------------------------------------------------------------------------------------------- +// printfض +// ˵ void +// ز void +// @since v1.0 +// עϢ ضprintfDEBUG +//------------------------------------------------------------------------------------------------------------------- +#if (1 == PRINTF_ENABLE) +int _write(int fd, char *buf, int size) +{ + int i; + for(i=0; itype_index = 0; + + info->display_x_max = 0xFFFF; + info->display_y_max = 0xFFFF; + + info->font_x_size = 0xFF; + info->font_y_size = 0xFF; + + info->output_uart = NULL; + info->output_screen = NULL; + info->output_screen_clear = NULL; +} + +//------------------------------------------------------------------------------------------------------------------- +// debug 󶨳ʼ ˲ֲû +// ˵ *info debug Ϣṹ +// ز void +// ʹʾ debug_output_init(info); +// עϢ һ㲻û +//------------------------------------------------------------------------------------------------------------------- +void debug_output_init (debug_output_struct *info) +{ + debug_output_info.type_index = info->type_index; + + debug_output_info.display_x_max = info->display_x_max; + debug_output_info.display_y_max = info->display_y_max; + + debug_output_info.font_x_size = info->font_x_size; + debug_output_info.font_y_size = info->font_y_size; + + debug_output_info.output_uart = info->output_uart; + debug_output_info.output_screen = info->output_screen; + debug_output_info.output_screen_clear = info->output_screen_clear; + + zf_debug_init_flag = 1; +} + +//------------------------------------------------------------------------------------------------------------------- +// debug ڳʼ ˲ֲû +// ˵ void +// ز void +// ʹʾ debug_init(); +// עϢ ԴʾĬϵ ĬϽжϽ +//------------------------------------------------------------------------------------------------------------------- +void debug_init (void) +{ + debug_output_struct info; + debug_output_struct_init(&info); + info.output_uart = debug_uart_str_output; + debug_output_init(&info); + + uart_init( + DEBUG_UART_INDEX, // zf_common_debug.h в鿴Ӧֵ + DEBUG_UART_BAUDRATE, // zf_common_debug.h в鿴Ӧֵ + DEBUG_UART_TX_PIN, // zf_common_debug.h в鿴Ӧֵ + DEBUG_UART_RX_PIN); // zf_common_debug.h в鿴Ӧֵ + +#if DEBUG_UART_USE_INTERRUPT // ֻôжϲű + fifo_init(&debug_uart_fifo, FIFO_DATA_8BIT, debug_uart_buffer, DEBUG_RING_BUFFER_LEN); + uart_rx_interrupt(DEBUG_UART_INDEX, 1); // ʹܶӦڽж +#endif +} + + + + diff --git a/libraries/zf_common/zf_common_debug.h b/libraries/zf_common/zf_common_debug.h new file mode 100644 index 0000000..047eab5 --- /dev/null +++ b/libraries/zf_common/zf_common_debug.h @@ -0,0 +1,106 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_common_debug +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_common_debug_h_ +#define _zf_common_debug_h_ + +#include "zf_common_typedef.h" +#define PRINTF_ENABLE (1) // ʹprintf + +// ޸Ĵڲ debug UART жϽ Ҫͬ debug_interrupr_handler ӦжϷ +// ޸Ĵڲ debug UART жϽ Ҫͬ debug_interrupr_handler ӦжϷ +// ޸Ĵڲ debug UART жϽ Ҫͬ debug_interrupr_handler ӦжϷ +#define DEBUG_UART_INDEX (UART_3) // ָ debug uart ʹõĵĴ +#define DEBUG_UART_BAUDRATE (115200) // ָ debug uart ʹõĵĴڲ +#define DEBUG_UART_TX_PIN (UART3_MAP0_TX_B10 ) // ָ debug uart ʹõĵĴ +#define DEBUG_UART_RX_PIN (UART3_MAP0_RX_B11 ) // ָ debug uart ʹõĵĴ + +#define DEBUG_UART_USE_INTERRUPT (1) // Ƿ debug uart ж + +//------------------------------------------------------------------------------------------------------------------- +// +// ˵ x жǷ񴥷 0- 1- +// ز void +// ʹʾ zf_assert(0); +// עϢ һڲж zf_assert(0) ͶԱ +// Ĭ» Debug UART +// ʹÿԴĻӿڳʼĻ Ļʾ +//------------------------------------------------------------------------------------------------------------------- +#define zf_assert(x) (debug_assert_handler((x), __FILE__, __LINE__)) + +//------------------------------------------------------------------------------------------------------------------- +// Log Ϣ +// ˵ x жǷ񴥷 0- 1- +// ˵ *str Ҫ Log Ϣ +// ز void +// ʹʾ zf_log(0, "Error"); +// עϢ Ϣ һЩ߾֮ +// Ĭ» Debug UART +// ʹÿԴĻӿڳʼĻ Ļʾ +//------------------------------------------------------------------------------------------------------------------- +#define zf_log(x, str) (debug_log_handler((x), (str), __FILE__, __LINE__)) + + +typedef struct +{ + uint16 type_index; + + uint16 display_x_max; + uint16 display_y_max; + + uint8 font_x_size; + uint8 font_y_size; + + void (*output_uart) (const char *str); + void (*output_screen) (uint16 x, uint16 y, const char *str); + void (*output_screen_clear) (void); +}debug_output_struct; + +uint32 debug_send_buffer(const uint8 *buff, uint32 len); +#if DEBUG_UART_USE_INTERRUPT // debug uart ж +#define DEBUG_RING_BUFFER_LEN (64) // 廷λС Ĭ 64byte +void debug_interrupr_handler (void); +#endif + +uint32 debug_read_ring_buffer(uint8 *buff, uint32 len); +void debug_assert_enable (void); +void debug_assert_disable (void); +void debug_assert_handler (uint8 pass, char *file, int line); +void debug_log_handler (uint8 pass, char *str, char *file, int line); +void debug_output_struct_init (debug_output_struct *info); +void debug_output_init (debug_output_struct *info); +void debug_init (void); + +#endif diff --git a/libraries/zf_common/zf_common_fifo.c b/libraries/zf_common/zf_common_fifo.c new file mode 100644 index 0000000..7021b67 --- /dev/null +++ b/libraries/zf_common/zf_common_fifo.c @@ -0,0 +1,554 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_common_fifo +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "zf_common_debug.h" +#include "zf_common_fifo.h" + +//------------------------------------------------------------------------------------------------------------------- +// FIFO ͷָλ +// ˵ *fifo FIFO ָ +// ˵ offset ƫ +// ز void +// ʹʾ fifo_head_offset(fifo, 1); +// עϢ ļڲ ûùע Ҳ޸ +//------------------------------------------------------------------------------------------------------------------- +static void fifo_head_offset (fifo_struct *fifo, uint32 offset) +{ + fifo->head += offset; + + while(fifo->max <= fifo->head) // ΧС ֱС󻺳С + { + fifo->head -= fifo->max; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// FIFO βָλ +// ˵ *fifo FIFO ָ +// ˵ offset ƫ +// ز void +// ʹʾ fifo_end_offset(fifo, 1); +// עϢ ļڲ ûùע Ҳ޸ +//------------------------------------------------------------------------------------------------------------------- +static void fifo_end_offset (fifo_struct *fifo, uint32 offset) +{ + fifo->end += offset; + + while(fifo->max <= fifo->end) // ΧС ֱС󻺳С + { + fifo->end -= fifo->max; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// FIFO û +// ˵ *fifo FIFO ָ +// ز void +// ʹʾ fifo_clear(fifo); +// עϢ յǰ FIFO ڴ +//------------------------------------------------------------------------------------------------------------------- +fifo_state_enum fifo_clear (fifo_struct *fifo) +{ + zf_assert(fifo != NULL); + fifo_state_enum return_state = FIFO_SUCCESS; + do + { + if(FIFO_CLEAR & fifo->execution) + { + return_state = FIFO_CLEAR_UNDO; + break; + } + fifo->execution |= FIFO_CLEAR; + fifo->head = 0; + fifo->end = 0; + fifo->size = fifo->max; + switch(fifo->type) + { + case FIFO_DATA_8BIT: + memset(fifo->buffer, 0, fifo->max); + break; + case FIFO_DATA_16BIT: + memset(fifo->buffer, 0, fifo->max * 2); + break; + case FIFO_DATA_32BIT: + memset(fifo->buffer, 0, fifo->max * 4); + break; + } +// memset(fifo->buffer, 0, fifo->max); + fifo->execution &= ~FIFO_CLEAR; + }while(0); + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// FIFO ѯǰݸ +// ˵ *fifo FIFO ָ +// ز uint32 ʹó +// ʹʾ uint32 len = fifo_used(fifo); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 fifo_used (fifo_struct *fifo) +{ + zf_assert(fifo != NULL); + return (fifo->max - fifo->size); +} + +//------------------------------------------------------------------------------------------------------------------- +// FIFO д +// ˵ *fifo FIFO ָ +// ˵ dat +// ز fifo_state_enum ״̬ +// ʹʾ zf_log(fifo_write_element(&fifo, data) == FIFO_SUCCESS, "fifo_write_byte error"); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +fifo_state_enum fifo_write_element (fifo_struct *fifo, uint32 dat) +{ + zf_assert(fifo != NULL); + fifo_state_enum return_state = FIFO_SUCCESS; + + do + { + if(FIFO_WRITE & fifo->execution) + { + return_state = FIFO_WRITE_UNDO; + break; + } + fifo->execution |= FIFO_WRITE; + + if(1 <= fifo->size) // ʣռ㹻װ± + { + switch(fifo->type) + { + case FIFO_DATA_8BIT: + ((uint8 *)fifo->buffer)[fifo->head] = dat; + break; + case FIFO_DATA_16BIT: + ((uint16 *)fifo->buffer)[fifo->head] = dat; + break; + case FIFO_DATA_32BIT: + ((uint32 *)fifo->buffer)[fifo->head] = dat; + break; + } + fifo_head_offset(fifo, 1); // ͷָƫ + fifo->size -= 1; // ʣ೤ȼС + } + else + { + return_state = FIFO_SPACE_NO_ENOUGH; + } + fifo->execution &= ~FIFO_WRITE; + }while(0); + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// FIFO д +// ˵ *fifo FIFO ָ +// ˵ *dat Դָ +// ˵ length Ҫдݳ +// ز fifo_state_enum ״̬ +// ʹʾ zf_log(fifo_write_buffer(&fifo, data, 32) == FIFO_SUCCESS, "fifo_write_buffer error"); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +fifo_state_enum fifo_write_buffer (fifo_struct *fifo, void *dat, uint32 length) +{ + zf_assert(fifo != NULL); + fifo_state_enum return_state = FIFO_SUCCESS; + uint32 temp_length = 0; + + do + { + if(NULL == dat) + { + return_state = FIFO_BUFFER_NULL; + break; + } + if(FIFO_WRITE & fifo->execution) + { + return_state = FIFO_WRITE_UNDO; + break; + } + fifo->execution |= FIFO_WRITE; + + if(length <= fifo->size) // ʣռ㹻װ± + { + temp_length = fifo->max - fifo->head; // ͷָ뻺βжٿռ + + if(length > temp_length) // 뻺βȲд λֶβ + { + switch(fifo->type) + { + case FIFO_DATA_8BIT: + memcpy( + &(((uint8 *)fifo->buffer)[fifo->head]), + dat, temp_length); // һ + fifo_head_offset(fifo, temp_length); // ͷָƫ + memcpy( + &(((uint8 *)fifo->buffer)[fifo->head]), + &(((uint8 *)dat)[temp_length]), + length - temp_length); // ڶ + fifo_head_offset(fifo, length - temp_length); // ͷָƫ + break; + case FIFO_DATA_16BIT: + memcpy( + &(((uint16 *)fifo->buffer)[fifo->head]), + dat, temp_length * 2); // һ + fifo_head_offset(fifo, temp_length); // ͷָƫ + memcpy( + &(((uint16 *)fifo->buffer)[fifo->head]), + &(((uint16 *)dat)[temp_length]), + (length - temp_length) * 2); // ڶ + fifo_head_offset(fifo, length - temp_length); // ͷָƫ + break; + case FIFO_DATA_32BIT: + memcpy( + &(((uint32 *)fifo->buffer)[fifo->head]), + dat, temp_length * 4); // һ + fifo_head_offset(fifo, temp_length); // ͷָƫ + memcpy( + &(((uint32 *)fifo->buffer)[fifo->head]), + &(((uint32 *)dat)[temp_length]), + (length - temp_length) * 4); // ڶ + fifo_head_offset(fifo, length - temp_length); // ͷָƫ + break; + } + } + else + { + switch(fifo->type) + { + case FIFO_DATA_8BIT: + memcpy( + &(((uint8 *)fifo->buffer)[fifo->head]), + dat, length); // һд + fifo_head_offset(fifo, length); // ͷָƫ + break; + case FIFO_DATA_16BIT: + memcpy( + &(((uint16 *)fifo->buffer)[fifo->head]), + dat, length * 2); // һд + fifo_head_offset(fifo, length); // ͷָƫ + break; + case FIFO_DATA_32BIT: + memcpy( + &(((uint32 *)fifo->buffer)[fifo->head]), + dat, length * 4); // һд + fifo_head_offset(fifo, length); // ͷָƫ + break; + } +// memcpy(&fifo->buffer[fifo->head], dat, length); // һд +// fifo_head_offset(fifo, length); // ͷָƫ + } + + fifo->size -= length; // ʣ೤ȼС + } + else + { + return_state = FIFO_SPACE_NO_ENOUGH; + } + fifo->execution &= ~FIFO_WRITE; + }while(0); + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// FIFO ȡ +// ˵ *fifo FIFO ָ +// ˵ *dat Ŀ껺ָ +// ˵ flag Ƿ FIFO ״̬ ѡǷնȡ +// ز fifo_state_enum ״̬ +// ʹʾ zf_log(fifo_read_element(&fifo, data, FIFO_READ_ONLY) == FIFO_SUCCESS, "fifo_read_byte error"); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +fifo_state_enum fifo_read_element (fifo_struct *fifo, void *dat, fifo_operation_enum flag) +{ + zf_assert(fifo != NULL); + fifo_state_enum return_state = FIFO_SUCCESS; + + do + { + if(NULL == dat) + { + return_state = FIFO_BUFFER_NULL; + break; + } + fifo->execution |= FIFO_READ; + + if(1 > fifo_used(fifo)) + { + return_state = FIFO_DATA_NO_ENOUGH; // ־ݲ + } + + switch(fifo->type) + { + case FIFO_DATA_8BIT: + *((uint8 *)dat) = ((uint8 *)fifo->buffer)[fifo->end]; + break; + case FIFO_DATA_16BIT: + *((uint16 *)dat) = ((uint16 *)fifo->buffer)[fifo->end]; + break; + case FIFO_DATA_32BIT: + *((uint32 *)dat) = ((uint32 *)fifo->buffer)[fifo->end]; + break; + } + + if(flag == FIFO_READ_AND_CLEAN) // ѡȡ FIFO ״̬ + { + if(FIFO_CLEAR & fifo->execution) + { + return_state = FIFO_CLEAR_UNDO; + break; + } + fifo->execution |= FIFO_CLEAR; + fifo_end_offset(fifo, 1); // ƶ FIFO ͷָ + fifo->size += 1; + fifo->execution &= ~FIFO_CLEAR; + } + }while(0); + fifo->execution &= FIFO_READ; + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// FIFO ȡ +// ˵ *fifo FIFO ָ +// ˵ *dat Ŀ껺ָ +// ˵ *length ȡݳ ûôᱻ޸ +// ˵ flag Ƿ FIFO ״̬ ѡǷնȡ +// ز fifo_state_enum ״̬ +// ʹʾ zf_log(fifo_read_buffer(&fifo, data, &length, FIFO_READ_ONLY) == FIFO_SUCCESS, "fifo_read_buffer error"); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +fifo_state_enum fifo_read_buffer (fifo_struct *fifo, void *dat, uint32 *length, fifo_operation_enum flag) +{ + zf_assert(fifo != NULL); + zf_assert(length != NULL); + fifo_state_enum return_state = FIFO_SUCCESS; + uint32 temp_length; + uint32 fifo_data_length; + + do + { + if(NULL == dat) + { + return_state = FIFO_BUFFER_NULL; + break; + } + fifo->execution |= FIFO_READ; + + fifo_data_length = fifo_used(fifo); + + if(*length > fifo_data_length) + { + *length = fifo_data_length; // ȡij + return_state = FIFO_DATA_NO_ENOUGH; // ־ݲ + } + + temp_length = fifo->max - fifo->end; // βָ뻺βжٿռ + if(*length <= temp_length) // 㹻һԶȡ + { + switch(fifo->type) + { + case FIFO_DATA_8BIT: + memcpy(dat, &(((uint8 *)fifo->buffer)[fifo->end]), *length); + break; + case FIFO_DATA_16BIT: + memcpy(dat, &(((uint16 *)fifo->buffer)[fifo->end]), *length * 2); + break; + case FIFO_DATA_32BIT: + memcpy(dat, &(((uint32 *)fifo->buffer)[fifo->end]), *length * 4); + break; + } + } + else + { + switch(fifo->type) + { + case FIFO_DATA_8BIT: + memcpy(dat, &(((uint8 *)fifo->buffer)[fifo->end]), temp_length); + memcpy(&(((uint8 *)dat)[temp_length]), fifo->buffer, *length - temp_length); + break; + case FIFO_DATA_16BIT: + memcpy(dat, &(((uint16 *)fifo->buffer)[fifo->end]), temp_length * 2); + memcpy(&(((uint16 *)dat)[temp_length]), fifo->buffer, (*length - temp_length) * 2); + break; + case FIFO_DATA_32BIT: + memcpy(dat, &(((uint32 *)fifo->buffer)[fifo->end]), temp_length * 4); + memcpy(&(((uint32 *)dat)[temp_length]), fifo->buffer, (*length - temp_length) * 4); + break; + } + } + + if(flag == FIFO_READ_AND_CLEAN) // ѡȡ FIFO ״̬ + { + if(FIFO_CLEAR & fifo->execution) + { + return_state = FIFO_CLEAR_UNDO; + break; + } + fifo->execution |= FIFO_CLEAR; + fifo_end_offset(fifo, *length); // ƶ FIFO ͷָ + fifo->size += *length; + fifo->execution &= ~FIFO_CLEAR; + } + }while(0); + fifo->execution &= FIFO_READ; + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// FIFO βȡָ buffer +// ˵ *fifo FIFO ָ +// ˵ *dat Ŀ껺ָ +// ˵ *length ȡݳ ûôᱻ޸ +// ˵ flag Ƿ FIFO ״̬ ѡǷնȡ +// ز fifo_state_enum ״̬ +// ʹʾ zf_log(fifo_read_tail_buffer(&fifo, data, &length, FIFO_READ_ONLY) == FIFO_SUCCESS, "fifo_read_buffer error"); +// עϢ ʹ FIFO_READ_AND_CLEAN ᶪݲ FIFO +// ʹ FIFO_READ_AND_CLEAN ᶪݲ FIFO +// ʹ FIFO_READ_AND_CLEAN ᶪݲ FIFO +//------------------------------------------------------------------------------------------------------------------- +fifo_state_enum fifo_read_tail_buffer (fifo_struct *fifo, void *dat, uint32 *length, fifo_operation_enum flag) +{ + zf_assert(fifo != NULL); + zf_assert(length != NULL); + fifo_state_enum return_state = FIFO_SUCCESS; + uint32 temp_length; + uint32 fifo_data_length; + + do + { + if(NULL == dat) + { + return_state = FIFO_BUFFER_NULL; + break; + } + fifo->execution |= FIFO_READ; + + fifo_data_length = fifo_used(fifo); + if(*length > fifo_data_length) + { + *length = fifo_data_length; // ȡij + return_state = FIFO_DATA_NO_ENOUGH; // ־ݲ + } + + if((fifo->head > fifo->end) || (fifo->head >= *length)) + { + switch(fifo->type) + { + case FIFO_DATA_8BIT: + memcpy(dat, &(((uint8 *)fifo->buffer)[fifo->head - *length]), *length); + break; + case FIFO_DATA_16BIT: + memcpy(dat, &(((uint16 *)fifo->buffer)[fifo->head - *length]), *length * 2); + break; + case FIFO_DATA_32BIT: + memcpy(dat, &(((uint32 *)fifo->buffer)[fifo->head - *length]), *length * 4); + break; + } + } + else + { + temp_length = *length - fifo->head; // βָ뻺βжٿռ + switch(fifo->type) + { + case FIFO_DATA_8BIT: + memcpy(dat, &(((uint8 *)fifo->buffer)[fifo->max - temp_length]), temp_length); + memcpy(&(((uint8 *)dat)[temp_length]), &(((uint8 *)fifo->buffer)[fifo->head - *length]), (*length - temp_length)); + break; + case FIFO_DATA_16BIT: + memcpy(dat, &(((uint16 *)fifo->buffer)[fifo->max - temp_length]), temp_length * 2); + memcpy(&(((uint16 *)dat)[temp_length]), &(((uint16 *)fifo->buffer)[fifo->head - *length]), (*length - temp_length) * 2); + break; + case FIFO_DATA_32BIT: + memcpy(dat, &(((uint32 *)fifo->buffer)[fifo->max - temp_length]), temp_length * 4); + memcpy(&(((uint32 *)dat)[temp_length]), &(((uint32 *)fifo->buffer)[fifo->head - *length]), (*length - temp_length) * 4); + break; + } + } + + if(flag == FIFO_READ_AND_CLEAN) // ѡȡ FIFO ״̬ + { + if(FIFO_CLEAR & fifo->execution) + { + return_state = FIFO_CLEAR_UNDO; + break; + } + fifo->execution |= FIFO_CLEAR; + fifo_end_offset(fifo, (fifo->max - fifo->size)); + fifo->size = fifo->max; + fifo->execution &= ~FIFO_CLEAR; + } + }while(0); + fifo->execution &= FIFO_READ; + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// FIFO ʼ ضӦ +// ˵ *fifo FIFO ָ +// ˵ type FIFO λ +// ˵ *buffer_addr ҪصĻ +// ˵ size С +// ز fifo_state_enum ״̬ +// ʹʾ fifo_init(&user_fifo, user_buffer, 64); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +fifo_state_enum fifo_init (fifo_struct *fifo, fifo_data_type_enum type, void *buffer_addr, uint32 size) +{ + zf_assert(fifo != NULL); + fifo_state_enum return_value = FIFO_SUCCESS; + do + { + if(NULL == buffer_addr) + { + return_value = FIFO_BUFFER_NULL; + break; + } + fifo->buffer = buffer_addr; + fifo->execution = FIFO_IDLE; + fifo->type = type; + fifo->head = 0; + fifo->end = 0; + fifo->size = size; + fifo->max = size; + }while(0); + return return_value; +} diff --git a/libraries/zf_common/zf_common_fifo.h b/libraries/zf_common/zf_common_fifo.h new file mode 100644 index 0000000..32c6a60 --- /dev/null +++ b/libraries/zf_common/zf_common_fifo.h @@ -0,0 +1,96 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_common_fifo +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_common_fifo_h_ +#define _zf_common_fifo_h_ + +#include "zf_common_typedef.h" + +typedef enum +{ + FIFO_SUCCESS, + + FIFO_WRITE_UNDO, + FIFO_CLEAR_UNDO, + FIFO_BUFFER_NULL, + FIFO_SPACE_NO_ENOUGH, + FIFO_DATA_NO_ENOUGH, +}fifo_state_enum; + +typedef enum +{ + FIFO_IDLE = 0x00, + FIFO_CLEAR = 0x01, + FIFO_WRITE = 0x02, + FIFO_READ = 0x04, +}fifo_execution_enum; + +typedef enum +{ + FIFO_READ_AND_CLEAN, + FIFO_READ_ONLY, +}fifo_operation_enum; + +typedef enum +{ + FIFO_DATA_8BIT, + FIFO_DATA_16BIT, + FIFO_DATA_32BIT, +}fifo_data_type_enum; + +typedef struct +{ + uint8 execution; // ִв + fifo_data_type_enum type; // + void *buffer; // ָ + uint32 head; // ͷָ ָյĻ + uint32 end; // βָ ָǿջ棨ȫճ⣩ + uint32 size; // ʣС + uint32 max; // ܴС +}fifo_struct; + +fifo_state_enum fifo_clear (fifo_struct *fifo); +uint32 fifo_used (fifo_struct *fifo); + +fifo_state_enum fifo_write_element (fifo_struct *fifo, uint32 dat); +fifo_state_enum fifo_write_buffer (fifo_struct *fifo, void *dat, uint32 length); +fifo_state_enum fifo_read_element (fifo_struct *fifo, void *dat, fifo_operation_enum flag); +fifo_state_enum fifo_read_buffer (fifo_struct *fifo, void *dat, uint32 *length, fifo_operation_enum flag); +fifo_state_enum fifo_read_tail_buffer (fifo_struct *fifo, void *dat, uint32 *length, fifo_operation_enum flag); + +fifo_state_enum fifo_init (fifo_struct *fifo, fifo_data_type_enum type, void *buffer_addr, uint32 size); + +#endif + diff --git a/libraries/zf_common/zf_common_font.c b/libraries/zf_common/zf_common_font.c new file mode 100644 index 0000000..094730a --- /dev/null +++ b/libraries/zf_common/zf_common_font.c @@ -0,0 +1,2718 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_common_font +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "zf_common_font.h" + +const uint8 ascii_font_8x16[][16]= +{ + // <> <ʽ> <> <8*16> + // < 8bit Ϊһģ> <ȡģ> + + // ģݴʽΪ{byte1, byte2,....byte16} + + // ģضӦϵ + // byte 1 2 3 4 5 6 7 8 + // bit [ 0] [ 8] [ 16] [ 24] [ 32] [ 40] [ 48] [ 56] + // bit [ 1] [ 9] [ 17] [ 25] [ 33] [ 41] [ 49] [ 57] + // bit [ 2] [ 10] [ 18] [ 26] [ 34] [ 42] [ 50] [ 58] + // bit [ 3] [ 11] [ 19] [ 37] [ 35] [ 43] [ 51] [ 59] + // bit [ 4] [ 12] [ 20] [ 38] [ 36] [ 44] [ 52] [ 60] + // bit [ 5] [ 13] [ 21] [ 39] [ 37] [ 45] [ 53] [ 61] + // bit [ 6] [ 14] [ 22] [ 30] [ 38] [ 46] [ 54] [ 62] + // bit [ 7] [ 15] [ 23] [ 31] [ 39] [ 47] [ 55] [ 63] + + // byte 9 10 11 12 13 14 15 16 + // bit [ 64] [ 72] [ 80] [ 88] [ 96] [104] [112] [120] + // bit [ 65] [ 73] [ 81] [ 89] [ 97] [105] [113] [121] + // bit [ 66] [ 74] [ 82] [ 90] [ 98] [106] [114] [122] + // bit [ 67] [ 75] [ 83] [ 91] [ 99] [107] [115] [123] + // bit [ 68] [ 76] [ 84] [ 92] [100] [108] [116] [124] + // bit [ 69] [ 77] [ 85] [ 93] [101] [109] [117] [125] + // bit [ 70] [ 78] [ 86] [ 94] [102] [110] [118] [126] + // bit [ 71] [ 79] [ 87] [ 95] [103] [111] [119] [127] + + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // 0 + {0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x30,0x00,0x00,0x00}, // ! 1 + {0x00,0x10,0x0C,0x06,0x10,0x0C,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // " 2 + {0x40,0xC0,0x78,0x40,0xC0,0x78,0x40,0x00,0x04,0x3F,0x04,0x04,0x3F,0x04,0x04,0x00}, // # 3 + {0x00,0x70,0x88,0xFC,0x08,0x30,0x00,0x00,0x00,0x18,0x20,0xFF,0x21,0x1E,0x00,0x00}, // $ 4 + {0xF0,0x08,0xF0,0x00,0xE0,0x18,0x00,0x00,0x00,0x21,0x1C,0x03,0x1E,0x21,0x1E,0x00}, // % 5 + {0x00,0xF0,0x08,0x88,0x70,0x00,0x00,0x00,0x1E,0x21,0x23,0x24,0x19,0x27,0x21,0x10}, // & 6 + {0x10,0x16,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ' 7 + {0x00,0x00,0x00,0xE0,0x18,0x04,0x02,0x00,0x00,0x00,0x00,0x07,0x18,0x20,0x40,0x00}, // ( 8 + {0x00,0x02,0x04,0x18,0xE0,0x00,0x00,0x00,0x00,0x40,0x20,0x18,0x07,0x00,0x00,0x00}, // ) 9 + {0x40,0x40,0x80,0xF0,0x80,0x40,0x40,0x00,0x02,0x02,0x01,0x0F,0x01,0x02,0x02,0x00}, // * 10 + {0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x1F,0x01,0x01,0x01,0x00}, // + 11 + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xB0,0x70,0x00,0x00,0x00,0x00,0x00}, // , 12 + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01}, // - 13 + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,0x00,0x00}, // . 14 + {0x00,0x00,0x00,0x00,0x80,0x60,0x18,0x04,0x00,0x60,0x18,0x06,0x01,0x00,0x00,0x00}, // / 15 + {0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x0F,0x10,0x20,0x20,0x10,0x0F,0x00}, // 0 16 + {0x00,0x10,0x10,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00}, // 1 17 + {0x00,0x70,0x08,0x08,0x08,0x88,0x70,0x00,0x00,0x30,0x28,0x24,0x22,0x21,0x30,0x00}, // 2 18 + {0x00,0x30,0x08,0x88,0x88,0x48,0x30,0x00,0x00,0x18,0x20,0x20,0x20,0x11,0x0E,0x00}, // 3 19 + {0x00,0x00,0xC0,0x20,0x10,0xF8,0x00,0x00,0x00,0x07,0x04,0x24,0x24,0x3F,0x24,0x00}, // 4 20 + {0x00,0xF8,0x08,0x88,0x88,0x08,0x08,0x00,0x00,0x19,0x21,0x20,0x20,0x11,0x0E,0x00}, // 5 21 + {0x00,0xE0,0x10,0x88,0x88,0x18,0x00,0x00,0x00,0x0F,0x11,0x20,0x20,0x11,0x0E,0x00}, // 6 22 + {0x00,0x38,0x08,0x08,0xC8,0x38,0x08,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00}, // 7 23 + {0x00,0x70,0x88,0x08,0x08,0x88,0x70,0x00,0x00,0x1C,0x22,0x21,0x21,0x22,0x1C,0x00}, // 8 24 + {0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x00,0x31,0x22,0x22,0x11,0x0F,0x00}, // 9 25 + {0x00,0x00,0x00,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00}, // : 26 + {0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x00,0x00,0x00,0x00}, // ; 27 + {0x00,0x00,0x80,0x40,0x20,0x10,0x08,0x00,0x00,0x01,0x02,0x04,0x08,0x10,0x20,0x00}, // < 28 + {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x00}, // = 29 + {0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00,0x00,0x20,0x10,0x08,0x04,0x02,0x01,0x00}, // > 30 + {0x00,0x70,0x48,0x08,0x08,0x08,0xF0,0x00,0x00,0x00,0x00,0x30,0x36,0x01,0x00,0x00}, // ? 31 + {0xC0,0x30,0xC8,0x28,0xE8,0x10,0xE0,0x00,0x07,0x18,0x27,0x24,0x23,0x14,0x0B,0x00}, // @ 32 + {0x00,0x00,0xC0,0x38,0xE0,0x00,0x00,0x00,0x20,0x3C,0x23,0x02,0x02,0x27,0x38,0x20}, // A 33 + {0x08,0xF8,0x88,0x88,0x88,0x70,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x11,0x0E,0x00}, // B 34 + {0xC0,0x30,0x08,0x08,0x08,0x08,0x38,0x00,0x07,0x18,0x20,0x20,0x20,0x10,0x08,0x00}, // C 35 + {0x08,0xF8,0x08,0x08,0x08,0x10,0xE0,0x00,0x20,0x3F,0x20,0x20,0x20,0x10,0x0F,0x00}, // D 36 + {0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x20,0x23,0x20,0x18,0x00}, // E 37 + {0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x00,0x03,0x00,0x00,0x00}, // F 38 + {0xC0,0x30,0x08,0x08,0x08,0x38,0x00,0x00,0x07,0x18,0x20,0x20,0x22,0x1E,0x02,0x00}, // G 39 + {0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x20,0x3F,0x21,0x01,0x01,0x21,0x3F,0x20}, // H 40 + {0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00}, // I 41 + {0x00,0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,0x00}, // J 42 + {0x08,0xF8,0x88,0xC0,0x28,0x18,0x08,0x00,0x20,0x3F,0x20,0x01,0x26,0x38,0x20,0x00}, // K 43 + {0x08,0xF8,0x08,0x00,0x00,0x00,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x20,0x30,0x00}, // L 44 + {0x08,0xF8,0xF8,0x00,0xF8,0xF8,0x08,0x00,0x20,0x3F,0x00,0x3F,0x00,0x3F,0x20,0x00}, // M 45 + {0x08,0xF8,0x30,0xC0,0x00,0x08,0xF8,0x08,0x20,0x3F,0x20,0x00,0x07,0x18,0x3F,0x00}, // N 46 + {0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x10,0x20,0x20,0x20,0x10,0x0F,0x00}, // O 47 + {0x08,0xF8,0x08,0x08,0x08,0x08,0xF0,0x00,0x20,0x3F,0x21,0x01,0x01,0x01,0x00,0x00}, // P 48 + {0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x18,0x24,0x24,0x38,0x50,0x4F,0x00}, // Q 49 + {0x08,0xF8,0x88,0x88,0x88,0x88,0x70,0x00,0x20,0x3F,0x20,0x00,0x03,0x0C,0x30,0x20}, // R 50 + {0x00,0x70,0x88,0x08,0x08,0x08,0x38,0x00,0x00,0x38,0x20,0x21,0x21,0x22,0x1C,0x00}, // S 51 + {0x18,0x08,0x08,0xF8,0x08,0x08,0x18,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00}, // T 52 + {0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00}, // U 53 + {0x08,0x78,0x88,0x00,0x00,0xC8,0x38,0x08,0x00,0x00,0x07,0x38,0x0E,0x01,0x00,0x00}, // V 54 + {0xF8,0x08,0x00,0xF8,0x00,0x08,0xF8,0x00,0x03,0x3C,0x07,0x00,0x07,0x3C,0x03,0x00}, // W 55 + {0x08,0x18,0x68,0x80,0x80,0x68,0x18,0x08,0x20,0x30,0x2C,0x03,0x03,0x2C,0x30,0x20}, // X 56 + {0x08,0x38,0xC8,0x00,0xC8,0x38,0x08,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00}, // Y 57 + {0x10,0x08,0x08,0x08,0xC8,0x38,0x08,0x00,0x20,0x38,0x26,0x21,0x20,0x20,0x18,0x00}, // Z 58 + {0x00,0x00,0x00,0xFE,0x02,0x02,0x02,0x00,0x00,0x00,0x00,0x7F,0x40,0x40,0x40,0x00}, // [ 59 + {0x00,0x0C,0x30,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x06,0x38,0xC0,0x00}, // \ 60 + {0x00,0x02,0x02,0x02,0xFE,0x00,0x00,0x00,0x00,0x40,0x40,0x40,0x7F,0x00,0x00,0x00}, // ] 61 + {0x00,0x00,0x04,0x02,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ^ 62 + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80}, // _ 63 + {0x00,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ` 64 + {0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x19,0x24,0x22,0x22,0x22,0x3F,0x20}, // a 65 + {0x08,0xF8,0x00,0x80,0x80,0x00,0x00,0x00,0x00,0x3F,0x11,0x20,0x20,0x11,0x0E,0x00}, // b 66 + {0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x0E,0x11,0x20,0x20,0x20,0x11,0x00}, // c 67 + {0x00,0x00,0x00,0x80,0x80,0x88,0xF8,0x00,0x00,0x0E,0x11,0x20,0x20,0x10,0x3F,0x20}, // d 68 + {0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x22,0x22,0x22,0x22,0x13,0x00}, // e 69 + {0x00,0x80,0x80,0xF0,0x88,0x88,0x88,0x18,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00}, // f 70 + {0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x6B,0x94,0x94,0x94,0x93,0x60,0x00}, // g 71 + {0x08,0xF8,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20}, // h 72 + {0x00,0x80,0x98,0x98,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00}, // i 73 + {0x00,0x00,0x00,0x80,0x98,0x98,0x00,0x00,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00}, // j 74 + {0x08,0xF8,0x00,0x00,0x80,0x80,0x80,0x00,0x20,0x3F,0x24,0x02,0x2D,0x30,0x20,0x00}, // k 75 + {0x00,0x08,0x08,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00}, // l 76 + {0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x20,0x3F,0x20,0x00,0x3F,0x20,0x00,0x3F}, // m 77 + {0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20}, // n 78 + {0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00}, // o 79 + {0x80,0x80,0x00,0x80,0x80,0x00,0x00,0x00,0x80,0xFF,0xA1,0x20,0x20,0x11,0x0E,0x00}, // p 80 + {0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x0E,0x11,0x20,0x20,0xA0,0xFF,0x80}, // q 81 + {0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x20,0x20,0x3F,0x21,0x20,0x00,0x01,0x00}, // r 82 + {0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x33,0x24,0x24,0x24,0x24,0x19,0x00}, // s 83 + {0x00,0x80,0x80,0xE0,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x1F,0x20,0x20,0x00,0x00}, // t 84 + {0x80,0x80,0x00,0x00,0x00,0x80,0x80,0x00,0x00,0x1F,0x20,0x20,0x20,0x10,0x3F,0x20}, // u 85 + {0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x00,0x01,0x0E,0x30,0x08,0x06,0x01,0x00}, // v 86 + {0x80,0x80,0x00,0x80,0x00,0x80,0x80,0x80,0x0F,0x30,0x0C,0x03,0x0C,0x30,0x0F,0x00}, // w 87 + {0x00,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x31,0x2E,0x0E,0x31,0x20,0x00}, // x 88 + {0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x80,0x81,0x8E,0x70,0x18,0x06,0x01,0x00}, // y 89 + {0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x21,0x30,0x2C,0x22,0x21,0x30,0x00}, // z 90 + {0x00,0x00,0x00,0x00,0x80,0x7C,0x02,0x02,0x00,0x00,0x00,0x00,0x00,0x3F,0x40,0x40}, // { 91 + {0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00}, // | 92 + {0x00,0x02,0x02,0x7C,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x3F,0x00,0x00,0x00,0x00}, // } 93 + {0x00,0x06,0x01,0x01,0x02,0x02,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} // ~ 94 +}; + +const uint8 ascii_font_6x8[][6] = +{ + // <> <ʽ> <> <6*8> + // < 8bit Ϊһģ> <ȡģ> + + // ģݴʽΪ{byte1, byte2,....byte6} + + // ģضӦϵ + // byte 1 2 3 4 5 6 + // bit [ 0] [ 8] [ 16] [ 24] [ 32] [ 40] + // bit [ 1] [ 9] [ 17] [ 25] [ 33] [ 41] + // bit [ 2] [ 10] [ 18] [ 26] [ 34] [ 42] + // bit [ 3] [ 11] [ 19] [ 37] [ 35] [ 43] + // bit [ 4] [ 12] [ 20] [ 38] [ 36] [ 44] + // bit [ 5] [ 13] [ 21] [ 39] [ 37] [ 45] + // bit [ 6] [ 14] [ 22] [ 30] [ 38] [ 46] + // bit [ 7] [ 15] [ 23] [ 31] [ 39] [ 47] + + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // 0 + { 0x00, 0x00, 0x00, 0x2f, 0x00, 0x00 }, // ! 1 + { 0x00, 0x00, 0x07, 0x00, 0x07, 0x00 }, // " 2 + { 0x00, 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # 3 + { 0x00, 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ 4 + { 0x00, 0x62, 0x64, 0x08, 0x13, 0x23 }, // % 5 + { 0x00, 0x36, 0x49, 0x55, 0x22, 0x50 }, // & 6 + { 0x00, 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' 7 + { 0x00, 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( 8 + { 0x00, 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) 9 + { 0x00, 0x14, 0x08, 0x3E, 0x08, 0x14 }, // * 10 + { 0x00, 0x08, 0x08, 0x3E, 0x08, 0x08 }, // + 11 + { 0x00, 0x00, 0x00, 0xA0, 0x60, 0x00 }, // , 12 + { 0x00, 0x08, 0x08, 0x08, 0x08, 0x08 }, // - 13 + { 0x00, 0x00, 0x60, 0x60, 0x00, 0x00 }, // . 14 + { 0x40, 0x20, 0x10, 0x08, 0x04, 0x02 }, // / 15 + { 0x00, 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 16 + { 0x00, 0x00, 0x42, 0x7F, 0x40, 0x00 }, // 1 17 + { 0x00, 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 18 + { 0x00, 0x21, 0x41, 0x45, 0x4B, 0x31 }, // 3 19 + { 0x00, 0x18, 0x14, 0x12, 0x7F, 0x10 }, // 4 20 + { 0x00, 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 21 + { 0x00, 0x3C, 0x4A, 0x49, 0x49, 0x30 }, // 6 22 + { 0x00, 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 23 + { 0x00, 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 24 + { 0x00, 0x06, 0x49, 0x49, 0x29, 0x1E }, // 9 25 + { 0x00, 0x00, 0x36, 0x36, 0x00, 0x00 }, // : 26 + { 0x00, 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; 27 + { 0x00, 0x08, 0x14, 0x22, 0x41, 0x00 }, // < 28 + { 0x00, 0x14, 0x14, 0x14, 0x14, 0x14 }, // = 29 + { 0x00, 0x00, 0x41, 0x22, 0x14, 0x08 }, // > 30 + { 0x00, 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? 31 + { 0x00, 0x32, 0x49, 0x59, 0x51, 0x3E }, // @ 32 + { 0x00, 0x7C, 0x12, 0x11, 0x12, 0x7C }, // A 33 + { 0x00, 0x7F, 0x49, 0x49, 0x49, 0x36 }, // B 34 + { 0x00, 0x3E, 0x41, 0x41, 0x41, 0x22 }, // C 35 + { 0x00, 0x7F, 0x41, 0x41, 0x22, 0x1C }, // D 36 + { 0x00, 0x7F, 0x49, 0x49, 0x49, 0x41 }, // E 37 + { 0x00, 0x7F, 0x09, 0x09, 0x09, 0x01 }, // F 38 + { 0x00, 0x3E, 0x41, 0x49, 0x49, 0x7A }, // G 39 + { 0x00, 0x7F, 0x08, 0x08, 0x08, 0x7F }, // H 40 + { 0x00, 0x00, 0x41, 0x7F, 0x41, 0x00 }, // I 41 + { 0x00, 0x20, 0x40, 0x41, 0x3F, 0x01 }, // J 42 + { 0x00, 0x7F, 0x08, 0x14, 0x22, 0x41 }, // K 43 + { 0x00, 0x7F, 0x40, 0x40, 0x40, 0x40 }, // L 44 + { 0x00, 0x7F, 0x02, 0x0C, 0x02, 0x7F }, // M 45 + { 0x00, 0x7F, 0x04, 0x08, 0x10, 0x7F }, // N 46 + { 0x00, 0x3E, 0x41, 0x41, 0x41, 0x3E }, // O 47 + { 0x00, 0x7F, 0x09, 0x09, 0x09, 0x06 }, // P 48 + { 0x00, 0x3E, 0x41, 0x51, 0x21, 0x5E }, // Q 49 + { 0x00, 0x7F, 0x09, 0x19, 0x29, 0x46 }, // R 50 + { 0x00, 0x46, 0x49, 0x49, 0x49, 0x31 }, // S 51 + { 0x00, 0x01, 0x01, 0x7F, 0x01, 0x01 }, // T 52 + { 0x00, 0x3F, 0x40, 0x40, 0x40, 0x3F }, // U 53 + { 0x00, 0x1F, 0x20, 0x40, 0x20, 0x1F }, // V 54 + { 0x00, 0x3F, 0x40, 0x38, 0x40, 0x3F }, // W 55 + { 0x00, 0x63, 0x14, 0x08, 0x14, 0x63 }, // X 56 + { 0x00, 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y 57 + { 0x00, 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z 58 + { 0x00, 0x00, 0x7F, 0x41, 0x41, 0x00 }, // [ 59 + { 0x02, 0x04, 0x08, 0x10, 0x20, 0x40 }, // \ 60 + { 0x00, 0x00, 0x41, 0x41, 0x7F, 0x00 }, // ] 61 + { 0x00, 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ 62 + { 0x00, 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ 63 + { 0x00, 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` 64 + { 0x00, 0x20, 0x54, 0x54, 0x54, 0x78 }, // a 65 + { 0x00, 0x7F, 0x48, 0x44, 0x44, 0x38 }, // b 66 + { 0x00, 0x38, 0x44, 0x44, 0x44, 0x20 }, // c 67 + { 0x00, 0x38, 0x44, 0x44, 0x48, 0x7F }, // d 68 + { 0x00, 0x38, 0x54, 0x54, 0x54, 0x18 }, // e 69 + { 0x00, 0x08, 0x7E, 0x09, 0x01, 0x02 }, // f 70 + { 0x00, 0x18, 0xA4, 0xA4, 0xA4, 0x7C }, // g 71 + { 0x00, 0x7F, 0x08, 0x04, 0x04, 0x78 }, // h 72 + { 0x00, 0x00, 0x44, 0x7D, 0x40, 0x00 }, // i 73 + { 0x00, 0x40, 0x80, 0x84, 0x7D, 0x00 }, // j 74 + { 0x00, 0x7F, 0x10, 0x28, 0x44, 0x00 }, // k 75 + { 0x00, 0x00, 0x41, 0x7F, 0x40, 0x00 }, // l 76 + { 0x00, 0x7C, 0x04, 0x18, 0x04, 0x78 }, // m 77 + { 0x00, 0x7C, 0x08, 0x04, 0x04, 0x78 }, // n 78 + { 0x00, 0x38, 0x44, 0x44, 0x44, 0x38 }, // o 79 + { 0x00, 0xFC, 0x24, 0x24, 0x24, 0x18 }, // p 80 + { 0x00, 0x18, 0x24, 0x24, 0x18, 0xFC }, // q 81 + { 0x00, 0x7C, 0x08, 0x04, 0x04, 0x08 }, // r 82 + { 0x00, 0x48, 0x54, 0x54, 0x54, 0x20 }, // s 83 + { 0x00, 0x04, 0x3F, 0x44, 0x40, 0x20 }, // t 84 + { 0x00, 0x3C, 0x40, 0x40, 0x20, 0x7C }, // u 85 + { 0x00, 0x1C, 0x20, 0x40, 0x20, 0x1C }, // v 86 + { 0x00, 0x3C, 0x40, 0x30, 0x40, 0x3C }, // w 87 + { 0x00, 0x44, 0x28, 0x10, 0x28, 0x44 }, // x 88 + { 0x00, 0x1C, 0xA0, 0xA0, 0xA0, 0x7C }, // y 89 + { 0x00, 0x44, 0x64, 0x54, 0x4C, 0x44 }, // z 90 + { 0x14, 0x14, 0x14, 0x14, 0x14, 0x14 } // horiz lines +}; + +//------------------------------------------------------------------------------------------------------------------- +// ʹPCtoLCD2002ȡģ +// 롢ʽ˳ 16*16 +//------------------------------------------------------------------------------------------------------------------- +const uint8 chinese_test[8][16] = +{ + {0x00,0x00,0x23,0xFC,0x10,0x40,0x10,0x80,0x01,0x44,0x06,0x68,0xF0,0xB0,0x11,0x28}, + {0x16,0x68,0x10,0xA4,0x11,0x24,0x16,0x20,0x10,0xA0,0x28,0x40,0x47,0xFE,0x00,0x00},/*"",0*/ + {0x00,0x00,0xFF,0xC0,0x00,0x40,0x00,0x44,0x00,0x48,0x00,0x50,0x00,0x60,0x00,0x50}, + {0x00,0x48,0x00,0x44,0x00,0x20,0x00,0x20,0x00,0x12,0x00,0x0A,0x00,0x06,0x00,0x02},/*"",1*/ + {0x08,0x10,0x1D,0x10,0xF0,0x90,0x10,0x90,0x10,0x10,0xFD,0x10,0x10,0x90,0x38,0x90}, + {0x34,0x10,0x50,0x1E,0x53,0xF0,0x90,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10},/*"",2*/ + {0x10,0x20,0x10,0x20,0x10,0x20,0x13,0xFE,0xFC,0x20,0x10,0x20,0x10,0x20,0x15,0xFC}, + {0x18,0x84,0x30,0x88,0xD0,0x48,0x10,0x50,0x10,0x20,0x10,0x50,0x51,0x88,0x26,0x06},/*"",3*/ +}; + +//------------------------------------------------------------------------------------------------------------------- +// ʹPCtoLCD2002ȡģ +// 롢ʽ 16*16 +//------------------------------------------------------------------------------------------------------------------- +const uint8 oled_16x16_chinese[][16]= +{ + {0x40,0x40,0x42,0xCC,0x00,0x20,0x22,0x92,0x4A,0x36,0xE2,0x42,0xA2,0x12,0x00,0x00}, + {0x00,0x40,0x20,0x1F,0x20,0x49,0x49,0x44,0x52,0x61,0x5F,0x40,0x41,0x46,0x40,0x00},/*"",0*/ + {0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0xFE,0x40,0xA0,0x10,0x08,0x00,0x00}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x0C,0x10,0x21,0x42,0xF0,0x00},/*"",1*/ + {0x24,0x24,0xA4,0xFE,0xA3,0x22,0x00,0x22,0xCC,0x00,0x00,0xFF,0x00,0x00,0x00,0x00}, + {0x08,0x06,0x01,0xFF,0x00,0x01,0x04,0x04,0x04,0x04,0x04,0xFF,0x02,0x02,0x02,0x00},/*"",2*/ + {0x10,0x10,0x10,0xFF,0x10,0x90,0x08,0x88,0x88,0x88,0xFF,0x88,0x88,0x88,0x08,0x00}, + {0x04,0x44,0x82,0x7F,0x01,0x80,0x80,0x40,0x43,0x2C,0x10,0x28,0x46,0x81,0x80,0x00},/*"",3*/ +}; + +//16λBMP 240*80 ɿƼlogoͼȡģ +//Image2LCDȡģѡ +//ˮƽɨ +//16λ +//240*80 +//ͼͷ +// +//Զ +//λǰ +const unsigned char gImage_seekfree_logo[38400] = { /* 0X00,0X10,0XF0,0X00,0X50,0X00,0X01,0X1B, */ +0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF, +0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF, +0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF, 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+/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_common_font +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_common_font_h_ +#define _zf_common_font_h_ + +#include "zf_common_typedef.h" + +//-------ɫ---------- +typedef enum +{ + RGB565_WHITE = (0xFFFF), // ɫ + RGB565_BLACK = (0x0000), // ɫ + RGB565_BLUE = (0x001F), // ɫ + RGB565_PURPLE = (0xF81F), // ɫ + RGB565_PINK = (0xFE19), // ɫ + RGB565_RED = (0xF800), // ɫ + RGB565_MAGENTA = (0xF81F), // Ʒ + RGB565_GREEN = (0x07E0), // ɫ + RGB565_CYAN = (0x07FF), // ɫ + RGB565_YELLOW = (0xFFE0), // ɫ + RGB565_BROWN = (0xBC40), // ɫ + RGB565_GRAY = (0x8430), // ɫ + + RGB565_39C5BB = (0x3616), + RGB565_66CCFF = (0x665F), +}rgb565_color_enum; + +extern const uint8 ascii_font_8x16[][16]; +extern const uint8 ascii_font_6x8[][6]; +extern const uint8 chinese_test[8][16]; +extern const uint8 oled_16x16_chinese[][16]; +extern const uint8 gImage_seekfree_logo[38400]; + +#endif diff --git a/libraries/zf_common/zf_common_function.c b/libraries/zf_common/zf_common_function.c new file mode 100644 index 0000000..f76b0d5 --- /dev/null +++ b/libraries/zf_common/zf_common_function.c @@ -0,0 +1,907 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_common_function +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "zf_common_debug.h" +#include "zf_common_function.h" + +//------------------------------------------------------------------------------------------------------------------- +// ȡԼ ֮ +// ˵ num1 1 +// ˵ num2 2 +// ز uint32 Լ +// ʹʾ return func_get_greatest_common_divisor(144, 36); // ȡ 144 36 Լ +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 func_get_greatest_common_divisor (uint32 num1, uint32 num2) +{ + while(num1 != num2) + { + if(num1 > num2) + { + num1 = num1 - num2; + } + if(num1 < num2) + { + num2 = num2 - num1; + } + } + return num1; +} + +//------------------------------------------------------------------------------------------------------------------- +// ʱ +// ˵ t ʱʱ +// ز void +// ʹʾ func_soft_delay(100); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void func_soft_delay (volatile long t) +{ + while(t --); +} + +//------------------------------------------------------------------------------------------------------------------- +// ַת ݷΧ [-32768,32767] +// ˵ *str ַ ɴ +// ز int32 ת +// ʹʾ int32 dat = func_str_to_int("-100"); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +int32 func_str_to_int (char *str) +{ + zf_assert(str != NULL); + uint8 sign = 0; // Ƿ 0- 1- + int32 temp = 0; // ʱ + do + { + if(NULL == str) + { + break; + } + + if('-' == *str) // һַǸ + { + sign = 1; // Ǹ + str ++; + } + else if('+' == *str) // һַ + { + str ++; + } + + while(('0' <= *str) && ('9' >= *str)) // ȷǸ + { + temp = temp * 10 + ((uint8)(*str) - 0x30); // ֵ + str ++; + } + + if(sign) + { + temp = -temp; + } + }while(0); + return temp; +} + +//------------------------------------------------------------------------------------------------------------------- +// תַ ݷΧ [-32768,32767] +// ˵ *str ַָ +// ˵ number +// ز void +// ʹʾ func_int_to_str(data_buffer, -300); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void func_int_to_str (char *str, int32 number) +{ + zf_assert(str != NULL); + uint8 data_temp[16]; // + uint8 bit = 0; // λ + int32 number_temp = 0; + + do + { + if(NULL == str) + { + break; + } + + if(0 > number) // + { + *str ++ = '-'; + number = -number; + } + else if(0 == number) // Ǹ 0 + { + *str = '0'; + break; + } + + while(0 != number) // ѭֱֵ + { + number_temp = number % 10; + data_temp[bit ++] = func_abs(number_temp); // ֵȡ + number /= 10; // ȡĸλ + } + while(0 != bit) // ȡָݼ + { + *str ++ = (data_temp[bit - 1] + 0x30); // ִӵеȡ ַ + bit --; + } + }while(0); +} + +//------------------------------------------------------------------------------------------------------------------- +// ַת ݷΧ [0,65535] +// ˵ *str ַ ޷ +// ز uint32 ת +// ʹʾ uint32 dat = func_str_to_uint("100"); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 func_str_to_uint (char *str) +{ + zf_assert(str != NULL); + uint32 temp = 0; // ʱ + + do + { + if(NULL == str) + { + break; + } + + while(('0' <= *str) && ('9' >= *str)) // ȷǸ + { + temp = temp * 10 + ((uint8)(*str) - 0x30); // ֵ + str ++; + } + }while(0); + + return temp; +} + +//------------------------------------------------------------------------------------------------------------------- +// תַ ݷΧ [0,65535] +// ˵ *str ַָ +// ˵ number +// ز void +// ʹʾ func_uint_to_str(data_buffer, 300); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void func_uint_to_str (char *str, uint32 number) +{ + zf_assert(str != NULL); + int8 data_temp[16]; // + uint8 bit = 0; // λ + + do + { + if(NULL == str) + { + break; + } + + if(0 == number) // Ǹ 0 + { + *str = '0'; + break; + } + + while(0 != number) // ѭֱֵ + { + data_temp[bit ++] = (number % 10); // ֵȡ + number /= 10; // ȡĸλ + } + while(0 != bit) // ȡָݼ + { + *str ++ = (data_temp[bit - 1] + 0x30); // ִӵеȡ ַ + bit --; + } + }while(0); +} + +//------------------------------------------------------------------------------------------------------------------- +// ַת ЧۼƾΪСλ +// ˵ *str ַ ɴ +// ز float ת +// ʹʾ float dat = func_str_to_float("-100.2"); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +float func_str_to_float (char *str) +{ + zf_assert(str != NULL); + uint8 sign = 0; // Ƿ 0- 1- + float temp = 0.0; // ʱ + float temp_point = 0.0; // ʱ С + float point_bit = 1; // СۼƳ + + do + { + if(NULL == str) + { + break; + } + + if('-' == *str) // + { + sign = 1; // Ǹ + str ++; + } + else if('+' == *str) // һַ + { + str ++; + } + + // ȡ + while(('0' <= *str) && ('9' >= *str)) // ȷǸ + { + temp = temp * 10 + ((uint8)(*str) - 0x30); // ֵȡ + str ++; + } + if('.' == *str) + { + str ++; + while(('0' <= *str) && ('9' >= *str) && point_bit < 1000000.0) // ȷǸ Ҿȿƻûλ + { + temp_point = temp_point * 10 + ((uint8)(*str) - 0x30); // ȡСֵ + point_bit *= 10; // ⲿСij + str ++; + } + temp_point /= point_bit; // С + } + temp += temp_point; // ֵƴ + + if(sign) + { + temp = -temp; + } + }while(0); + return temp; +} + +//------------------------------------------------------------------------------------------------------------------- +// תַ +// ˵ *str ַָ +// ˵ number +// ˵ point_bit С㾫 +// ز void +// ʹʾ func_float_to_str(data_buffer, 3.1415, 2); // data_buffer = "3.14" +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void func_float_to_str (char *str, float number, uint8 point_bit) +{ + zf_assert(str != NULL); + int data_int = 0; // + int data_float = 0.0; // С + int data_temp[8]; // ַ + int data_temp_point[6]; // Сַ + uint8 bit = point_bit; // תλ + + do + { + if(NULL == str) + { + break; + } + + // ȡ + data_int = (int)number; // ֱǿתΪ int + if(0 > number) // жԴǸ + { + *str ++ = '-'; + } + else if(0.0 == number) // Ǹ 0 + { + *str ++ = '0'; + *str ++ = '.'; + *str = '0'; + break; + } + + // ȡС + number = number - data_int; // ȥּ + while(bit --) + { + number = number * 10; // ҪСλȡ + } + data_float = (int)number; // ȡⲿֵ + + // תΪַ + bit = 0; + do + { + data_temp[bit ++] = data_int % 10; // ֵдַ + data_int /= 10; + }while(0 != data_int); + while(0 != bit) + { + *str ++ = (func_abs(data_temp[bit - 1]) + 0x30); // ٵ򽫵ֵдַ õֵ + bit --; + } + + // СתΪַ + if(point_bit != 0) + { + bit = 0; + *str ++ = '.'; + if(0 == data_float) + { + *str = '0'; + } + else + { + while(0 != point_bit) // жЧλ + { + data_temp_point[bit ++] = data_float % 10; // дַ + data_float /= 10; + point_bit --; + } + while(0 != bit) + { + *str ++ = (func_abs(data_temp_point[bit - 1]) + 0x30); // ٵ򽫵ֵдַ õֵ + bit --; + } + } + } + }while(0); +} + +//------------------------------------------------------------------------------------------------------------------- +// ַת ЧۼƾΪСλ +// ˵ str ַ ɴ +// ز double ת +// ʹʾ double dat = func_str_to_double("-100.2"); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +double func_str_to_double (char *str) +{ + zf_assert(str != NULL); + uint8 sign = 0; // Ƿ 0- 1- + double temp = 0.0; // ʱ + double temp_point = 0.0; // ʱ С + double point_bit = 1; // СۼƳ + + do + { + if(NULL == str) + { + break; + } + + if('-' == *str) // + { + sign = 1; // Ǹ + str ++; + } + else if('+' == *str) // һַ + { + str ++; + } + + // ȡ + while(('0' <= *str) && ('9' >= *str)) // ȷǸ + { + temp = temp * 10 + ((uint8)(*str) - 0x30); // ֵȡ + str ++; + } + if('.' == *str) + { + str ++; + while(('0' <= *str) && ('9' >= *str) && point_bit < 1000000000.0) // ȷǸ Ҿȿƻûλ + { + temp_point = temp_point * 10 + ((uint8)(*str) - 0x30); // ȡСֵ + point_bit *= 10; // ⲿСij + str ++; + } + temp_point /= point_bit; // С + } + temp += temp_point; // ֵƴ + + if(sign) + { + temp = -temp; + } + }while(0); + return temp; + +} + +//------------------------------------------------------------------------------------------------------------------- +// תַ +// ˵ *str ַָ +// ˵ number +// ˵ point_bit С㾫 +// ز void +// ʹʾ func_double_to_str(data_buffer, 3.1415, 2); // data_buffer = "3.14" +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void func_double_to_str (char *str, double number, uint8 point_bit) +{ + zf_assert(str != NULL); + int data_int = 0; // + int data_float = 0.0; // С + int data_temp[12]; // ַ + int data_temp_point[9]; // Сַ + uint8 bit = point_bit; // תλ + + do + { + if(NULL == str) + { + break; + } + + // ȡ + data_int = (int)number; // ֱǿתΪ int + if(0 > number) // жԴǸ + { + *str ++ = '-'; + } + else if(0.0 == number) // Ǹ 0 + { + *str ++ = '0'; + *str ++ = '.'; + *str = '0'; + break; + } + + // ȡС + number = number - data_int; // ȥּ + while(bit --) + { + number = number * 10; // ҪСλȡ + } + data_float = (int)number; // ȡⲿֵ + + // תΪַ + bit = 0; + do + { + data_temp[bit ++] = data_int % 10; // ֵдַ + data_int /= 10; + }while(0 != data_int); + while(0 != bit) + { + *str ++ = (func_abs(data_temp[bit - 1]) + 0x30); // ٵ򽫵ֵдַ õֵ + bit --; + } + + // СתΪַ + if(point_bit != 0) + { + bit = 0; + *str ++ = '.'; + if(0 == data_float) + *str = '0'; + else + { + while(0 != point_bit) // жЧλ + { + data_temp_point[bit ++] = data_float % 10; // дַ + data_float /= 10; + point_bit --; + } + while(0 != bit) + { + *str ++ = (func_abs(data_temp_point[bit - 1]) + 0x30); // ٵ򽫵ֵдַ õֵ + bit --; + } + } + } + }while(0); +} + +//------------------------------------------------------------------------------------------------------------------- +// ַת Hex +// ˵ str ַ ޷ +// ز uint32 ת +// ʹʾ uint32 dat = func_str_to_hex("0x11"); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 func_str_to_hex (char *str) +{ + zf_assert(str != NULL); + uint32 str_len = strlen(str); // ַ + uint32 result_data = 0; // + uint8 temp = 0; // + uint8 flag = 0; // ־λ + + do + { + if(NULL == str) + { + break; + } + + if(flag) + { + if(('a' <= *str) && ('f' >= *str)) + { + temp = (*str - 87); + } + else if(('A' <= *str) && ('F' >= *str)) + { + temp = (*str - 55); + } + else if(('0' <= *str) && ('9' >= *str)) + { + temp = (*str - 48); + } + else + { + break; + } + result_data = ((result_data << 4) | (temp & 0x0F)); + } + else + { +// if(strncmp("0x", str, 2)) + if((*str == '0') && (*(str + 1) == 'x')) + { + str ++; + flag = 1; + } + } + str ++; + }while(str_len --); + + return result_data; +} + +//------------------------------------------------------------------------------------------------------------------- +// Hex תַ +// ˵ *str ַָ +// ˵ number +// ز void +// ʹʾ func_hex_to_str(data_buffer, 0x11); // data_buffer = "0x11" +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void func_hex_to_str (char *str, uint32 number) +{ + zf_assert(str != NULL); + const char hex_index[16] = { + '0', '1', '2', '3', + '4', '5', '6', '7', + '8', '9', 'A', 'B', + 'C', 'D', 'E', 'F'}; + int8 data_temp[12]; // + uint8 bit = 0; // λ + + *str++ = '0'; + *str++ = 'x'; + do + { + if(NULL == str) + { + break; + } + + if(0 == number) // Ǹ 0 + { + *str = '0'; + break; + } + + while(0 != number) // ѭֱֵ + { + data_temp[bit ++] = (number & 0xF); // ֵȡ + number >>= 4; // ȡĸλ + } + while(0 != bit) // ȡָݼ + { + *str ++ = hex_index[data_temp[bit - 1]]; // ִӵеȡ ַ + bit --; + } + }while(0); +} + +//------------------------------------------------------------------------------------------------------------------- +// תΪ ASCII ֵ +// ˵ dat +// ˵ *p ݻ +// ˵ neg_type +// ˵ radix +// ز uint8 +// ʹʾ number_conversion_ascii((uint32)ival, vstr, 1, 10); +// עϢ ļڲ ûùע Ҳ޸ +//------------------------------------------------------------------------------------------------------------------- +static uint8 number_conversion_ascii (uint32 dat, int8 *p, uint8 neg_type, uint8 radix) +{ + int32 neg_dat; + uint32 pos_dat; + uint8 temp_data = 0; + uint8 valid_num = 0; + + if(neg_type) + { + neg_dat = (int32)dat; + if(0 > neg_dat) + { + neg_dat = -neg_dat; + } + while(1) + { + *p = neg_dat%radix + '0'; + neg_dat = neg_dat/radix; + valid_num ++; + + if(!neg_dat) + { + break; + } + p ++; + } + } + else + { + pos_dat = dat; + while(1) + { + temp_data = pos_dat%radix; + if(10 <= temp_data) + { + temp_data += 'A'-10; + } + else + { + temp_data += '0'; + } + + *p = temp_data; + + pos_dat = pos_dat/radix; + valid_num ++; + + if(!pos_dat) + { + break; + } + p ++; + } + } + return valid_num; +} + +//------------------------------------------------------------------------------------------------------------------- +// printf ʾת +// ˵ *d_buff +// ˵ len +// ز void +// ʹʾ printf_reverse_order(vstr, vlen); +// עϢ ļڲ ûùע Ҳ޸ +//------------------------------------------------------------------------------------------------------------------- +static void printf_reverse_order (int8 *d_buff, uint32 len) +{ + uint32 i; + int8 temp_data; + for(i = 0; len / 2 > i; i ++) + { + temp_data = d_buff[len - 1 - i]; + d_buff[len - 1 -i ] = d_buff[i]; + d_buff[i] = temp_data; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// sprintf ʵ +// ˵ *buff +// ˵ *format Դַ +// ˵ ... ɱб +// ز uint32 ݳ +// ʹʾ zf_sprintf(buff, "Data : %d", 100); +// עϢ ļڲ ûùע Ҳ޸ +//------------------------------------------------------------------------------------------------------------------- +uint32 zf_sprintf (int8 *buff, const int8 *format, ...) +{ + uint32 buff_len = 0; + va_list arg; + va_start(arg, format); + + while (*format) + { + int8 ret = *format; + if ('%' == ret) + { + switch (*++ format) + { + case 'a':// ʮp δʵ + { + } + break; + + case 'c':// һַ + { + int8 ch = (int8)va_arg(arg, uint32); + *buff = ch; + buff ++; + buff_len ++; + } + break; + + case 'd': + case 'i':// зʮ + { + int8 vstr[33]; + int32 ival = (int32)va_arg(arg, int32); + uint8 vlen = number_conversion_ascii((uint32)ival, vstr, 1, 10); + + if(0 > ival) + { + vstr[vlen] = '-'; + vlen ++; + } + printf_reverse_order(vstr, vlen); + memcpy(buff, vstr, vlen); + buff += vlen; + buff_len += vlen; + } + break; + + case 'f':// Сλ ָ + case 'F':// Сλ ָ + { + int8 vstr[33]; + double ival = (double)va_arg(arg, double); + uint8 vlen = number_conversion_ascii((uint32)(int32)ival, vstr, 1, 10); + + if(0 > ival) + { + vstr[vlen] = '-'; + vlen ++; + } + printf_reverse_order(vstr, vlen); + memcpy(buff, vstr, vlen); + buff += vlen; + buff_len += vlen; + + ival = ((double)ival - (int32)ival)*1000000; + if(ival) + { + vlen = number_conversion_ascii((uint32)(int32)ival, vstr, 1, 10); + } + else + { + vstr[0] = vstr[1] = vstr[2] = vstr[3] = vstr[4] = vstr[5] = '0'; + vlen = 6; + } + + while(6 > vlen) + { + vstr[vlen] = '0'; + vlen ++; + } + + vstr[vlen] = '.'; + vlen ++; + + printf_reverse_order(vstr, vlen); + memcpy(buff, vstr, vlen); + buff += vlen; + buff_len += vlen; + } + break; + + case 'u':// ޷ʮ + { + int8 vstr[33]; + uint32 ival = (uint32)va_arg(arg, uint32); + uint8 vlen = number_conversion_ascii(ival, vstr, 0, 10); + + printf_reverse_order(vstr, vlen); + memcpy(buff, vstr, vlen); + buff += vlen; + buff_len += vlen; + } + break; + + case 'o':// ޷Ű˽ + { + int8 vstr[33]; + uint32 ival = (uint32)va_arg(arg, uint32); + uint8 vlen = number_conversion_ascii(ival, vstr, 0, 8); + + printf_reverse_order(vstr, vlen); + memcpy(buff, vstr, vlen); + buff += vlen; + buff_len += vlen; + + } + break; + + case 'x':// ޷ʮ + case 'X':// ޷ʮ + { + int8 vstr[33]; + uint32 ival = (uint32)va_arg(arg, uint32); + uint8 vlen = number_conversion_ascii(ival, vstr, 0, 16); + + printf_reverse_order(vstr, vlen); + memcpy(buff, vstr, vlen); + buff += vlen; + buff_len += vlen; + } + break; + + case 's':// ַ + { + int8 *pc = va_arg(arg, int8 *); + while (*pc) + { + *buff = *pc; + buff ++; + buff_len ++; + pc ++; + } + } + break; + + case 'p':// 16ʽָ + { + int8 vstr[33]; + uint32 ival = (uint32)va_arg(arg, uint32); + //uint8 vlen = number_conversion_ascii(ival, vstr, 0, 16); + number_conversion_ascii(ival, vstr, 0, 16); + printf_reverse_order(vstr, 8); + memcpy(buff, vstr, 8); + buff += 8; + buff_len += 8; + } + break; + + case '%':// ַ% + { + *buff = '%'; + buff ++; + buff_len ++; + } + break; + + default: + break; + } + } + else + { + *buff = (int8)(*format); + buff ++; + buff_len ++; + } + format ++; + } + va_end(arg); + + return buff_len; +} + + diff --git a/libraries/zf_common/zf_common_function.h b/libraries/zf_common/zf_common_function.h new file mode 100644 index 0000000..4837db3 --- /dev/null +++ b/libraries/zf_common/zf_common_function.h @@ -0,0 +1,97 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_common_function +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* s ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_common_function_h_ +#define _zf_common_function_h_ + +#include "zf_common_typedef.h" + +//====================================================궨庯==================================================== +//------------------------------------------------------------------------------------------------------------------- +// ֵ ݷΧ [-32767,32767] +// ˵ dat Ҫֵ +// ز int ؾֵ +// ʹʾ dat = func_abs(dat); // dat +// עϢ +//------------------------------------------------------------------------------------------------------------------- +#define func_abs(x) ((x) >= 0 ? (x): -(x)) + +//------------------------------------------------------------------------------------------------------------------- +// ޷ ݷΧ [-32768,32767] +// ˵ x ޷ +// ˵ y ޷Χ(ݻᱻ-y+y֮) +// ز int ޷֮ +// ʹʾ int dat = func_limit(500, 300); // ݱ-300+300֮ ˷صĽ300 +// עϢ +//------------------------------------------------------------------------------------------------------------------- +#define func_limit(x, y) ((x) > (y) ? (y) : ((x) < -(y) ? -(y) : (x))) + +//------------------------------------------------------------------------------------------------------------------- +// ˫޷ ݷΧ [-32768,32767] +// ˵ x ޷ +// ˵ a ޷Χ߽ +// ˵ b ޷Χұ߽ +// ز int ޷֮ +// ʹʾ int dat = func_limit_ab(500, -300, 400); //ݱ-300+400֮ ˷صĽ400 +// עϢ +//------------------------------------------------------------------------------------------------------------------- +#define func_limit_ab(x, a, b) ((x) < (a) ? (a) : ((x) > (b) ? (b) : (x))) + + + + + +//====================================================궨庯==================================================== + +//=====================================================溯===================================================== +uint32 func_get_greatest_common_divisor (uint32 num1, uint32 num2); + +void func_soft_delay (volatile long t); + +int32 func_str_to_int (char *str); +void func_int_to_str (char *str, int32 number); +uint32 func_str_to_uint (char *str); +void func_uint_to_str (char *str, uint32 number); +float func_str_to_float (char *str); +void func_float_to_str (char *str, float number, uint8 point_bit); +double func_str_to_double (char *str); +void func_double_to_str (char *str, double number, uint8 point_bit); +uint32 func_str_to_hex (char *str); +void func_hex_to_str (char *str, uint32 number); + +uint32 zf_sprintf (int8 *buff, const int8 *format, ...); +//=====================================================溯===================================================== + +#endif diff --git a/libraries/zf_common/zf_common_headfile.h b/libraries/zf_common/zf_common_headfile.h new file mode 100644 index 0000000..538701a --- /dev/null +++ b/libraries/zf_common/zf_common_headfile.h @@ -0,0 +1,146 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_common_headfile +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef __HEADFILE_H +#define __HEADFILE_H + + + + +#include "stdio.h" +#include "stdint.h" +#include "string.h" + + + +//===================================================оƬ SDK ײ=================================================== +#include "ch32v30x_adc.h" +#include "ch32v30x_bkp.h" +#include "ch32v30x_can.h" +#include "ch32v30x_crc.h" +#include "ch32v30x_dac.h" +#include "ch32v30x_dbgmcu.h" +#include "ch32v30x_dma.h" +#include "ch32v30x_exti.h" +#include "ch32v30x_flash.h" +#include "ch32v30x_fsmc.h" +#include "ch32v30x_gpio.h" +#include "ch32v30x_i2c.h" +#include "ch32v30x_iwdg.h" +#include "ch32v30x_pwr.h" +#include "ch32v30x_rcc.h" +#include "ch32v30x_rtc.h" +#include "ch32v30x_sdio.h" +#include "ch32v30x_spi.h" +#include "ch32v30x_tim.h" +#include "ch32v30x_usart.h" +#include "ch32v30x_wwdg.h" + + +//===================================================оƬ SDK ײ=================================================== + +//====================================================Դ⹫==================================================== +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_common_font.h" +#include "zf_common_function.h" +#include "zf_common_interrupt.h" +#include "zf_common_fifo.h" +#include "zf_common_typedef.h" +//====================================================Դ⹫==================================================== + +//===================================================оƬ=================================================== +#include "zf_driver_adc.h" +#include "zf_driver_delay.h" +#include "zf_driver_dvp.h" +#include "zf_driver_encoder.h" +#include "zf_driver_exti.h" +#include "zf_driver_flash.h" +#include "zf_driver_gpio.h" +//#include "zf_driver_iic.h" +#include "zf_driver_pit.h" +#include "zf_driver_pwm.h" +//#include "zf_driver_soft_iic.h" +//#include "zf_driver_soft_spi.h" +#include "zf_driver_spi.h" +#include "zf_driver_timer.h" +#include "zf_driver_uart.h" +#include "zf_driver_usb_cdc.h" + +//===================================================оƬ=================================================== + +//===================================================豸=================================================== +#include "zf_device_camera.h" +#include "zf_device_icm20602.h" +#include "zf_device_ips114.h" +#include "zf_device_tft180.h" +#include "zf_device_ips200.h" +#include "zf_device_mt9v03x_dvp.h" +#include "zf_device_mpu6050.h" +#include "zf_device_type.h" +#include "zf_device_wireless_uart.h" +#include "zf_device_oled.h" +#include "zf_device_scc8660_dvp.h" +#include "zf_device_bluetooth_ch9141.h" +#include "zf_device_wireless_ch573.h" +#include "zf_device_wireless_uart.h" +#include "zf_device_virtual_oscilloscope.h" +#include "zf_device_w25q32.h" +#include "zf_device_k24c02.h" +#include "zf_device_aht20.h" +#include "zf_device_wifi_uart.h" +#include "zf_device_imu660ra.h" +#include "zf_device_imu963ra.h" +#include "zf_device_key.h" +#include "zf_device_gps_tau1201.h" +#include "zf_device_dl1a.h" +#include "zf_device_dm1xa.h" +#include "zf_device_wifi_spi.h" +#include "zf_device_detector.h" +#include "zf_device_dl1b.h" + +//===================================================豸=================================================== + + +//===================================================Ӧ=================================================== + +//===================================================Ӧ=================================================== + +//===================================================ûԶļ=================================================== + +//===================================================ûԶļ=================================================== + +#endif + diff --git a/libraries/zf_common/zf_common_interrupt.c b/libraries/zf_common/zf_common_interrupt.c new file mode 100644 index 0000000..de6db0b --- /dev/null +++ b/libraries/zf_common/zf_common_interrupt.c @@ -0,0 +1,135 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_common_interrupt +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + + +#include "zf_common_interrupt.h" + +static uint32 interrupt_nest_count = 0; + + +//------------------------------------------------------------------------------------------------------------------- +// ָжʹ +// ˵ irqn ָжϺ ɲ鿴 isr.c ӦжϷıע +// ز void +// ʹʾ interrupt_enable(UART1_IRQn); +//------------------------------------------------------------------------------------------------------------------- +void interrupt_enable (IRQn_Type irqn) +{ + NVIC_EnableIRQ(irqn); +} + +//------------------------------------------------------------------------------------------------------------------- +// ָж +// ˵ irqn ָжϺ ɲ鿴 isr.c ӦжϷıע +// ز void +// ʹʾ interrupt_disable(UART1_IRQn); +//------------------------------------------------------------------------------------------------------------------- +void interrupt_disable (IRQn_Type irqn) +{ + NVIC_DisableIRQ(irqn); +} + +//------------------------------------------------------------------------------------------------------------------- +// ָжȼ +// ˵ irqn ָжϺ ɲ鿴 isr.c ӦжϷıע +// ˵ priority bit7-bit5Ϊռȼbit4-bit0ΪȼֵԽȼԽ +// ز void +// ʹʾ interrupt_enable(UART1_IRQn, (1<<5) | 2); +// ռȼΪ1,ȼΪ2 +// ֹch32v30x_miscĺ +//------------------------------------------------------------------------------------------------------------------- +void interrupt_set_priority (IRQn_Type irqn, uint8 priority) +{ + NVIC_SetPriority(irqn, priority); +} + +////------------------------------------------------------------------------------------------------------------------- +//// @brief жʼ clock_init ڲ +//// @param void +//// @return void +//// Sample usage: interrupt_init(); +////------------------------------------------------------------------------------------------------------------------- +//void interrupt_init (void) +//{ +// NVIC_PriorityGroupConfig(4); +// +//} + +//------------------------------------------------------------------------------------------------------------------- +// ȫжʹ +// ˵ void ԭǶײ 0 ֱǶײж +// ز void +// ʹʾ interrupt_global_enable(); +//------------------------------------------------------------------------------------------------------------------- +void interrupt_global_enable (uint32 primask) +{ + if(primask) + { + interrupt_nest_count --; + } + if(!interrupt_nest_count) + { + __enable_irq(); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// ȫж +// ˵ void +// ز void +// ʹʾ interrupt_disable_all(); +//------------------------------------------------------------------------------------------------------------------- +uint32 interrupt_global_disable (void) +{ + + if(!interrupt_nest_count) + { + __disable_irq(); + } + interrupt_nest_count ++; + return interrupt_nest_count; +} + +//------------------------------------------------------------------------------------------------------------------- +// жϳʼ +// ˵ void +// ز void +// ʹʾ interrupt_init(); +// עϢ clock_init ڲ +//------------------------------------------------------------------------------------------------------------------- +void interrupt_init (void) +{ + interrupt_global_enable(0); //ʹȫж +} diff --git a/libraries/zf_common/zf_common_interrupt.h b/libraries/zf_common/zf_common_interrupt.h new file mode 100644 index 0000000..6436062 --- /dev/null +++ b/libraries/zf_common/zf_common_interrupt.h @@ -0,0 +1,51 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_common_interrupt +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_nvic_h +#define _zf_nvic_h + +#include "ch32v30x.h" +#include "zf_common_typedef.h" + + + +void interrupt_init (void); +void interrupt_global_enable (uint32 primask); +uint32 interrupt_global_disable (void); +void interrupt_enable (IRQn_Type irqn); +void interrupt_disable (IRQn_Type irqn); +void interrupt_set_priority (IRQn_Type irqn, uint8 priority); + +#endif diff --git a/libraries/zf_common/zf_common_typedef.h b/libraries/zf_common/zf_common_typedef.h new file mode 100644 index 0000000..6778a29 --- /dev/null +++ b/libraries/zf_common/zf_common_typedef.h @@ -0,0 +1,82 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_common_typedef +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_common_typedef_h_ +#define _zf_common_typedef_h_ + +#include "stdio.h" +#include "stdint.h" +#include "stdbool.h" +#include "stdarg.h" +#include "string.h" +#include "stdlib.h" + +//=================================================== Ͷ =================================================== + +//#define COMPATIBLE_WITH_OLDER_VERSIONS // ݾɰ濪Դӿ +#define USE_ZF_TYPEDEF (1) // ǷͶ +#if USE_ZF_TYPEDEF +// +// ʹ stdint.h ͻ Բü +typedef unsigned char uint8; // ޷ 8 bits +typedef unsigned short int uint16; // ޷ 16 bits +typedef unsigned int uint32; // ޷ 32 bits +typedef unsigned long long uint64; // ޷ 64 bits + +typedef signed char int8; // з 8 bits +typedef signed short int int16; // з 16 bits +typedef signed int int32; // з 32 bits +typedef signed long long int64; // з 64 bits + +typedef volatile uint8 vuint8; // ױ ޷ 8 bits +typedef volatile uint16 vuint16; // ױ ޷ 16 bits +typedef volatile uint32 vuint32; // ױ ޷ 32 bits +typedef volatile uint64 vuint64; // ױ ޷ 64 bits + +typedef volatile int8 vint8; // ױ з 8 bits +typedef volatile int16 vint16; // ױ з 16 bits +typedef volatile int32 vint32; // ױ з 32 bits +typedef volatile int64 vint64; // ױ з 64 bits + +#define ZF_ENABLE (1) +#define ZF_DISABLE (0) + +#define ZF_TRUE (1) +#define ZF_FALSE (0) +#endif + +//=================================================== Ͷ =================================================== + +#endif diff --git a/libraries/zf_device/libzf_device_config.a b/libraries/zf_device/libzf_device_config.a new file mode 100644 index 0000000..9fd9a2a Binary files /dev/null and b/libraries/zf_device/libzf_device_config.a differ diff --git a/libraries/zf_device/zf_device_absolute_encoder.c b/libraries/zf_device/zf_device_absolute_encoder.c new file mode 100644 index 0000000..fbaa55b --- /dev/null +++ b/libraries/zf_device/zf_device_absolute_encoder.c @@ -0,0 +1,230 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_absolute_encoder +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶: +* ------------------------------------ +* ģܽ Ƭܽ +* SCLK 鿴 zf_device_absolute_encoder.h ABSOLUTE_ENCODER_SCLK_PIN 궨 +* MOSI 鿴 zf_device_absolute_encoder.h ABSOLUTE_ENCODER_MOSI_PIN 궨 +* MISO 鿴 zf_device_absolute_encoder.h ABSOLUTE_ENCODER_MISO_PIN 궨 +* CS 鿴 zf_device_absolute_encoder.h ABSOLUTE_ENCODER_CS_PIN 궨 +* VCC 3.3VԴ +* GND Դ +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_common_function.h" +#include "zf_driver_delay.h" +#include "zf_driver_soft_spi.h" +#include "zf_driver_spi.h" + +#include "zf_device_absolute_encoder.h" + +static int16 now_location = 0; +static int16 last_location = 0; + +#if ABSOLUTE_ENCODER_USE_SOFT_SPI +static soft_spi_info_struct absolute_encoder_spi; +#define absolute_encoder_read() (soft_spi_read_8bit(&absolute_encoder_spi)) +#define absolute_encoder_write(data) (soft_spi_write_8bit(&absolute_encoder_spi, (data))) +#else +#define absolute_encoder_read() (spi_read_8bit(ABSOLUTE_ENCODER_SPI)) +#define absolute_encoder_write(data) (spi_write_8bit(ABSOLUTE_ENCODER_SPI, (data))) +#endif + +//------------------------------------------------------------------------------------------------------------------- +// ֵдĴ +// ˵ reg Ĵַ +// ˵ data +// ز void +// ʹʾ absolute_encoder_write_register(i + 1, dat[i]); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static void absolute_encoder_write_register(uint8 reg, uint8 data) +{ + ABSOLUTE_ENCODER_CSN(0); // Ƭѡѡ + absolute_encoder_write(reg | ABSOLUTE_ENCODER_SPI_W); // Ĵ + absolute_encoder_write(data); // + ABSOLUTE_ENCODER_CSN(1); // Ƭѡͷ + system_delay_us(1); // Ҫ + ABSOLUTE_ENCODER_CSN(0); // Ƭѡѡ + absolute_encoder_read(); // ᷵дǷɹ ж + absolute_encoder_read(); // Ҫ + ABSOLUTE_ENCODER_CSN(1); // Ƭѡͷ +} + +//------------------------------------------------------------------------------------------------------------------- +// ֵĴ ڲ +// ˵ reg Ĵַ +// ز uint8 +// ʹʾ absolute_encoder_read_register(6); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static uint8 absolute_encoder_read_register(uint8 reg) +{ + uint8 data = 0; + ABSOLUTE_ENCODER_CSN(0); // Ƭѡѡ + absolute_encoder_write(reg | ABSOLUTE_ENCODER_SPI_R); // Ĵ + absolute_encoder_write(0x00); // ռλ + ABSOLUTE_ENCODER_CSN(1); // Ƭѡͷ + system_delay_us(1); // Ҫ + ABSOLUTE_ENCODER_CSN(0); // Ƭѡѡ + data = absolute_encoder_read(); // ȡȡ + absolute_encoder_read(); // Ҫ + ABSOLUTE_ENCODER_CSN(1); // Ƭѡͷ + return data; +} + +//------------------------------------------------------------------------------------------------------------------- +// ֵλ ڲ +// ˵ void +// ز uint16 λֵ +// ʹʾ absolute_encoder_read_data(); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static uint16 absolute_encoder_read_data (void) +{ + uint16 data = 0; + ABSOLUTE_ENCODER_CSN(0); // Ƭѡѡ + data = absolute_encoder_read(); // ȡ߰λ + data = (data & 0x00FF) << 8; // λ + data |= absolute_encoder_read(); // ȡͰλ + ABSOLUTE_ENCODER_CSN(1); // Ƭѡͷ + return data; +} + +//------------------------------------------------------------------------------------------------------------------- +// ֵԼ ڲ +// ˵ void +// ز uint8 Լ״̬ +// ʹʾ absolute_encoder_self_check(); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static uint8 absolute_encoder_self_check (void) +{ + uint8 i = 0, return_state = 0; + uint8 dat[6] = {0, 0, 0, 0xC0, 0xFF, 0x1C}; + uint16 time_count = 0; + while(0x1C != absolute_encoder_read_register(6)) // ȡ״̬Ĵ + { + for(i = 0; i < 6; i ++) + { + absolute_encoder_write_register(i + 1, dat[i]); // дĬò + system_delay_ms(1); + } + if(time_count ++ > ABSOLUTE_ENCODER_TIMEOUT_COUNT) // ȴʱ + { + return_state = 1; + break; + } + } + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// ֵȡǰǶֵ +// ˵ void +// ز int16 Ƕֵ +// ʹʾ absolute_encoder_get_location(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +int16 absolute_encoder_get_location (void) +{ + last_location = now_location; + now_location = absolute_encoder_read_data() >> 4; + return now_location; +} + +//------------------------------------------------------------------------------------------------------------------- +// ֵȡϴλõƫֵ +// ˵ void +// ز int16 ƫֵ +// ʹʾ absolute_encoder_get_offset(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +int16 absolute_encoder_get_offset (void) +{ + int16 result_data = 0; + if(func_abs(now_location - last_location) > 2048) + { + result_data = (now_location > 2048 ? (now_location - 4096 - last_location) : (now_location + 4096 - last_location)); + } + else + { + result_data = (now_location - last_location); + } + return result_data; +} + +//------------------------------------------------------------------------------------------------------------------- +// ֵʼ +// ˵ void +// ز uint8 ʼ״̬ 0-ɹ 1-ʧ +// ʹʾ absolute_encoder_init(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 absolute_encoder_init (void) +{ + uint8 return_state = 0; + uint16 zero_position = ABSOLUTE_ENCODER_DEFAULT_ZERO; +#if ABSOLUTE_ENCODER_USE_SOFT_SPI + soft_spi_init(&absolute_encoder_spi, 0, ABSOLUTE_ENCODER_SOFT_SPI_DELAY, ABSOLUTE_ENCODER_SCLK_PIN, ABSOLUTE_ENCODER_MOSI_PIN, ABSOLUTE_ENCODER_MISO_PIN, SOFT_SPI_PIN_NULL); +#else + spi_init(ABSOLUTE_ENCODER_SPI, SPI_MODE0, ABSOLUTE_ENCODER_SPI_SPEED, ABSOLUTE_ENCODER_SCLK_PIN, ABSOLUTE_ENCODER_MOSI_PIN, ABSOLUTE_ENCODER_MISO_PIN, SPI_CS_NULL); +#endif + gpio_init(ABSOLUTE_ENCODER_CS_PIN, GPO, GPIO_LOW, GPO_PUSH_PULL); + + do + { + if(absolute_encoder_self_check()) + { + // ˶Ϣ ʾλ + // ôǾֵԼʱ˳ + // һ½û ûܾǻ + return_state = 1; + zf_log(0, "absolute encoder init errror."); + break; + } + absolute_encoder_write_register(ABSOLUTE_ENCODER_DIR_REG, 0x00); // ת תֵС0x00 תֵ0x80 + zero_position = (uint16)(4096 - zero_position); + zero_position = zero_position << 4; + absolute_encoder_write_register(ABSOLUTE_ENCODER_ZERO_L_REG, (uint8)zero_position); // λ + absolute_encoder_write_register(ABSOLUTE_ENCODER_ZERO_H_REG, zero_position >> 8); + }while(0); + return return_state; +} + diff --git a/libraries/zf_device/zf_device_absolute_encoder.h b/libraries/zf_device/zf_device_absolute_encoder.h new file mode 100644 index 0000000..f17d1b6 --- /dev/null +++ b/libraries/zf_device/zf_device_absolute_encoder.h @@ -0,0 +1,90 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_absolute_encoder +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶: +* ------------------------------------ +* ģܽ Ƭܽ +* SCLK 鿴 zf_device_absolute_encoder.h ABSOLUTE_ENCODER_SCLK_PIN 궨 +* MOSI 鿴 zf_device_absolute_encoder.h ABSOLUTE_ENCODER_MOSI_PIN 궨 +* MISO 鿴 zf_device_absolute_encoder.h ABSOLUTE_ENCODER_MISO_PIN 궨 +* CS 鿴 zf_device_absolute_encoder.h ABSOLUTE_ENCODER_CS_PIN 궨 +* VCC 3.3VԴ +* GND Դ +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_absolute_encoder_h_ +#define _zf_device_absolute_encoder_h_ + +#include "zf_common_typedef.h" + +#define ABSOLUTE_ENCODER_USE_SOFT_SPI (0) // ĬʹӲ SPI ʽ +#if ABSOLUTE_ENCODER_USE_SOFT_SPI // ɫIJȷ ɫҵľûõ +//==================================================== SPI ==================================================== +#define ABSOLUTE_ENCODER_SOFT_SPI_DELAY (1) // SPI ʱʱ ֵԽС SPI ͨԽ +#define ABSOLUTE_ENCODER_SCLK_PIN (B13) // Ӳ SPI SCK +#define ABSOLUTE_ENCODER_MOSI_PIN (B15) // Ӳ SPI MOSI +#define ABSOLUTE_ENCODER_MISO_PIN (B14) // Ӳ SPI MISO +//==================================================== SPI ==================================================== +#else +//====================================================Ӳ SPI ==================================================== +#define ABSOLUTE_ENCODER_SPI_SPEED (10 * 1000 * 1000) // Ӳ SPI +#define ABSOLUTE_ENCODER_SPI (SPI_2) // Ӳ SPI +#define ABSOLUTE_ENCODER_SCLK_PIN (SPI2_MAP0_SCK_B13) // Ӳ SPI SCK +#define ABSOLUTE_ENCODER_MOSI_PIN (SPI2_MAP0_MISO_B14) // Ӳ SPI MOSI +#define ABSOLUTE_ENCODER_MISO_PIN (SPI2_MAP0_MOSI_B15) // Ӳ SPI MISO +//====================================================Ӳ SPI ==================================================== +#endif + +#define ABSOLUTE_ENCODER_CS_PIN (B12) +#define ABSOLUTE_ENCODER_CSN(x) ((x) ? (gpio_high(ABSOLUTE_ENCODER_CS_PIN)): (gpio_low(ABSOLUTE_ENCODER_CS_PIN))) + +#define ABSOLUTE_ENCODER_TIMEOUT_COUNT (100) +#define ABSOLUTE_ENCODER_DEFAULT_ZERO (0) + +//====================================================Ƕȴ==================================================== +#define ABSOLUTE_ENCODER_SPI_W (0x80) +#define ABSOLUTE_ENCODER_SPI_R (0x40) + +#define ABSOLUTE_ENCODER_ZERO_L_REG (0x00) +#define ABSOLUTE_ENCODER_ZERO_H_REG (0x01) +#define ABSOLUTE_ENCODER_DIR_REG (0X09) +//====================================================Ƕȴ==================================================== + +int16 absolute_encoder_get_location (void); +int16 absolute_encoder_get_offset (void); +uint8 absolute_encoder_init (void); + +#endif diff --git a/libraries/zf_device/zf_device_aht20.c b/libraries/zf_device/zf_device_aht20.c new file mode 100644 index 0000000..95fbe27 --- /dev/null +++ b/libraries/zf_device/zf_device_aht20.c @@ -0,0 +1,150 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_aht20 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶: +* ------------------------------------ +* ģܽ Ƭܽ +* IIC ͨŶӦϵ +* SCL 鿴 zf_device_aht20.h AHT20_SOFT_IIC_SCL 궨 +* SDA 鿴 zf_device_aht20.h AHT20_SOFT_IIC_SDA 궨 +* VCC 3.3VԴ +* GND Դ +* +* +* Ӳ IIC ͨŶӦϵ +* SCL 鿴 zf_device_aht20.h AHT20_IIC_SCL 궨 +* SDA 鿴 zf_device_aht20.h AHT20_IIC_SDA 궨 +* VCC 3.3VԴ +* GND Դ +* +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_device_aht20.h" + +float aht_temperature = 0, aht_humidity = 0; + +#if AHT20_USE_SOFT_IIC +static soft_iic_info_struct aht20_iic_struct; + +#define aht20_write_register(reg, data) (soft_iic_write_8bit_register(&aht20_iic_struct, (reg), (data))) +#define aht20_write_registers(reg, data, len) (soft_iic_write_8bit_registers(&aht20_iic_struct, (reg), (data), (len))) +#define aht20_read_register(reg) (soft_iic_read_8bit_register(&aht20_iic_struct, (reg))) +#define aht20_read_registers(reg, data, len) (soft_iic_read_8bit_registers(&aht20_iic_struct, (reg), (data), (len))) +#else +#define aht20_write_register(reg, data) (iic_write_8bit_register(AHT20_IIC, AHT20_DEV_ADDR, (reg), (data))) +#define aht20_write_registers(reg, data, len) (iic_write_8bit_registers(AHT20_IIC, AHT20_DEV_ADDR, (reg), (data), (len))) +#define aht20_read_register(reg) (iic_read_8bit_register(AHT20_IIC, AHT20_DEV_ADDR, (reg))) +#define aht20_read_registers(reg, data, len) (iic_read_8bit_registers(AHT20_IIC, AHT20_DEV_ADDR, (reg), (data), (len))) +#endif + +//------------------------------------------------------------------------------------------------------------------- +// AHT20 Լ캯 +// ˵ NULL +// ز uint8 0 - ʼɹ 1 - ʼʧ +// ʹʾ øúǰȵģIICijʼ +//------------------------------------------------------------------------------------------------------------------- +static uint8 aht20_self1_check(void) +{ + uint8 return_state = 0; + uint16 timeout_count = 0; + uint8 send_data[2] = {0x08, 0x00}; + while((AHT20_CAL_ENABLE & aht20_read_register(AHT20_READ_STATE)) != AHT20_CAL_ENABLE) + { + //ԭ¼ + //1 AHT20 ˣµĸʼ + //2 ߴûнӺ + //3 Ҫ裬3.3V + aht20_write_registers(AHT20_SELF_INIT, send_data, 2); + system_delay_ms(10); + if(timeout_count ++ > AHT20_TIMEOUT_COUNT) + { + return_state = 1; + break; + } + } + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// ȡ AHT20 ʪ +// ˵ void +// ز void +// ʹʾ aht20_read_data(); // ִиúֱӲ鿴Ӧı +//------------------------------------------------------------------------------------------------------------------- +void aht20_read_data (void) +{ + uint32 temp_data; + uint8 data_buffer[6] = {0x33, 0x00, 0x00, 0x00, 0x00, 0x00}; + + aht20_write_registers(AHT20_MEASURE_CMD, data_buffer, 2); + system_delay_ms(75); + data_buffer[0] = AHT20_STATE_BUSY; + while(data_buffer[0] & aht20_read_register(AHT20_READ_STATE)) + { + system_delay_ms(1); + } + aht20_read_registers(AHT20_READ_STATE, data_buffer, 6); + + temp_data = data_buffer[1]; + temp_data = (temp_data << 8) + data_buffer[2]; + temp_data = (temp_data << 4) + (data_buffer[3]>>4 & 0x0f); + aht_humidity = ((double)temp_data/0x100000)*100; + + temp_data = (data_buffer[3] & 0x0f); + temp_data = (temp_data << 8) + data_buffer[4]; + temp_data = (temp_data << 8) + data_buffer[5]; + aht_temperature = ((double)temp_data/0x100000)*200-50; +} + +//------------------------------------------------------------------------------------------------------------------- +// ʼ AHT20 +// ˵ NULL +// ز uint8 0 - ʼɹ 1 - ʼʧ +// ʹʾ øúǰȵģIICijʼ +//------------------------------------------------------------------------------------------------------------------- +uint8 aht20_init (void) +{ + uint8 return_state = 0; +#if AHT20_USE_SOFT_IIC + soft_iic_init(&aht20_iic_struct, AHT20_DEV_ADDR, AHT20_SOFT_IIC_DELAY, AHT20_SCL_PIN, AHT20_SDA_PIN); +#else + iic_init(AHT20_IIC, AHT20_DEV_ADDR, AHT20_IIC_SPEED, AHT20_SCL_PIN, AHT20_SDA_PIN); +#endif + system_delay_ms(40); // ϵʱ + + return_state = aht20_self1_check(); + return return_state; +} diff --git a/libraries/zf_device/zf_device_aht20.h b/libraries/zf_device/zf_device_aht20.h new file mode 100644 index 0000000..a370059 --- /dev/null +++ b/libraries/zf_device/zf_device_aht20.h @@ -0,0 +1,100 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_aht20 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶: +* ------------------------------------ +* ģܽ Ƭܽ +* IIC ͨŶӦϵ +* SCL 鿴 zf_device_aht20.h AHT20_SOFT_IIC_SCL 궨 +* SDA 鿴 zf_device_aht20.h AHT20_SOFT_IIC_SDA 궨 +* VCC 3.3VԴ +* GND Դ +* +* +* Ӳ IIC ͨŶӦϵ +* SCL 鿴 zf_device_aht20.h AHT20_IIC_SCL 궨 +* SDA 鿴 zf_device_aht20.h AHT20_IIC_SDA 궨 +* VCC 3.3VԴ +* GND Դ +* +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_aht20_h_ +#define _zf_device_aht20_h_ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" + +#include "zf_driver_delay.h" + +#include "zf_driver_soft_iic.h" + +#define AHT20_USE_SOFT_IIC (1) // Ĭʹ IIC ʽ ʹ IIC ʽ +#if AHT20_USE_SOFT_IIC // ɫIJȷ ɫҵľûõ +//==================================================== IIC ==================================================== +#define AHT20_SOFT_IIC_DELAY (10 ) // IIC ʱʱ ֵԽС IIC ͨԽ +#define AHT20_SCL_PIN (B10) // IIC SCL MPU6050 SCL +#define AHT20_SDA_PIN (B11) // IIC SDA MPU6050 SDA +//==================================================== IIC ==================================================== +#else +//====================================================Ӳ IIC ==================================================== +#define AHT20_IIC_SPEED (400000 ) // Ӳ IIC ͨ 400KHz 40KHz +#define AHT20_IIC (IIC_2 ) // Ӳ IIC SCL MPU6050 SCL +#define AHT20_SCL_PIN (IIC2_SCL_B10) // Ӳ IIC SCL MPU6050 SCL +#define AHT20_SDA_PIN (IIC2_SDA_B11) // Ӳ IIC SDA MPU6050 SDA +//====================================================Ӳ IIC ==================================================== +#endif + +#define AHT20_TIMEOUT_COUNT (0x001F) // MPU6050 ʱ + +//================================================ AHT20 ڲַ================================================ +#define AHT20_DEV_ADDR (0x38) + +#define AHT20_READ_STATE (0x71) +#define AHT20_CAL_ENABLE (0x08) +#define AHT20_STATE_BUSY (0x80) + +#define AHT20_MEASURE_CMD (0xAC) + +#define AHT20_SELF_INIT (0xBE) +//================================================ AHT20 ڲַ================================================ + +extern float aht_temperature, aht_humidity; + +void aht20_read_data (void); +uint8 aht20_init (void); + +#endif diff --git a/libraries/zf_device/zf_device_bluetooth_ch9141.c b/libraries/zf_device/zf_device_bluetooth_ch9141.c new file mode 100644 index 0000000..4e36f5a --- /dev/null +++ b/libraries/zf_device/zf_device_bluetooth_ch9141.c @@ -0,0 +1,272 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_bluetooth_ch9141 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-01-10 W ԻCH1CH2ź +* 2022-03-16 W ɾԲʹλ +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶: +* ------------------------------------ +* ģܽ Ƭܽ +* TX 鿴 zf_device_bluetooth_ch9141.h BLUETOOTH_CH9141_TX_PIN 궨 +* RX 鿴 zf_device_bluetooth_ch9141.h BLUETOOTH_CH9141_RX_PIN 궨 +* RTS 鿴 zf_device_bluetooth_ch9141.h BLUETOOTH_CH9141_RTS_PIN 궨 +* VCC 3.3VԴ +* GND Դ +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_common_fifo.h" + +#include "zf_device_type.h" + +#include "zf_driver_gpio.h" +#include "zf_driver_uart.h" +#include "zf_driver_delay.h" + +#include "zf_device_bluetooth_ch9141.h" + +static fifo_struct bluetooth_ch9141_fifo; +static uint8 bluetooth_ch9141_buffer[BLUETOOTH_CH9141_BUFFER_SIZE]; // ݴ + +static uint8 bluetooth_ch9141_data; + +//------------------------------------------------------------------------------------------------------------------- +// תģ +// ˵ data 8bit +// ز uint32 ʣ෢ͳ +// ʹʾ bluetooth_ch9141_send_byte(0x5A); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 bluetooth_ch9141_send_byte (const uint8 data) +{ + uint16 time_count = BLUETOOTH_CH9141_TIMEOUT_COUNT; + while(time_count) + { + if(!gpio_get_level(BLUETOOTH_CH9141_RTS_PIN)) + { + uart_write_byte(BLUETOOTH_CH9141_INDEX, data); // + break; + } + time_count --; + system_delay_ms(1); + } + return (0 < time_count); +} + +//------------------------------------------------------------------------------------------------------------------- +// תģ ͺ +// ˵ buff Ҫ͵ݵַ +// ز len ͳ +// ʹʾ uint32 ʣδ͵ֽ +// ʹʾ bluetooth_ch9141_send_buff(buff, 16); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 bluetooth_ch9141_send_buffer (const uint8 *buff, uint32 len) +{ + zf_assert(buff != NULL); + uint16 time_count = 0; + while(0 != len) + { + if(!gpio_get_level(BLUETOOTH_CH9141_RTS_PIN)) // RTSΪ͵ƽ + { + if(30 <= len) // ݷ 30byte ÿ + { + uart_write_buffer(BLUETOOTH_CH9141_INDEX, buff, 30); // + buff += 30; // ַƫ + len -= 30; // + time_count = 0; + } + else // 30byte һԷ + { + uart_write_buffer(BLUETOOTH_CH9141_INDEX, buff, len); // + len = 0; + break; + } + } + else // RTSΪߵƽ ģæ + { + if(BLUETOOTH_CH9141_TIMEOUT_COUNT <= (++ time_count)) // ȴʱ + { + break; // ˳ + } + system_delay_ms(1); + } + } + return len; +} + +//------------------------------------------------------------------------------------------------------------------- +// תģ ַ +// ˵ *str Ҫ͵ַַ +// ز uint32 ʣ෢ͳ +// ʹʾ bluetooth_ch9141_send_string("Trust yourself."); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 bluetooth_ch9141_send_string (const char *str) +{ + zf_assert(str != NULL); + uint16 time_count = 0; + uint32 len = strlen(str); + while(0 != len) + { + if(!gpio_get_level(BLUETOOTH_CH9141_RTS_PIN)) // RTSΪ͵ƽ + { + if(30 <= len) // ݷ 30byte ÿ + { + uart_write_buffer(BLUETOOTH_CH9141_INDEX, (const uint8 *)str, 30); // + str += 30; // ַƫ + len -= 30; // + time_count = 0; + } + else // 30byte һԷ + { + uart_write_buffer(BLUETOOTH_CH9141_INDEX, (const uint8 *)str, len);// + len = 0; + break; + } + } + else // RTSΪߵƽ ģæ + { + if(BLUETOOTH_CH9141_TIMEOUT_COUNT <= (++ time_count)) // ȴʱ + { + break; // ˳ + } + system_delay_ms(1); + } + } + return len; +} + +//------------------------------------------------------------------------------------------------------------------- +// תģ ͷͼλ鿴ͼ +// ˵ *image_addr Ҫ͵ͼַ +// ˵ image_size ͼĴС +// ز void +// ʹʾ bluetooth_ch9141_send_image(&mt9v03x_image[0][0], MT9V03X_IMAGE_SIZE); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void bluetooth_ch9141_send_image (const uint8 *image_addr, uint32 image_size) +{ + zf_assert(image_addr != NULL); + uint16 time_count = 0; + + extern uint8 camera_send_image_frame_header[4]; + bluetooth_ch9141_send_buffer(camera_send_image_frame_header, 4); + bluetooth_ch9141_send_buffer((uint8 *)image_addr, image_size); + + while(0 != image_size) + { + if(!gpio_get_level(BLUETOOTH_CH9141_RTS_PIN)) // RTSΪ͵ƽ + { +// system_delay_ms(5); + if(30 <= image_size) // ݷ 30byte ÿ + { + uart_write_buffer(BLUETOOTH_CH9141_INDEX, image_addr, 30); // + image_addr += 30; // ַƫ + image_size -= 30; // + time_count = 0; + } + else // 30byte һԷ + { + uart_write_buffer(BLUETOOTH_CH9141_INDEX, image_addr, image_size);// + image_size = 0; + break; + } + } + else // RTSΪߵƽ ģæ + { + if(BLUETOOTH_CH9141_TIMEOUT_COUNT <= (++ time_count)) // ȴʱ + { + break; // ˳ + } + system_delay_ms(1); + } + } +} + +//------------------------------------------------------------------------------------------------------------------- +// תģ ȡ +// ˵ buff 洢ݵַ +// ˵ len +// ز uint32 ʵʶȡֽ +// ʹʾ bluetooth_ch9141_read_buff(buff, 16); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 bluetooth_ch9141_read_buffer (uint8 *buff, uint32 len) +{ + zf_assert(buff != NULL); + uint32 data_len = len; + fifo_read_buffer(&bluetooth_ch9141_fifo, buff, &data_len, FIFO_READ_AND_CLEAN); + return data_len; +} + +//------------------------------------------------------------------------------------------------------------------- +// תģ жϻص +// ˵ void +// ز void +// ʹʾ +// עϢ ú ISR ļĴжϳ򱻵 +// ɴжϷ wireless_module_uart_handler() +// wireless_module_uart_handler() ñ +//------------------------------------------------------------------------------------------------------------------- +void bluetooth_ch9141_uart_callback (void) +{ + uart_query_byte(BLUETOOTH_CH9141_INDEX, &bluetooth_ch9141_data); // ȡ + fifo_write_buffer(&bluetooth_ch9141_fifo, &bluetooth_ch9141_data, 1); // FIFO +} + +//------------------------------------------------------------------------------------------------------------------- +// תģ ʼ +// ˵ void +// ز uint8 ʼ״̬ 0-ɹ 1-ʧ +// ʹʾ bluetooth_ch9141_init(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 bluetooth_ch9141_init (void) +{ + uint8 return_state = 0; + set_wireless_type(BLUETOOTH_CH9141, bluetooth_ch9141_uart_callback); + + fifo_init(&bluetooth_ch9141_fifo, FIFO_DATA_8BIT, bluetooth_ch9141_buffer, BLUETOOTH_CH9141_BUFFER_SIZE); + // ʹõIJΪ115200 ΪתģĬϲ ʹλ޸ģ + gpio_init(BLUETOOTH_CH9141_RTS_PIN, GPI, 1, GPI_PULL_UP); // ʼ + uart_init(BLUETOOTH_CH9141_INDEX, BLUETOOTH_CH9141_BUAD_RATE, BLUETOOTH_CH9141_RX_PIN, BLUETOOTH_CH9141_TX_PIN); + uart_rx_interrupt(BLUETOOTH_CH9141_INDEX, 1); + + return return_state; +} + + diff --git a/libraries/zf_device/zf_device_bluetooth_ch9141.h b/libraries/zf_device/zf_device_bluetooth_ch9141.h new file mode 100644 index 0000000..82cb20f --- /dev/null +++ b/libraries/zf_device/zf_device_bluetooth_ch9141.h @@ -0,0 +1,75 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_bluetooth_ch9141 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-01-10 W ԻCH1CH2ź +* 2022-03-16 W ɾԲʹλ +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶: +* ------------------------------------ +* ģܽ Ƭܽ +* TX 鿴 zf_device_bluetooth_ch9141.h BLUETOOTH_CH9141_TX_PIN 궨 +* RX 鿴 zf_device_bluetooth_ch9141.h BLUETOOTH_CH9141_RX_PIN 궨 +* RTS 鿴 zf_device_bluetooth_ch9141.h BLUETOOTH_CH9141_RTS_PIN 궨 +* VCC 3.3VԴ +* GND Դ +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_bluetooth_ch9141_h_ +#define _zf_device_bluetooth_ch9141_h_ + +#include "zf_common_typedef.h" + +#define BLUETOOTH_CH9141_INDEX UART_7 // ģ 1 ӦʹõĴں +#define BLUETOOTH_CH9141_BUAD_RATE 115200 // ģ 1 ӦʹõĴڲ +#define BLUETOOTH_CH9141_TX_PIN UART7_MAP3_RX_E13 // ģ 1 Ӧģ TX ҪӵƬ RX +#define BLUETOOTH_CH9141_RX_PIN UART7_MAP3_TX_E12 // ģ 1 Ӧģ RX ҪӵƬ TX +#define BLUETOOTH_CH9141_RTS_PIN E8 // ģ 1 Ӧģ RTS + +#define BLUETOOTH_CH9141_BUFFER_SIZE 64 +#define BLUETOOTH_CH9141_TIMEOUT_COUNT 500 + + +uint32 bluetooth_ch9141_send_byte (const uint8 data); +uint32 bluetooth_ch9141_send_buffer (const uint8 *buff, uint32 len); +uint32 bluetooth_ch9141_send_string (const char *str); +void bluetooth_ch9141_send_image (const uint8 *image_addr, uint32 image_size); + +uint32 bluetooth_ch9141_read_buffer (uint8 *buff, uint32 len); + +void bluetooth_ch9141_uart_callback (void); + +uint8 bluetooth_ch9141_init (void); +#endif + diff --git a/libraries/zf_device/zf_device_camera.c b/libraries/zf_device/zf_device_camera.c new file mode 100644 index 0000000..c33888a --- /dev/null +++ b/libraries/zf_device/zf_device_camera.c @@ -0,0 +1,101 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_camera +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2021-12-02 W Ӵڷͼλ +* 2022-09-15 W first version +********************************************************************************************************************/ + + +#include "zf_common_debug.h" +#include "zf_common_interrupt.h" +#include "zf_driver_exti.h" +#include "zf_driver_timer.h" +#include "zf_device_type.h" +#include "zf_device_mt9v03x_dvp.h" +#include "zf_device_scc8660_dvp.h" + +#include "zf_device_camera.h" + + +uint8 camera_receiver_buffer[CAMERA_RECEIVER_BUFFER_SIZE]; + +uint8 camera_send_image_frame_header[4] = {0x00, 0xFF, 0x01, 0x01}; + + + +//------------------------------------------------------------------------------------------------------------------- +// ͷͼݽѹΪʮưλ С +// ˵ *data1 ͷͼ +// ˵ *data2 Žѹݵĵַ +// ˵ image_size ͼĴС +// ز void +// ʹʾ camera_binary_image_decompression(&ov7725_image_binary[0][0], &data_buffer[0][0], OV7725_SIZE); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void camera_binary_image_decompression (const uint8 *data1, uint8 *data2, uint32 image_size) +{ + zf_assert(data1 != NULL); + zf_assert(data2 != NULL); + uint8 i = 8; + + while(image_size --) + { + i = 8; + while(i --) + { + *data2 ++ = (((*data1 >> i) & 0x01) ? 255 : 0); + } + data1 ++; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// ͷͼλ鿴ͼ +// ˵ uartn ʹõĴں +// ˵ *image_addr Ҫ͵ͼַ +// ˵ image_size ͼĴС +// ز void +// ʹʾ camera_send_image(DEBUG_UART_INDEX, &mt9v03x_image[0][0], MT9V03X_IMAGE_SIZE); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void camera_send_image (uart_index_enum uartn, const uint8 *image_addr, uint32 image_size) +{ + zf_assert(image_addr != NULL); + // + uart_write_buffer(uartn, camera_send_image_frame_header, 4); + + // ͼ + uart_write_buffer(uartn, (uint8 *)image_addr, image_size); +} + + + diff --git a/libraries/zf_device/zf_device_camera.h b/libraries/zf_device/zf_device_camera.h new file mode 100644 index 0000000..9d9cbfa --- /dev/null +++ b/libraries/zf_device/zf_device_camera.h @@ -0,0 +1,53 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_camera +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2021-12-02 W Ӵڷͼλ +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_device_camera_h_ +#define _zf_device_camera_h_ + +#include "zf_common_fifo.h" +#include "zf_driver_uart.h" + +#define CAMERA_RECEIVER_BUFFER_SIZE (8) + +extern uint8 camera_receiver_buffer[CAMERA_RECEIVER_BUFFER_SIZE]; + +extern uint8 camera_send_image_frame_header[4]; + +void camera_binary_image_decompression (const uint8 *data1, uint8 *data2, uint32 image_size); +void camera_send_image (uart_index_enum uartn, const uint8 *image_addr, uint32 image_size); + + +#endif diff --git a/libraries/zf_device/zf_device_config.h b/libraries/zf_device/zf_device_config.h new file mode 100644 index 0000000..dfd6174 --- /dev/null +++ b/libraries/zf_device/zf_device_config.h @@ -0,0 +1,53 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_adc +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +#ifndef _zf_device_config_h_ +#define _zf_device_config_h_ + +extern const unsigned char image_frame_header[4]; +extern const unsigned char imu660ra_config_file[8192]; +extern const unsigned char dl1b_config_file[135]; + + +unsigned char mt9v03x_sccb_check_id (void *soft_iic_obj); +unsigned char mt9v03x_sccb_set_config (const short int buff[10][2]); +unsigned char mt9v03x_sccb_set_exposure_time (unsigned short int light); +unsigned char mt9v03x_sccb_set_reg (unsigned char addr, unsigned short int data); + +unsigned char scc8660_sccb_check_id (void *soft_iic_obj); +unsigned char scc8660_sccb_set_config (const short int buff[11][2]); +unsigned char scc8660_sccb_set_brightness (unsigned short int brightness); +unsigned char scc8660_sccb_set_manual_wb (unsigned short int manual_wb); +unsigned char scc8660_sccb_set_reg (unsigned char reg, unsigned short int data); +#endif diff --git a/libraries/zf_device/zf_device_detector.c b/libraries/zf_device/zf_device_detector.c new file mode 100644 index 0000000..d83c895 --- /dev/null +++ b/libraries/zf_device/zf_device_detector.c @@ -0,0 +1,628 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_wifi_spi +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2023-05-25 W first version +********************************************************************************************************************/ + +#include "zf_driver_uart.h" +#include "zf_common_fifo.h" +#include "zf_device_wireless_uart.h" +#include "zf_device_bluetooth_ch9141.h" +#include "zf_device_wifi_uart.h" +#include "zf_device_wifi_spi.h" + +#include "zf_device_detector.h" + + +typedef uint32 (*detector_transfer_callback_function) (const uint8 *buff, uint32 length); +typedef uint32 (*detector_receive_callback_function) (uint8 *buff, uint32 length); + +detector_transfer_type_enum detector_transfer_type; // ݴ䷽ʽ + +detector_transfer_callback_function detector_transfer_callback; // ݷͺָ +detector_receive_callback_function detector_receive_callback; // ݽպָ + +detector_oscilloscope_struct detector_oscilloscope_data; // ʾ +static detector_camera_struct detector_camera_data; // ͼλЭ +static detector_camera_dot_struct detector_camera_dot_data; // ͼλЭ +static detector_camera_buffer_struct detector_camera_buffer; // ͼԼ߽绺Ϣ + +static fifo_struct detector_fifo; +static uint8 detector_buffer[DETECTOR_BUFFER_SIZE]; // ݴ +float detector_parameter[DETECTOR_SET_PARAMETR_COUNT]; // յIJ + +////------------------------------------------------------------------------------------------------------------------- +//// δߴڷͺ +//// ˵ *buff Ҫ͵ݵַ +//// ˵ length Ҫ͵ij +//// ز uint32 ʣδݳ +//// ʹʾ +////------------------------------------------------------------------------------------------------------------------- +//uint32 detector_debug_uart_transfer (const uint8 *buff, uint32 length) +//{ +// uart_write_buffer(DEBUG_UART_INDEX, buff, length); +// return 0; +//} + +////------------------------------------------------------------------------------------------------------------------- +//// δߴڽպ +//// ˵ *buff Ҫյݵַ +//// ˵ length Ҫյij +//// ز uint32 ʵʽճ +//// ʹʾ +////------------------------------------------------------------------------------------------------------------------- +//uint32 detector_debug_uart_receive (uint8 *buff, uint32 length) +//{ +// return debug_read_ring_buffer(buff, length); +//} + +//------------------------------------------------------------------------------------------------------------------- +// δԶֽڷͺ +// ˵ data Ҫ͵ݵַ +// ز uint8 +// ʹʾ +//------------------------------------------------------------------------------------------------------------------- +static uint8 detector_custom_write_byte(const uint8 data) +{ + // ʵֽڷ + + return 0; +} + +//------------------------------------------------------------------------------------------------------------------- +// δԶ巢ͺ +// ˵ *buff Ҫ͵ݵַ +// ˵ length Ҫ͵ij +// ز uint32 ʣδݳ +// ʹʾ ݴ䷽ʽַ֧Χʵ +//------------------------------------------------------------------------------------------------------------------- +uint32 detector_custom_transfer (const uint8 *buff, uint32 length) +{ + uint32 send_length; + send_length = length; + + while(send_length--) + { + detector_custom_write_byte(*buff); + buff++; + } + + return send_length; +} + +//------------------------------------------------------------------------------------------------------------------- +// δԶպ ֽڽ +// ˵ *data Ҫ͵ݵַ +// ز uint8 0:ճɹ 1ʧ +// ע detector_custom_receive_byte detector_custom_receive ֻҪһ +//------------------------------------------------------------------------------------------------------------------- +uint8 detector_custom_receive_byte (uint8 data) +{ + uint8 return_state = 0; + // ʵֽڷ + if(FIFO_SUCCESS != fifo_write_buffer(&detector_fifo, &data, 1)) + { + return_state = 1; + } + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// δԶպ +// ˵ *buff Ҫ͵ݵַ +// ˵ length Ҫ͵ij +// ز uint8 0:ճɹ 1ʧ +// ע detector_custom_receive_byte detector_custom_receive ֻҪһ +//------------------------------------------------------------------------------------------------------------------- +uint8 detector_custom_receive (uint8 *buff, uint32 length) +{ + uint8 return_state = 0; + + // յдFIFO + if(FIFO_SUCCESS != fifo_write_buffer(&detector_fifo, buff, length)) + { + return_state = 1; + } + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// δͷͺ +// ˵ *send_data Ҫ͵ݵַ +// ˵ send_length Ҫ͵ij +// ز uint32 ʣδݳ +// ʹʾ +//------------------------------------------------------------------------------------------------------------------- +static uint32 detector_transfer (void *send_data, uint32 send_length) +{ + return detector_transfer_callback((const uint8 *)send_data, send_length); +} + +//------------------------------------------------------------------------------------------------------------------- +// δͺ +// ˵ *buffer ҪУݵַ +// ˵ length У鳤 +// ز uint8 ֵ +// ʹʾ +//------------------------------------------------------------------------------------------------------------------- +static uint8 detector_sum (uint8 *buffer, uint32 length) +{ + uint8 temp_sum = 0; + + while(length--) + { + temp_sum += *buffer++; + } + + return temp_sum; +} + + + +//------------------------------------------------------------------------------------------------------------------- +// δ ͼͺ +// ˵ camera_type ͷ +// ˵ *image_addr ͼ׵ַ +// ˵ boundary_num ͼа߽ +// ˵ width ͼ +// ˵ height ͼ߶ +// ز void +// ʹʾ +//------------------------------------------------------------------------------------------------------------------- +void detector_camera_data_send (detector_image_type_enum camera_type, void *image_addr, uint8 boundary_num, uint16 width, uint16 height) +{ + uint32 image_size = 0; + + detector_camera_data.head = DETECTOR_SEND_HEAD; + detector_camera_data.function = DETECTOR_CAMERA_FUNCTION; + detector_camera_data.camera_type = (camera_type << 5) | ((image_addr != NULL ? 0 : 1) << 4) | boundary_num; + // дϢЭ鲿 + detector_camera_data.length = sizeof(detector_camera_struct); + detector_camera_data.image_width = width; + detector_camera_data.image_height = height; + + // ȷ֡ͷܡͷ͡Լȸ߶ȵϢ + detector_transfer(&detector_camera_data, sizeof(detector_camera_struct)); + + // ͷͼͼС + switch(camera_type) + { + case DETECTOR_OV7725_BIN: + { + image_size = width * height / 8; + }break; + + case DETECTOR_MT9V03X: + { + image_size = width * height; + }break; + + case DETECTOR_SCC8660: + { + image_size = width * height * 2; + }break; + } + + // ͼ + if(NULL != image_addr) + { + detector_transfer(image_addr, image_size); + } + +} + +//------------------------------------------------------------------------------------------------------------------- +// δ ͼ߻ƺ +// ˵ boundary_id ID +// ˵ dot_num +// ˵ *dot_x ׵ַ +// ˵ *dot_y ׵ַ +// ˵ width ͼ +// ˵ height ͼ߶ +// ز void +// ʹʾ +//------------------------------------------------------------------------------------------------------------------- +void detector_camera_dot_send (detector_camera_buffer_struct *buffer) +{ + uint8 i; + uint16 dot_bytes = 0; // ֽ + wifi_spi_send_multi_struct multi_buffer; + + dot_bytes = detector_camera_dot_data.dot_num; + + if(detector_camera_dot_data.dot_type & (1 << 5)) + { + dot_bytes *= 2; + } + + // ߷ʱ WIFI SPIöԴַͺ,Լ߷ٶ + if(DETECTOR_WIFI_SPI == detector_transfer_type) + { + multi_buffer.source[0] = (uint8 *)&detector_camera_dot_data; + multi_buffer.length[0] = sizeof(detector_camera_dot_struct); + + for(i=0; i < DETECTOR_CAMERA_MAX_BOUNDARY; i++) + { + multi_buffer.source[i * 2 + 1] = buffer->boundary_x[i]; + multi_buffer.source[i * 2 + 2] = buffer->boundary_y[i]; + + multi_buffer.length[i * 2 + 1] = dot_bytes; + multi_buffer.length[i * 2 + 2] = dot_bytes; + } + + wifi_spi_send_buffer_multi(&multi_buffer); + } + else + { + // ȷ֡ͷܡ߽š곤ȡ + detector_transfer(&detector_camera_dot_data, sizeof(detector_camera_dot_struct)); + + for(i=0; i < DETECTOR_CAMERA_MAX_BOUNDARY; i++) + { + // жǷͺ + if(NULL != buffer->boundary_x[i]) + { + detector_transfer(buffer->boundary_x[i], dot_bytes); + } + + // жǷ + if(NULL != buffer->boundary_y[i]) + { + // ûݣʾÿһֻһ߽ + // ָ˺ݣַʽʵͬһж߽㷨ܹ䡣 + detector_transfer(buffer->boundary_y[i], dot_bytes); + } + } + } +} + +//------------------------------------------------------------------------------------------------------------------- +// δ ʾͺ +// ˵ *detector_oscilloscope ʾݽṹ +// ز void +// ʹʾ detector_oscilloscope_send(&detector_oscilloscope_data); +//------------------------------------------------------------------------------------------------------------------- +void detector_oscilloscope_send (detector_oscilloscope_struct *detector_oscilloscope) +{ + uint8 packet_size; + + // λ + detector_oscilloscope->channel_num &= 0x0f; + + zf_assert(DETECTOR_SET_OSCILLOSCOPE_COUNT >= detector_oscilloscope->channel_num); + + // ֡ͷ + detector_oscilloscope->head = DETECTOR_SEND_HEAD; + + // дϢ + packet_size = sizeof(detector_oscilloscope_struct) - (DETECTOR_SET_OSCILLOSCOPE_COUNT - detector_oscilloscope->channel_num) * 4; + detector_oscilloscope->length = packet_size; + + // д빦ͨ + detector_oscilloscope->channel_num |= DETECTOR_CAMERA_OSCILLOSCOPE; + + // У + detector_oscilloscope->check_sum = 0; + detector_oscilloscope->check_sum = detector_sum((uint8 *)&detector_oscilloscope_data, packet_size); + + // ڵñ֮ǰûҪ͵дdetector_oscilloscope_data.data[] + + detector_transfer((uint8 *)detector_oscilloscope, packet_size); +} + +//------------------------------------------------------------------------------------------------------------------- +// δͼϢú +// ˵ camera_type ͼ +// ˵ image_addr ͼַ NULLʾֻͱϢλ +// ˵ width ͼ +// ˵ height ͼ߶ +// ز void +// ʹʾ detector_camera_information_config(DETECTOR_MT9V03X, mt9v03x_image[0], MT9V03X_W, MT9V03X_H); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void detector_camera_information_config (detector_image_type_enum camera_type, void *image_addr, uint16 width, uint16 height) +{ + detector_camera_dot_data.head = DETECTOR_SEND_HEAD; + detector_camera_dot_data.function = DETECTOR_CAMERA_DOT_FUNCTION; + // дϢ + detector_camera_dot_data.length = sizeof(detector_camera_dot_struct); + + detector_camera_buffer.camera_type = camera_type; + detector_camera_buffer.image_addr = image_addr; + detector_camera_buffer.width = width; + detector_camera_buffer.height = height; +} + +//------------------------------------------------------------------------------------------------------------------- +// δͼ߷ú +// ˵ boundary_type ߽ +// ˵ dot_num һ߽жٸ +// ˵ dot_x1 ű1ĵַ NULLʾͱ1 +// ˵ dot_x2 ű2ĵַ NULLʾͱ2 +// ˵ dot_x3 ű3ĵַ NULLʾͱ3 +// ˵ dot_y1 ű1ĵַ NULLʾͱ1 +// ˵ dot_y2 ű2ĵַ NULLʾͱ2 +// ˵ dot_y3 ű3ĵַ NULLʾͱ3 +// ز void +// ʹʾ detector_camera_config(X_BOUNDARY, MT9V03X_H, x1_boundary, x2_boundary, x3_boundary, NULL, NULL, NULL); // ͼʱߣֻк +// ʹʾ detector_camera_config(Y_BOUNDARY, MT9V03X_W, NULL, NULL, NULL, y1_boundary, y2_boundary, y3_boundary); // ͼʱߣֻ +// ʹʾ detector_camera_config(XY_BOUNDARY, 160, xy_x1_boundary, xy_x2_boundary, xy_x3_boundary, xy_y1_boundary, xy_y2_boundary, xy_y3_boundary); // ͼʱߣ߰ +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void detector_camera_boundary_config (detector_boundary_type_enum boundary_type, uint16 dot_num, void *dot_x1, void *dot_x2, void *dot_x3, void *dot_y1, void *dot_y2, void *dot_y3) +{ + uint8 i = 0; + uint8 boundary_num = 0; + uint8 boundary_data_type = 0; + + // ͼͻǷ׼, ô˺֮ǰҪȵdetector_camera_configúͼϢ + zf_assert(0 != detector_camera_buffer.camera_type); + + detector_camera_dot_data.dot_num = dot_num; + + detector_camera_dot_data.valid_flag = 0; + for(i = 0; i < 3; i++) + { + detector_camera_buffer.boundary_x[i] = NULL; + detector_camera_buffer.boundary_y[i] = NULL; + } + + switch(boundary_type) + { + case X_BOUNDARY: + { + if(NULL != dot_x1) + { + boundary_num++; + detector_camera_dot_data.valid_flag |= 1 << 0; + detector_camera_buffer.boundary_x[i++] = dot_x1; + } + if(NULL != dot_x2) + { + boundary_num++; + detector_camera_dot_data.valid_flag |= 1 << 1; + detector_camera_buffer.boundary_x[i++] = dot_x2; + } + if(NULL != dot_x3) + { + boundary_num++; + detector_camera_dot_data.valid_flag |= 1 << 2; + detector_camera_buffer.boundary_x[i++] = dot_x3; + } + + if(255 < detector_camera_buffer.height) + { + boundary_data_type = 1; + } + }break; + + case Y_BOUNDARY: + { + if(NULL != dot_y1) + { + boundary_num++; + detector_camera_dot_data.valid_flag |= 1 << 0; + detector_camera_buffer.boundary_y[i++] = dot_y1; + } + if(NULL != dot_y2) + { + boundary_num++; + detector_camera_dot_data.valid_flag |= 1 << 1; + detector_camera_buffer.boundary_y[i++] = dot_y2; + } + if(NULL != dot_y3) + { + boundary_num++; + detector_camera_dot_data.valid_flag |= 1 << 2; + detector_camera_buffer.boundary_y[i++] = dot_y3; + } + + if(255 < detector_camera_buffer.width) + { + boundary_data_type = 1; + } + }break; + + case XY_BOUNDARY: + { + if((NULL != dot_x1) && (NULL != dot_y1)) + { + boundary_num++; + detector_camera_dot_data.valid_flag |= 1 << 0; + detector_camera_buffer.boundary_x[i] = dot_x1; + detector_camera_buffer.boundary_y[i++] = dot_y1; + } + if((NULL != dot_x2) && (NULL != dot_y2)) + { + boundary_num++; + detector_camera_dot_data.valid_flag |= 1 << 1; + detector_camera_buffer.boundary_x[i] = dot_x2; + detector_camera_buffer.boundary_y[i++] = dot_y2; + } + if((NULL != dot_x3) && (NULL != dot_y3)) + { + boundary_num++; + detector_camera_dot_data.valid_flag |= 1 << 2; + detector_camera_buffer.boundary_x[i] = dot_x3; + detector_camera_buffer.boundary_y[i++] = dot_y3; + } + + if((255 < detector_camera_buffer.width) || (255 < detector_camera_buffer.height)) + { + boundary_data_type = 1; + } + }break; + + case NO_BOUNDARY:break; + } + + detector_camera_dot_data.dot_type = (boundary_type << 6) | (boundary_data_type << 5) | boundary_num; +} + +//------------------------------------------------------------------------------------------------------------------- +// δͷͷͼ +// ˵ void +// ز void +// ʹʾ +// עϢ ڵͼͺ֮ǰصһdetector_camera_configӦIJú +//------------------------------------------------------------------------------------------------------------------- +void detector_camera_send (void) +{ + // ͼͻǷ׼ + zf_assert(0 != detector_camera_buffer.camera_type); + + detector_camera_data_send(detector_camera_buffer.camera_type, detector_camera_buffer.image_addr, detector_camera_dot_data.dot_type & 0x0f, detector_camera_buffer.width, detector_camera_buffer.height); + + if(detector_camera_dot_data.dot_type & 0x0f) + { + detector_camera_dot_send(&detector_camera_buffer); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// δͽյ +// ˵ void +// ز void +// ʹʾ ֻҪŵеPITжϻѭ +//------------------------------------------------------------------------------------------------------------------- +void detector_data_analysis (void) +{ + uint8 temp_sum; + uint32 read_length; + detector_parameter_struct *receive_packet; + + // ʹuint32ж壬ĿΪ˱ֽ֤ڶ + uint32 temp_buffer[DETECTOR_BUFFER_SIZE / 4]; + + // Զȡ, ԶĴ䷽ʽӽջصжȡ + if(DETECTOR_CUSTOM != detector_transfer_type) + { + read_length = detector_receive_callback((uint8 *)temp_buffer, DETECTOR_BUFFER_SIZE); + if(read_length) + { + // ȡдFIFO + fifo_write_buffer(&detector_fifo, (uint8 *)temp_buffer, read_length); + } + } + + while(sizeof(detector_parameter_struct) <= fifo_used(&detector_fifo)) + { + read_length = sizeof(detector_parameter_struct); + fifo_read_buffer(&detector_fifo, (uint8 *)temp_buffer, &read_length, FIFO_READ_ONLY); + + if(DETECTOR_RECEIVE_HEAD != ((uint8 *)temp_buffer)[0]) + { + // û֡ͷFIFOȥһ + read_length = 1; + } + else + { + // ҵ֡ͷ + receive_packet = (detector_parameter_struct *)temp_buffer; + temp_sum = receive_packet->check_sum; + receive_packet->check_sum = 0; + if(temp_sum == detector_sum((uint8 *)temp_buffer, sizeof(detector_parameter_struct))) + { + // Уɹ + detector_parameter[receive_packet->channel - 1] = receive_packet->data; + } + else + { + read_length = 1; + } + } + + // ʹõ + fifo_read_buffer(&detector_fifo, NULL, &read_length, FIFO_READ_AND_CLEAN); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// δ ʼ +// ˵ transfer_type ѡʹַʽ +// ز void +// ʹʾ +//------------------------------------------------------------------------------------------------------------------- +void detector_init (detector_transfer_type_enum transfer_type) +{ + detector_transfer_type = transfer_type; + + fifo_init(&detector_fifo, FIFO_DATA_8BIT, detector_buffer, DETECTOR_BUFFER_SIZE); + + switch(detector_transfer_type) + { + case DETECTOR_DEBUG_UART: + { + detector_transfer_callback = debug_send_buffer; + detector_receive_callback = debug_read_ring_buffer; + }break; + + case DETECTOR_WIRELESS_UART: + { + detector_transfer_callback = wireless_uart_send_buffer; + detector_receive_callback = wireless_uart_read_buffer; + }break; + + case DETECTOR_CH9141: + { + detector_transfer_callback = bluetooth_ch9141_send_buffer; + detector_receive_callback = bluetooth_ch9141_read_buffer; + }break; + + case DETECTOR_WIFI_UART: + { + detector_transfer_callback = wifi_uart_send_buffer; + detector_receive_callback = wifi_uart_read_buffer; + }break; + + case DETECTOR_WIFI_SPI: + { + detector_transfer_callback = wifi_spi_send_buffer; + detector_receive_callback = wifi_spi_read_buffer; + }break; + + case DETECTOR_CUSTOM: + { + // Լ ʵdetector_custom_write_byteݵĴ + detector_transfer_callback = detector_custom_transfer; + + // ýջص + + // ںʵλõdetector_custom_receive detector_custom_receive_byteʵݽ + // detector_custom_receive detector_custom_receive_byte ֻһɣԼǰֽڽݻǰݽ + // յݻᱻдdetector_fifoУ Աʹ + //detector_receive_callback = detector_custom_receive; + + }break; + } +} diff --git a/libraries/zf_device/zf_device_detector.h b/libraries/zf_device/zf_device_detector.h new file mode 100644 index 0000000..2b7dbd4 --- /dev/null +++ b/libraries/zf_device/zf_device_detector.h @@ -0,0 +1,173 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_wifi_spi +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2023-05-25 W first version +********************************************************************************************************************/ + +#ifndef _zf_device_detector_h_ +#define _zf_device_detector_h_ + +#include "zf_common_typedef.h" +#include "zf_common_debug.h" + +// FIFOС +#define DETECTOR_BUFFER_SIZE ( 0x40 ) + +// ʾͨ +#define DETECTOR_SET_OSCILLOSCOPE_COUNT ( 0x08 ) + +// Եͨ +#define DETECTOR_SET_PARAMETR_COUNT ( 0x08 ) + +// ͼ +#define DETECTOR_CAMERA_MAX_BOUNDARY ( 0x08 ) + +// Ƭλ͵֡ͷ +#define DETECTOR_SEND_HEAD ( 0xAA ) + +// ͷ +#define DETECTOR_CAMERA_FUNCTION ( 0x02 ) +#define DETECTOR_CAMERA_DOT_FUNCTION ( 0x03 ) +#define DETECTOR_CAMERA_OSCILLOSCOPE ( 0x10 ) + +// λƬ͵֡ͷ +#define DETECTOR_RECEIVE_HEAD ( 0x55 ) + +// +#define DETECTOR_RECEIVE_SET_PARAMETER ( 0x20 ) + + +// ݷ豸ö +typedef enum +{ + DETECTOR_DEBUG_UART, // Դ ʹõĴDEBUG_UART_INDEX궨ָ + DETECTOR_WIRELESS_UART, // ת + DETECTOR_CH9141, // 9141 + DETECTOR_WIFI_UART, // WIFIת + DETECTOR_WIFI_SPI, // WIFI SPI + DETECTOR_CUSTOM, // ԶͨѶʽ Ҫdetector_custom_write_byteʵݷ +}detector_transfer_type_enum; + + +// ͷö +typedef enum +{ + // ͷͺŶ + DETECTOR_OV7725_BIN = 1, + DETECTOR_MT9V03X, + DETECTOR_SCC8660, + + // ͼͶ + DETECTOR_BINARY = 1, + DETECTOR_GRAY, + DETECTOR_RGB565, +}detector_image_type_enum; + +// ͷö +typedef enum +{ + // ͷͺŶ + X_BOUNDARY, // ͵ͼб߽ϢֻXҲֻкϢͼ߶ȵõ + Y_BOUNDARY, // ͵ͼб߽ϢֻYҲֻϢͼȵõͨ + XY_BOUNDARY, // ͵ͼб߽ϢXYָλãͿԷʾЧ + NO_BOUNDARY, // ͵ͼûбϢ +}detector_boundary_type_enum; + +typedef struct +{ + uint8 head; // ֡ͷ + uint8 channel_num; // λΪ λΪͨ + uint8 check_sum; // У + uint8 length; // + float data[DETECTOR_SET_OSCILLOSCOPE_COUNT]; // ͨ +}detector_oscilloscope_struct; + + +typedef struct +{ + uint8 head; // ֡ͷ + uint8 function; // + uint8 camera_type; // λʾ߽ λʾǷͼ 0x133ʾһͼ߽磨߽ͨ硢ߡұ߽磩1ʾûͼ + uint8 length; // ȣЭ鲿֣ + uint16 image_width; // ͼ + uint16 image_height; // ͼ߶ +}detector_camera_struct; + + +typedef struct +{ + uint8 head; // ֡ͷ + uint8 function; // + uint8 dot_type; // BIT5116λ 08λ BIT7-BIT60ֻX 1ֻY 2XY궼 BIT3-BIT0߽ + uint8 length; // ȣЭ鲿֣ + uint16 dot_num; // + uint8 valid_flag; // ͨʶ + uint8 reserve; // +}detector_camera_dot_struct; + +typedef struct +{ + void *image_addr; // ͷַ + uint16 width; // ͼ + uint16 height; // ͼ߶ + detector_image_type_enum camera_type; // ͷ + void *boundary_x[DETECTOR_CAMERA_MAX_BOUNDARY]; // ַ߽ + void *boundary_y[DETECTOR_CAMERA_MAX_BOUNDARY]; // ַ߽ +}detector_camera_buffer_struct; + +typedef struct +{ + uint8 head; // ֡ͷ + uint8 function; // + uint8 channel; // ͨ + uint8 check_sum; // У + float data; // +}detector_parameter_struct; + + +extern detector_oscilloscope_struct detector_oscilloscope_data; // ʾ +extern float detector_parameter[DETECTOR_SET_PARAMETR_COUNT]; // յIJ + + +void detector_oscilloscope_send (detector_oscilloscope_struct *detector_oscilloscope); + +void detector_camera_information_config (detector_image_type_enum camera_type, void *image_addr, uint16 width, uint16 height); +void detector_camera_boundary_config (detector_boundary_type_enum boundary_type, uint16 dot_num, void *dot_x1, void *dot_x2, void *dot_x3, void *dot_y1, void *dot_y2, void *dot_y3); +void detector_camera_send (void); + +void detector_data_analysis (void); +void detector_init (detector_transfer_type_enum transfer_type); + + + +#endif + diff --git a/libraries/zf_device/zf_device_dl1a.c b/libraries/zf_device/zf_device_dl1a.c new file mode 100644 index 0000000..378874a --- /dev/null +++ b/libraries/zf_device/zf_device_dl1a.c @@ -0,0 +1,779 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_dl1a +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2023-03-18 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* SCL 查看 zf_device_dl1a.h 中 DL1A_SCL_PIN 宏定义 +* SDA 查看 zf_device_dl1a.h 中 DL1A_SDA_PIN 宏定义 +* XS 查看 zf_device_dl1a.h 中 DL1A_XS_PIN 宏定义 +* VCC 5V 电源 +* GND 电源地 +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_debug.h" +#include "zf_driver_delay.h" +#include "zf_driver_soft_iic.h" +#include "zf_device_dl1a.h" +#include "zf_device_type.h" + +static uint8 dl1a_init_flag = 0; +uint8 dl1a_finsh_flag = 0; +uint16 dl1a_distance_mm = 8192; + +#if DL1A_USE_SOFT_IIC +static soft_iic_info_struct dl1a_iic_struct; + +#define dl1a_write_array(data, len) (soft_iic_write_8bit_array(&dl1a_iic_struct, (data), (len))) +#define dl1a_write_register(reg, data) (soft_iic_write_8bit_register(&dl1a_iic_struct, (reg), (data))) +#define dl1a_read_register(reg) (soft_iic_read_8bit_register(&dl1a_iic_struct, (reg))) +#define dl1a_read_registers(reg, data, len) (soft_iic_read_8bit_registers(&dl1a_iic_struct, (reg), (data), (len))) +#else +#define dl1a_write_array(data, len) (iic_write_8bit_array(DL1A_IIC, DL1A_DEV_ADDR, (data), (len))) +#define dl1a_write_register(reg, data) (iic_write_8bit_register(DL1A_IIC, DL1A_DEV_ADDR, (reg), (data))) +#define dl1a_read_register(reg) (iic_read_8bit_register(DL1A_IIC, DL1A_DEV_ADDR, (reg))) +#define dl1a_read_registers(reg, data, len) (iic_read_8bit_registers(DL1A_IIC, DL1A_DEV_ADDR, (reg), (data), (len))) +#endif + +// 这个速率表示从目标反射并被设备检测到的信号的振幅 +// 设置此限制可以确定传感器报告有效读数所需的最小测量值 +// 设置一个较低的限制可以增加传感器的测量范围 +// 但似乎也增加了 <由于来自目标以外的物体的不需要的反射导致> 得到不准确读数的可能性 +// 默认为 0.25 MCPS 可预设范围为 0 - 511.99 +#define DL1A_DEFAULT_RATE_LIMIT (0.25) + +// 从寄存器数据解码 PCLKs 中 VCSEL (vertical cavity surface emitting laser) 的脉宽周期 +#define decode_vcsel_period(reg_val) (((reg_val) + 1) << 1) + +// 从 PCLK 中的 VCSEL 周期计算宏周期 (以 *纳秒为单位) +// PLL_period_ps = 1655 +// macro_period_vclks = 2304 +#define calc_macro_period(vcsel_period_pclks) ((((uint32)2304 * (vcsel_period_pclks) * 1655) + 500) / 1000) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 获取设备 SPAD 信息 +// 参数说明 index 索引 +// 参数说明 type 类型值 +// 返回参数 uint8 是否成功 0-成功 1-失败 +// 使用示例 dl1a_get_spad_info(index, type_is_aperture); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +static uint8 dl1a_get_spad_info (uint8 *index, uint8 *type_is_aperture) +{ + uint8 tmp = 0; + uint8 return_state = 0; + volatile uint16 loop_count = 0; + + do + { + dl1a_write_register(0x80, 0x01); + dl1a_write_register(0xFF, 0x01); + dl1a_write_register(0x00, 0x00); + + dl1a_write_register(0xFF, 0x06); + dl1a_read_registers(0x83, &tmp, 1); + dl1a_write_register(0x83, tmp | 0x04); + dl1a_write_register(0xFF, 0x07); + dl1a_write_register(0x81, 0x01); + + dl1a_write_register(0x80, 0x01); + + dl1a_write_register(0x94, 0x6b); + dl1a_write_register(0x83, 0x00); + + tmp = 0x00; + while(0x00 == tmp || 0xFF == tmp) + { + system_delay_ms(1); + dl1a_read_registers(0x83, &tmp, 1); + if(DL1A_TIMEOUT_COUNT < loop_count ++) + { + return_state = 1; + break; + } + + } + if(return_state) + { + break; + } + dl1a_write_register(0x83, 0x01); + dl1a_read_registers(0x92, &tmp, 1); + + *index = tmp & 0x7f; + *type_is_aperture = (tmp >> 7) & 0x01; + + dl1a_write_register(0x81, 0x00); + dl1a_write_register(0xFF, 0x06); + dl1a_read_registers(0x83, &tmp, 1); + dl1a_write_register(0x83, tmp); + dl1a_write_register(0xFF, 0x01); + dl1a_write_register(0x00, 0x01); + + dl1a_write_register(0xFF, 0x00); + dl1a_write_register(0x80, 0x00); + }while(0); + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 将超时数值从 MCLKs 转换到对应的 ms +// 参数说明 timeout_period_mclks 超时周期 MCLKs +// 参数说明 vcsel_period_pclks PCLK 值 +// 返回参数 uint32 返回超时数值 +// 使用示例 dl1a_timeout_mclks_to_microseconds(timeout_period_mclks, vcsel_period_pclks); +// 备注信息 将序列步骤超时从具有给定 VCSEL 周期的 MCLK (以 PCLK 为单位)转换为微秒 +//------------------------------------------------------------------------------------------------------------------- +static uint32 dl1a_timeout_mclks_to_microseconds (uint16 timeout_period_mclks, uint8 vcsel_period_pclks) +{ + uint32 macro_period_ns = calc_macro_period(vcsel_period_pclks); + + return ((timeout_period_mclks * macro_period_ns) + (macro_period_ns / 2)) / 1000; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 将超时数值从 ms 转换到对应的 MCLKs +// 参数说明 timeout_period_us 超时周期 微秒单位 +// 参数说明 vcsel_period_pclks PCLK 值 +// 返回参数 uint32 返回超时数值 +// 使用示例 dl1a_timeout_microseconds_to_mclks(timeout_period_us, vcsel_period_pclks); +// 备注信息 将序列步骤超时从微秒转换为具有给定 VCSEL 周期的 MCLK (以 PCLK 为单位) +//------------------------------------------------------------------------------------------------------------------- +static uint32 dl1a_timeout_microseconds_to_mclks (uint32 timeout_period_us, uint8 vcsel_period_pclks) +{ + uint32 macro_period_ns = calc_macro_period(vcsel_period_pclks); + + return (((timeout_period_us * 1000) + (macro_period_ns / 2)) / macro_period_ns); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 对超时数值进行解码 +// 参数说明 reg_val 超时时长 寄存器值 +// 返回参数 uint16 返回超时数值 +// 使用示例 dl1a_decode_timeout(reg_val); +// 备注信息 从寄存器值解码 MCLK 中的序列步骤超时 +//------------------------------------------------------------------------------------------------------------------- +static uint16 dl1a_decode_timeout (uint16 reg_val) +{ + // 格式: (LSByte * 2 ^ MSByte) + 1 + return (uint16)((reg_val & 0x00FF) << + (uint16)((reg_val & 0xFF00) >> 8)) + 1; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 对超时数值进行编码 +// 参数说明 timeout_mclks 超时时长 -MCLKs 值 +// 返回参数 uint16 返回编码值 +// 使用示例 dl1a_encode_timeout(timeout_mclks); +// 备注信息 在 MCLK 中对超时的序列步骤超时寄存器值进行编码 +//------------------------------------------------------------------------------------------------------------------- +static uint16 dl1a_encode_timeout (uint16 timeout_mclks) +{ + uint32 ls_byte = 0; + uint16 ms_byte = 0; + uint16 return_data = 0; + + if(0 < timeout_mclks) + { + // 格式: (LSByte * 2 ^ MSByte) + 1 + ls_byte = timeout_mclks - 1; + while(0 < (ls_byte & 0xFFFFFF00)) + { + ls_byte >>= 1; + ms_byte++; + } + return_data = (ms_byte << 8) | ((uint16)ls_byte & 0xFF); + } + return return_data; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 获取序列步骤使能设置 +// 参数说明 enables 序列使能步骤结构体 +// 返回参数 void +// 使用示例 dl1a_get_sequence_step_enables(enables); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +static void dl1a_get_sequence_step_enables(dl1a_sequence_enables_step_struct *enables) +{ + uint8 sequence_config = 0; + dl1a_read_registers(DL1A_SYSTEM_SEQUENCE_CONFIG, &sequence_config, 1); + + enables->tcc = (sequence_config >> 4) & 0x1; + enables->dss = (sequence_config >> 3) & 0x1; + enables->msrc = (sequence_config >> 2) & 0x1; + enables->pre_range = (sequence_config >> 6) & 0x1; + enables->final_range = (sequence_config >> 7) & 0x1; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 获取脉冲周期 +// 参数说明 type 预量程类型 +// 返回参数 uint8 返回的周期值 +// 使用示例 dl1a_get_vcsel_pulse_period(DL1A_VCSEL_PERIOD_PER_RANGE); +// 备注信息 在 PCLKs 中获取给定周期类型的 VCSEL 脉冲周期 +//------------------------------------------------------------------------------------------------------------------- +static uint8 dl1a_get_vcsel_pulse_period (dl1a_vcsel_period_type_enum type) +{ + uint8 data_buffer = 0; + if(DL1A_VCSEL_PERIOD_PER_RANGE == type) + { + dl1a_read_registers(DL1A_PRE_RANGE_CONFIG_VCSEL_PERIOD, &data_buffer, 1); + data_buffer = decode_vcsel_period(data_buffer); + } + else if(DL1A_VCSEL_PERIOD_FINAL_RANGE == type) + { + dl1a_read_registers(DL1A_FINAL_RANGE_CONFIG_VCSEL_PERIOD, &data_buffer, 1); + data_buffer = decode_vcsel_period(data_buffer); + } + else + { + data_buffer = 255; + } + return data_buffer; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 获取序列步骤超时设置 +// 参数说明 enables 序列使能步骤结构体 +// 参数说明 timeouts 序列超时步骤结构体 +// 返回参数 void +// 使用示例 dl1a_get_sequence_step_timeouts(enables, timeouts); +// 备注信息 获取所有超时而不仅仅是请求的超时 并且还存储中间值 +//------------------------------------------------------------------------------------------------------------------- +static void dl1a_get_sequence_step_timeouts (dl1a_sequence_enables_step_struct const *enables, dl1a_sequence_timeout_step_struct *timeouts) +{ + uint8 reg_buffer[2]; + uint16 reg16_buffer = 0; + + timeouts->pre_range_vcsel_period_pclks = dl1a_get_vcsel_pulse_period(DL1A_VCSEL_PERIOD_PER_RANGE); + + dl1a_read_registers(DL1A_MSRC_CONFIG_TIMEOUT_MACROP, reg_buffer, 1); + timeouts->msrc_dss_tcc_mclks = reg_buffer[0] + 1; + timeouts->msrc_dss_tcc_us = dl1a_timeout_mclks_to_microseconds(timeouts->msrc_dss_tcc_mclks, (uint8)timeouts->pre_range_vcsel_period_pclks); + + dl1a_read_registers(DL1A_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI, reg_buffer, 2); + reg16_buffer = ((uint16) reg_buffer[0] << 8) | reg_buffer[1]; + timeouts->pre_range_mclks = dl1a_decode_timeout(reg16_buffer); + timeouts->pre_range_us = dl1a_timeout_mclks_to_microseconds(timeouts->pre_range_mclks, (uint8)timeouts->pre_range_vcsel_period_pclks); + + timeouts->final_range_vcsel_period_pclks = dl1a_get_vcsel_pulse_period(DL1A_VCSEL_PERIOD_FINAL_RANGE); + + dl1a_read_registers(DL1A_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI, reg_buffer, 2); + reg16_buffer = ((uint16) reg_buffer[0] << 8) | reg_buffer[1]; + timeouts->final_range_mclks = dl1a_decode_timeout(reg16_buffer); + + if(enables->pre_range) + { + timeouts->final_range_mclks -= timeouts->pre_range_mclks; + } + + timeouts->final_range_us = dl1a_timeout_mclks_to_microseconds(timeouts->final_range_mclks, (uint8)timeouts->final_range_vcsel_period_pclks); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 执行单次参考校准 +// 参数说明 vhv_init_byte 预设校准值 +// 返回参数 uint8 操作是否成功 0-成功 1-失败 +// 使用示例 dl1a_get_vcsel_pulse_period(DL1A_VCSEL_PERIOD_PER_RANGE); +// 备注信息 在 PCLKs 中获取给定周期类型的 VCSEL 脉冲周期 +//------------------------------------------------------------------------------------------------------------------- +static uint8 dl1a_perform_single_ref_calibration (uint8 vhv_init_byte) +{ + uint8 return_state = 0; + uint8 data_buffer = 0; + volatile uint16 loop_count = 0; + do + { + dl1a_write_register(DL1A_SYSRANGE_START, 0x01 | vhv_init_byte); + dl1a_read_registers(DL1A_MSRC_CONFIG_TIMEOUT_MACROP, &data_buffer, 1); + while(0 == (data_buffer & 0x07)) + { + system_delay_ms(1); + dl1a_read_registers(DL1A_MSRC_CONFIG_TIMEOUT_MACROP, &data_buffer, 1); + if(DL1A_TIMEOUT_COUNT < loop_count ++) + { + return_state = 1; + break; + } + } + if(return_state) + { + break; + } + dl1a_write_register(DL1A_SYSTEM_INTERRUPT_CLEAR, 0x01); + dl1a_write_register(DL1A_SYSRANGE_START, 0x00); + }while(0); + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置测量定时预算 (以微秒为单位) +// 参数说明 budget_us 设定的测量允许的时间 +// 返回参数 uint8 操作结果 0-成功 1-失败 +// 使用示例 dl1a_set_measurement_timing_budget(measurement_timing_budget_us); +// 备注信息 这是一次测量允许的时间 +// 即在测距序列的子步骤之间分配时间预算 +// 更长的时间预算允许更精确的测量 +// 增加一个N倍的预算可以减少一个sqrt(N)倍的范围测量标准偏差 +// 默认为33毫秒 最小值为20 ms +//------------------------------------------------------------------------------------------------------------------- +static uint8 dl1a_set_measurement_timing_budget (uint32 budget_us) +{ + uint8 return_state = 0; + uint8 data_buffer[3]; + uint16 data = 0; + + dl1a_sequence_enables_step_struct enables; + dl1a_sequence_timeout_step_struct timeouts; + + do + { + if(DL1A_MIN_TIMING_BUDGET > budget_us) + { + return_state = 1; + break; + } + + uint32 used_budget_us = DL1A_SET_START_OVERHEAD + DL1A_END_OVERHEAD; + dl1a_get_sequence_step_enables(&enables); + dl1a_get_sequence_step_timeouts(&enables, &timeouts); + + if(enables.tcc) + { + used_budget_us += (timeouts.msrc_dss_tcc_us + DL1A_TCC_OVERHEAD); + } + + if(enables.dss) + { + used_budget_us += 2 * (timeouts.msrc_dss_tcc_us + DL1A_DSS_OVERHEAD); + } + else if(enables.msrc) + { + used_budget_us += (timeouts.msrc_dss_tcc_us + DL1A_MSRC_OVERHEAD); + } + + if(enables.pre_range) + { + used_budget_us += (timeouts.pre_range_us + DL1A_PRERANGE_OVERHEAD); + } + + if(enables.final_range) + { + // 请注意 最终范围超时由计时预算和序列中所有其他超时的总和决定 + // 如果没有空间用于最终范围超时 则将设置错误 + // 否则 剩余时间将应用于最终范围 + used_budget_us += DL1A_FINALlRANGE_OVERHEAD; + if(used_budget_us > budget_us) + { + // 请求的超时太大 + return_state = 1; + break; + } + + // 对于最终超时范围 必须添加预量程范围超时 + // 为此 最终超时和预量程超时必须以宏周期 MClks 表示 + // 因为它们具有不同的 VCSEL 周期 + uint32 final_range_timeout_us = budget_us - used_budget_us; + uint16 final_range_timeout_mclks = + (uint16)dl1a_timeout_microseconds_to_mclks(final_range_timeout_us, + (uint8)timeouts.final_range_vcsel_period_pclks); + + if(enables.pre_range) + { + final_range_timeout_mclks += timeouts.pre_range_mclks; + } + + data = dl1a_encode_timeout(final_range_timeout_mclks); + data_buffer[0] = DL1A_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI; + data_buffer[1] = ((data >> 8) & 0xFF); + data_buffer[2] = (data & 0xFF); + dl1a_write_array(data_buffer, 3); + } + }while(0); + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 获取测量定时预算 (以微秒为单位) +// 参数说明 void +// 返回参数 uint32 已设定的测量允许的时间 +// 使用示例 dl1a_get_measurement_timing_budget(); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +static uint32 dl1a_get_measurement_timing_budget (void) +{ + dl1a_sequence_enables_step_struct enables; + dl1a_sequence_timeout_step_struct timeouts; + + // 开始和结束开销时间始终存在 + uint32 budget_us = DL1A_GET_START_OVERHEAD + DL1A_END_OVERHEAD; + + dl1a_get_sequence_step_enables(&enables); + dl1a_get_sequence_step_timeouts(&enables, &timeouts); + + if(enables.tcc) + { + budget_us += (timeouts.msrc_dss_tcc_us + DL1A_TCC_OVERHEAD); + } + + if(enables.dss) + { + budget_us += 2 * (timeouts.msrc_dss_tcc_us + DL1A_DSS_OVERHEAD); + } + else if(enables.msrc) + { + budget_us += (timeouts.msrc_dss_tcc_us + DL1A_MSRC_OVERHEAD); + } + + if(enables.pre_range) + { + budget_us += (timeouts.pre_range_us + DL1A_PRERANGE_OVERHEAD); + } + + if(enables.final_range) + { + budget_us += (timeouts.final_range_us + DL1A_FINALlRANGE_OVERHEAD); + } + + return budget_us; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置返回信号速率限制 该值单位为 MCPS (百万次每秒) +// 参数说明 limit_mcps 设置的最小速率 +// 返回参数 void +// 使用示例 dl1a_set_signal_rate_limit(0.25); +// 备注信息 这个速率表示从目标反射并被设备检测到的信号的振幅 +// 设置此限制可以确定传感器报告有效读数所需的最小测量值 +// 设置一个较低的限制可以增加传感器的测量范围 +// 但似乎也增加了 <由于来自目标以外的物体的不需要的反射导致> 得到不准确读数的可能性 +// 默认为 0.25 MCPS 可预设范围为 0 - 511.99 +//------------------------------------------------------------------------------------------------------------------- +static void dl1a_set_signal_rate_limit (float limit_mcps) +{ + zf_assert(0 <= limit_mcps || 511.99 >= limit_mcps); + uint8 data_buffer[3]; + uint16 limit_mcps_16bit = (uint16)(limit_mcps * (1 << 7)); + + data_buffer[0] = DL1A_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT; + data_buffer[1] = ((limit_mcps_16bit >> 8) & 0xFF); + data_buffer[2] = (limit_mcps_16bit & 0xFF); + + dl1a_write_array(data_buffer, 3); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 返回以毫米为单位的范围读数 +// 参数说明 void +// 返回参数 void +// 使用示例 dl1a_get_distance(); +// 备注信息 在开始单次射程测量后也调用此函数 +//------------------------------------------------------------------------------------------------------------------- +void dl1a_get_distance (void) +{ + if(dl1a_init_flag) + { + uint8 reg_databuffer[3]; + + dl1a_read_registers(DL1A_RESULT_INTERRUPT_STATUS, reg_databuffer, 1); + if(0 != (reg_databuffer[0] & 0x07)) + { + // 假设线性度校正增益为默认值 1000 且未启用分数范围 + dl1a_read_registers(DL1A_RESULT_RANGE_STATUS + 10, reg_databuffer, 2); + dl1a_distance_mm = ((uint16_t)reg_databuffer[0] << 8); + dl1a_distance_mm |= reg_databuffer[1]; + + dl1a_write_register(DL1A_SYSTEM_INTERRUPT_CLEAR, 0x01); + dl1a_finsh_flag = 1; + } + if(reg_databuffer[0] & 0x10) + { + dl1a_read_registers(DL1A_RESULT_RANGE_STATUS + 10, reg_databuffer, 2); + dl1a_write_register(DL1A_SYSTEM_INTERRUPT_CLEAR, 0x01); + } + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 DL1A INT 中断响应处理函数 +// 参数说明 void +// 返回参数 void +// 使用示例 dl1a_int_handler(); +// 备注信息 本函数需要在 DL1A_INT_PIN 对应的外部中断处理函数中调用 +//------------------------------------------------------------------------------------------------------------------- +void dl1a_int_handler (void) +{ +#if DL1A_INT_ENABLE + dl1a_get_distance(); +#endif +} +// 函数简介 初始化 DL1A +// 参数说明 void +// 返回参数 uint8 1-初始化失败 0-初始化成功 +// 使用示例 dl1a_init(); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +uint8 dl1a_init (void) +{ + uint32 measurement_timing_budget_us; + uint8 stop_variable = 0; + uint8 return_state = 0; + uint8 reg_data_buffer = 0; + uint8 ref_spad_map[6]; + uint8 data_buffer[7]; + uint8 i = 0; + + memset(ref_spad_map, 0, 6); + memset(data_buffer, 0, 7); + +#if DL1A_USE_SOFT_IIC + soft_iic_init(&dl1a_iic_struct, DL1A_DEV_ADDR, DL1A_SOFT_IIC_DELAY, DL1A_SCL_PIN, DL1A_SDA_PIN); +#else + iic_init(DL1A_IIC, DL1A_DEV_ADDR, DL1A_IIC_SPEED, DL1A_SCL_PIN, DL1A_SDA_PIN); +#endif + gpio_init(DL1A_XS_PIN, GPO, GPIO_HIGH, GPO_PUSH_PULL); + + do + { + system_delay_ms(100); + gpio_low(DL1A_XS_PIN); + system_delay_ms(50); + gpio_high(DL1A_XS_PIN); + system_delay_ms(100); + + // -------------------------------- DL1A 启动初始化 -------------------------------- + reg_data_buffer = dl1a_read_register(DL1A_IO_VOLTAGE_CONFIG); // 传感器默认 IO 为 1.8V 模式 + dl1a_write_register(DL1A_IO_VOLTAGE_CONFIG, reg_data_buffer | 0x01); // 配置 IO 为 2.8V 模式 + + dl1a_write_register(0x88, 0x00); // 设置为标准 IIC 模式 + + dl1a_write_register(0x80, 0x01); + dl1a_write_register(0xFF, 0x01); + dl1a_write_register(0x00, 0x00); + + dl1a_read_registers(0x91, &stop_variable , 1); + + dl1a_write_register(0x00, 0x01); + dl1a_write_register(0xFF, 0x00); + dl1a_write_register(0x80, 0x00); + + // 禁用 SIGNAL_RATE_MSRC(bit1) 和 SIGNAL_RATE_PRE_RANGE(bit4) 限制检查 + reg_data_buffer = dl1a_read_register(DL1A_MSRC_CONFIG); + dl1a_write_register(DL1A_MSRC_CONFIG, reg_data_buffer | 0x12); + + dl1a_set_signal_rate_limit(DL1A_DEFAULT_RATE_LIMIT); // 设置信号速率限制 + dl1a_write_register(DL1A_SYSTEM_SEQUENCE_CONFIG, 0xFF); + // -------------------------------- DL1A 启动初始化 -------------------------------- + + // -------------------------------- DL1A 配置初始化 -------------------------------- + if(dl1a_get_spad_info(&data_buffer[0], &data_buffer[1])) + { + return_state = 1; + zf_log(0, "DL1A self check error."); + break; + } + + // 从 GLOBAL_CONFIG_SPAD_ENABLES_REF_[0-6] 获取 SPAD map (RefGoodSpadMap) 数据 + dl1a_read_registers(DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_0, ref_spad_map, 6); + + dl1a_write_register(0xFF, 0x01); + dl1a_write_register(DL1A_DYNAMIC_SPAD_REF_EN_START_OFFSET, 0x00); + dl1a_write_register(DL1A_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD, 0x2C); + dl1a_write_register(0xFF, 0x00); + dl1a_write_register(DL1A_GLOBAL_CONFIG_REF_EN_START_SELECT, 0xB4); + + data_buffer[2] = data_buffer[1] ? 12 : 0; // 12 is the first aperture spad + for(i = 0; 48 > i; i ++) + { + if(i < data_buffer[2] || data_buffer[3] == data_buffer[0]) + { + // 此位低于应启用的第一个位 + // 或者 (eference_spad_count) 位已启用 + // 因此此位为零 + ref_spad_map[i / 8] &= ~(1 << (i % 8)); + } + else if((ref_spad_map[i / 8] >> (i % 8)) & 0x1) + { + data_buffer[3] ++; + } + } + + data_buffer[0] = DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_0; + for(i = 1; 7 > i; i ++) + { + data_buffer[1] = ref_spad_map[i - 1]; + } + dl1a_write_array(data_buffer, 7); + + // 默认转换设置 version 02/11/2015_v36 + dl1a_write_register(0xFF, 0x01); + dl1a_write_register(0x00, 0x00); + dl1a_write_register(0xFF, 0x00); + dl1a_write_register(0x09, 0x00); + dl1a_write_register(0x10, 0x00); + dl1a_write_register(0x11, 0x00); + dl1a_write_register(0x24, 0x01); + dl1a_write_register(0x25, 0xFF); + dl1a_write_register(0x75, 0x00); + dl1a_write_register(0xFF, 0x01); + dl1a_write_register(0x4E, 0x2C); + dl1a_write_register(0x48, 0x00); + dl1a_write_register(0x30, 0x20); + dl1a_write_register(0xFF, 0x00); + dl1a_write_register(0x30, 0x09); + dl1a_write_register(0x54, 0x00); + dl1a_write_register(0x31, 0x04); + dl1a_write_register(0x32, 0x03); + dl1a_write_register(0x40, 0x83); + dl1a_write_register(0x46, 0x25); + dl1a_write_register(0x60, 0x00); + dl1a_write_register(0x27, 0x00); + dl1a_write_register(0x50, 0x06); + dl1a_write_register(0x51, 0x00); + dl1a_write_register(0x52, 0x96); + dl1a_write_register(0x56, 0x08); + dl1a_write_register(0x57, 0x30); + dl1a_write_register(0x61, 0x00); + dl1a_write_register(0x62, 0x00); + dl1a_write_register(0x64, 0x00); + dl1a_write_register(0x65, 0x00); + dl1a_write_register(0x66, 0xA0); + dl1a_write_register(0xFF, 0x01); + dl1a_write_register(0x22, 0x32); + dl1a_write_register(0x47, 0x14); + dl1a_write_register(0x49, 0xFF); + dl1a_write_register(0x4A, 0x00); + dl1a_write_register(0xFF, 0x00); + dl1a_write_register(0x7A, 0x0A); + dl1a_write_register(0x7B, 0x00); + dl1a_write_register(0x78, 0x21); + dl1a_write_register(0xFF, 0x01); + dl1a_write_register(0x23, 0x34); + dl1a_write_register(0x42, 0x00); + dl1a_write_register(0x44, 0xFF); + dl1a_write_register(0x45, 0x26); + dl1a_write_register(0x46, 0x05); + dl1a_write_register(0x40, 0x40); + dl1a_write_register(0x0E, 0x06); + dl1a_write_register(0x20, 0x1A); + dl1a_write_register(0x43, 0x40); + dl1a_write_register(0xFF, 0x00); + dl1a_write_register(0x34, 0x03); + dl1a_write_register(0x35, 0x44); + dl1a_write_register(0xFF, 0x01); + dl1a_write_register(0x31, 0x04); + dl1a_write_register(0x4B, 0x09); + dl1a_write_register(0x4C, 0x05); + dl1a_write_register(0x4D, 0x04); + dl1a_write_register(0xFF, 0x00); + dl1a_write_register(0x44, 0x00); + dl1a_write_register(0x45, 0x20); + dl1a_write_register(0x47, 0x08); + dl1a_write_register(0x48, 0x28); + dl1a_write_register(0x67, 0x00); + dl1a_write_register(0x70, 0x04); + dl1a_write_register(0x71, 0x01); + dl1a_write_register(0x72, 0xFE); + dl1a_write_register(0x76, 0x00); + dl1a_write_register(0x77, 0x00); + dl1a_write_register(0xFF, 0x01); + dl1a_write_register(0x0D, 0x01); + dl1a_write_register(0xFF, 0x00); + dl1a_write_register(0x80, 0x01); + dl1a_write_register(0x01, 0xF8); + dl1a_write_register(0xFF, 0x01); + dl1a_write_register(0x8E, 0x01); + dl1a_write_register(0x00, 0x01); + dl1a_write_register(0xFF, 0x00); + dl1a_write_register(0x80, 0x00); + + // 将中断配置设置为新样品就绪 + dl1a_write_register(DL1A_SYSTEM_INTERRUPT_GPIO_CONFIG, 0x04); + reg_data_buffer = dl1a_read_register(DL1A_GPIO_HV_MUX_ACTIVE_HIGH); + dl1a_write_register(DL1A_GPIO_HV_MUX_ACTIVE_HIGH, reg_data_buffer & ~0x10); + dl1a_write_register(DL1A_SYSTEM_INTERRUPT_CLEAR, 0x01); + + measurement_timing_budget_us = dl1a_get_measurement_timing_budget(); + + // 默认情况下禁用 MSRC 和 TCC + // MSRC = Minimum Signal Rate Check + // TCC = Target CentreCheck + dl1a_write_register(DL1A_SYSTEM_SEQUENCE_CONFIG, 0xE8); + dl1a_set_measurement_timing_budget(measurement_timing_budget_us); // 重新计算时序预算 + // -------------------------------- DL1A 配置初始化 -------------------------------- + + dl1a_write_register(DL1A_SYSTEM_SEQUENCE_CONFIG, 0x01); + if(dl1a_perform_single_ref_calibration(0x40)) + { + return_state = 1; + zf_log(0, "DL1A perform single reference calibration error."); + break; + } + dl1a_write_register(DL1A_SYSTEM_SEQUENCE_CONFIG, 0x02); + if(dl1a_perform_single_ref_calibration(0x00)) + { + return_state = 1; + zf_log(0, "DL1A perform single reference calibration error."); + break; + } + dl1a_write_register(DL1A_SYSTEM_SEQUENCE_CONFIG, 0xE8); // 恢复以前的序列配置 + + system_delay_ms(100); + + dl1a_write_register(0x80, 0x01); + dl1a_write_register(0xFF, 0x01); + dl1a_write_register(0x00, 0x00); + dl1a_write_register(0x91, stop_variable); + dl1a_write_register(0x00, 0x01); + dl1a_write_register(0xFF, 0x00); + dl1a_write_register(0x80, 0x00); + + dl1a_write_register(DL1A_SYSRANGE_START, 0x02); + dl1a_init_flag = 1; + + #if DL1A_INT_ENABLE + exti_init(DL1A_INT_PIN, EXTI_TRIGGER_FALLING); + dl1a_int_handler(); + dl1a_finsh_flag = 0; + #endif + set_tof_type(TOF_DL1A, dl1a_int_handler); + }while(0); + + return return_state; +} diff --git a/libraries/zf_device/zf_device_dl1a.h b/libraries/zf_device/zf_device_dl1a.h new file mode 100644 index 0000000..075f355 --- /dev/null +++ b/libraries/zf_device/zf_device_dl1a.h @@ -0,0 +1,208 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_dl1a +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2023-03-18 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* SCL 查看 zf_device_dl1a.h 中 DL1A_SCL_PIN 宏定义 +* SDA 查看 zf_device_dl1a.h 中 DL1A_SDA_PIN 宏定义 +* XS 查看 zf_device_dl1a.h 中 DL1A_XS_PIN 宏定义 +* VCC 5V 电源 +* GND 电源地 +* ------------------------------------ +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _ZF_DEVICE_DL1A_H_ +#define _ZF_DEVICE_DL1A_H_ + +#include "zf_common_typedef.h" + +// 需要注意的是 DL1A 最高支持 400KHz 的 IIC 通信速率 +// 需要注意的是 DL1A 最高支持 400KHz 的 IIC 通信速率 +// 需要注意的是 DL1A 最高支持 400KHz 的 IIC 通信速率 + +#define DL1A_USE_SOFT_IIC ( 1 ) // 默认使用软件 IIC 方式驱动 建议使用软件 IIC 方式 +#if DL1A_USE_SOFT_IIC // 这两段 颜色正常的才是正确的 颜色灰的就是没有用的 +//====================================================软件 IIC 驱动==================================================== +#define DL1A_SOFT_IIC_DELAY ( 10 ) // 软件 IIC 的时钟延时周期 数值越小 IIC 通信速率越快 +#define DL1A_SCL_PIN ( D6 ) // 软件 IIC SCL 引脚 连接 DL1A 的 SCL 引脚 +#define DL1A_SDA_PIN ( D5 ) // 软件 IIC SDA 引脚 连接 DL1A 的 SDA 引脚 +//====================================================软件 IIC 驱动==================================================== +#else +//====================================================硬件 IIC 驱动==================================================== +#define DL1A_IIC_SPEED ( 40*1000 ) // 硬件 IIC 通信速率 最高 400KHz 不建议低于 40KHz +#define DL1A_IIC ( 暂不支持 ) // 硬件 IIC SCL 引脚 连接 DL1A 的 SCL 引脚 +#define DL1A_SCL_PIN ( 暂不支持 ) // 硬件 IIC SCL 引脚 连接 DL1A 的 SCL 引脚 +#define DL1A_SDA_PIN ( 暂不支持 ) // 硬件 IIC SDA 引脚 连接 DL1A 的 SDA 引脚 +//====================================================硬件 IIC 驱动==================================================== +#endif + +#define DL1A_XS_PIN ( E10 ) +#define DL1A_INT_ENABLE ( 0 ) // 是否启用 INT 引脚 启用则会自动更新数据 +#if DL1A_INT_ENABLE +#define DL1A_INT_PIN ( C13 ) // 未定义引脚，可以不接。 +#endif +#define DL1A_TIMEOUT_COUNT (0x00FF) // DL1A 超时计数 + +//================================================定义 DL1A 内部地址================================================ +#define DL1A_DEV_ADDR ( 0x52 >> 1 ) // 0b0101001 + +#define DL1A_SYSRANGE_START ( 0x00 ) + +#define DL1A_SYSTEM_SEQUENCE_CONFIG ( 0x01 ) +#define DL1A_SYSTEM_INTERMEASUREMENT_PERIOD ( 0x04 ) +#define DL1A_SYSTEM_RANGE_CONFIG ( 0x09 ) +#define DL1A_SYSTEM_INTERRUPT_GPIO_CONFIG ( 0x0A ) +#define DL1A_SYSTEM_INTERRUPT_CLEAR ( 0x0B ) +#define DL1A_SYSTEM_THRESH_HIGH ( 0x0C ) +#define DL1A_SYSTEM_THRESH_LOW ( 0x0E ) +#define DL1A_SYSTEM_HISTOGRAM_BIN ( 0x81 ) + +#define DL1A_RESULT_INTERRUPT_STATUS ( 0x13 ) +#define DL1A_RESULT_RANGE_STATUS ( 0x14 ) +#define DL1A_RESULT_PEAK_SIGNAL_RATE_REF ( 0xB6 ) +#define DL1A_RESULT_CORE_AMBIENT_WINDOW_EVENTS_RTN ( 0xBC ) +#define DL1A_RESULT_CORE_RANGING_TOTAL_EVENTS_RTN ( 0xC0 ) +#define DL1A_RESULT_CORE_AMBIENT_WINDOW_EVENTS_REF ( 0xD0 ) +#define DL1A_RESULT_CORE_RANGING_TOTAL_EVENTS_REF ( 0xD4 ) + +#define DL1A_PRE_RANGE_CONFIG_MIN_SNR ( 0x27 ) +#define DL1A_PRE_RANGE_CONFIG_VCSEL_PERIOD ( 0x50 ) +#define DL1A_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI ( 0x51 ) +#define DL1A_PRE_RANGE_CONFIG_TIMEOUT_MACROP_LO ( 0x52 ) +#define DL1A_PRE_RANGE_CONFIG_VALID_PHASE_LOW ( 0x56 ) +#define DL1A_PRE_RANGE_CONFIG_VALID_PHASE_HIGH ( 0x57 ) +#define DL1A_PRE_RANGE_CONFIG_SIGMA_THRESH_HI ( 0x61 ) +#define DL1A_PRE_RANGE_CONFIG_SIGMA_THRESH_LO ( 0x62 ) +#define DL1A_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT ( 0x64 ) + +#define DL1A_FINAL_RANGE_CONFIG_VALID_PHASE_LOW ( 0x47 ) +#define DL1A_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH ( 0x48 ) +#define DL1A_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT ( 0x44 ) +#define DL1A_FINAL_RANGE_CONFIG_MIN_SNR ( 0x67 ) +#define DL1A_FINAL_RANGE_CONFIG_VCSEL_PERIOD ( 0x70 ) +#define DL1A_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI ( 0x71 ) +#define DL1A_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_LO ( 0x72 ) + +#define DL1A_GLOBAL_CONFIG_VCSEL_WIDTH ( 0x32 ) +#define DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_0 ( 0xB0 ) +#define DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_1 ( 0xB1 ) +#define DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_2 ( 0xB2 ) +#define DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_3 ( 0xB3 ) +#define DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_4 ( 0xB4 ) +#define DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_5 ( 0xB5 ) +#define DL1A_GLOBAL_CONFIG_REF_EN_START_SELECT ( 0xB6 ) + +#define DL1A_ALGO_PART_TO_PART_RANGE_OFFSET_MM ( 0x28 ) +#define DL1A_ALGO_PHASECAL_LIM ( 0x30 ) +#define DL1A_ALGO_PHASECAL_CONFIG_TIMEOUT ( 0x30 ) + +#define DL1A_HISTOGRAM_CONFIG_INITIAL_PHASE_SELECT ( 0x33 ) +#define DL1A_HISTOGRAM_CONFIG_READOUT_CTRL ( 0x55 ) + +#define DL1A_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD ( 0x4E ) +#define DL1A_DYNAMIC_SPAD_REF_EN_START_OFFSET ( 0x4F ) + +#define DL1A_MSRC_CONFIG_TIMEOUT_MACROP ( 0x46 ) +#define DL1A_MSRC_CONFIG ( 0x60 ) + +#define DL1A_IDENTIFICATION_MODEL_ID ( 0xC0 ) +#define DL1A_IDENTIFICATION_REVISION_ID ( 0xC2 ) + +#define DL1A_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS ( 0x20 ) + +#define DL1A_POWER_MANAGEMENT_GO1_POWER_FORCE ( 0x80 ) + +#define DL1A_GPIO_HV_MUX_ACTIVE_HIGH ( 0x84 ) + +#define DL1A_I2C_SLAVE_DEVICE_ADDRESS ( 0x8A ) + +#define DL1A_SOFT_RESET_GO2_SOFT_RESET_N ( 0xBF ) + +#define DL1A_OSC_CALIBRATE_VAL ( 0xF8 ) + +#define DL1A_IO_VOLTAGE_CONFIG ( 0x89 ) // IO 电压设置寄存器地址 默认 1V8 使用修改为 2V8 + +//================================================定义 DL1A 内部地址================================================ + +#define DL1A_MIN_TIMING_BUDGET ( 20000 ) + +#define DL1A_GET_START_OVERHEAD ( 1910 ) +#define DL1A_SET_START_OVERHEAD ( 1320 ) +#define DL1A_END_OVERHEAD ( 960 ) +#define DL1A_TCC_OVERHEAD ( 590 ) +#define DL1A_DSS_OVERHEAD ( 690 ) +#define DL1A_MSRC_OVERHEAD ( 660 ) +#define DL1A_PRERANGE_OVERHEAD ( 660 ) +#define DL1A_FINALlRANGE_OVERHEAD ( 550 ) + +typedef enum +{ + DL1A_VCSEL_PERIOD_PER_RANGE, + DL1A_VCSEL_PERIOD_FINAL_RANGE, +}dl1a_vcsel_period_type_enum; + +typedef struct +{ + uint8 tcc; + uint8 msrc; + uint8 dss; + uint8 pre_range; + uint8 final_range; +}dl1a_sequence_enables_step_struct; + +typedef struct +{ + uint16 pre_range_vcsel_period_pclks; + uint16 final_range_vcsel_period_pclks; + + uint16 msrc_dss_tcc_mclks; + uint16 pre_range_mclks; + uint16 final_range_mclks; + uint32 msrc_dss_tcc_us; + uint32 pre_range_us; + uint32 final_range_us; +}dl1a_sequence_timeout_step_struct; + +extern uint8 dl1a_finsh_flag; +extern uint16 dl1a_distance_mm; + +void dl1a_get_distance (void); + +uint8 dl1a_init (void); + +#endif + diff --git a/libraries/zf_device/zf_device_dl1b.c b/libraries/zf_device/zf_device_dl1b.c new file mode 100644 index 0000000..9faa0e4 --- /dev/null +++ b/libraries/zf_device/zf_device_dl1b.c @@ -0,0 +1,217 @@ +/********************************************************************************************************************* +* MM32F527X-E9P Opensourec Library 即（MM32F527X-E9P 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是 MM32F527X-E9P 开源库的一部分 +* +* MM32F527X-E9P 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_dl1b +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-08-10 Teternal first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* SCL 查看 zf_device_dl1b.h 中 DL1B_SCL_PIN 宏定义 +* SDA 查看 zf_device_dl1b.h 中 DL1B_SDA_PIN 宏定义 +* XS 查看 zf_device_dl1b.h 中 DL1B_XS_PIN 宏定义 +* VCC 5V 电源 +* GND 电源地 +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_debug.h" + +#include "zf_driver_delay.h" +#include "zf_driver_exti.h" +#include "zf_driver_soft_iic.h" + +#include "zf_device_dl1b.h" +#include "zf_device_config.h" +#include "zf_device_type.h" + +static uint8 dl1b_init_flag = 0; +uint8 dl1b_finsh_flag = 0; +uint16 dl1b_distance_mm = 8192; + +#if DL1B_USE_SOFT_IIC +static soft_iic_info_struct dl1b_iic_struct; + +#define dl1b_transfer_8bit_array(tdata, tlen, rdata, rlen) (soft_iic_transfer_8bit_array(&dl1b_iic_struct, (tdata), (tlen), (rdata), (rlen))) +#else +#define dl1b_transfer_8bit_array(tdata, tlen, rdata, rlen) (iic_transfer_8bit_array(DL1B_IIC, DL1B_DEV_ADDR, (tdata), (tlen), (rdata), (rlen))) +#endif + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 返回以毫米为单位的范围读数 +// 参数说明 void +// 返回参数 void +// 使用示例 dl1b_get_distance(); +// 备注信息 在开始单次射程测量后也调用此函数 +//------------------------------------------------------------------------------------------------------------------- +void dl1b_get_distance (void) +{ + if(dl1b_init_flag) + { + uint8 data_buffer[3]; + int16 dl1b_distance_temp = 0; + + data_buffer[0] = DL1B_GPIO__TIO_HV_STATUS >> 8; + data_buffer[1] = DL1B_GPIO__TIO_HV_STATUS & 0xFF; + dl1b_transfer_8bit_array(data_buffer, 2, &data_buffer[2], 1); + + if(data_buffer[2]) + { + + data_buffer[0] = DL1B_SYSTEM__INTERRUPT_CLEAR >> 8; + data_buffer[1] = DL1B_SYSTEM__INTERRUPT_CLEAR & 0xFF; + data_buffer[2] = 0x01; + dl1b_transfer_8bit_array(data_buffer, 3, data_buffer, 0);// clear Interrupt + + data_buffer[0] = DL1B_RESULT__RANGE_STATUS >> 8; + data_buffer[1] = DL1B_RESULT__RANGE_STATUS & 0xFF; + dl1b_transfer_8bit_array(data_buffer, 2, &data_buffer[2], 1); + + if(0x89 == data_buffer[2]) + { + data_buffer[0] = DL1B_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 >> 8; + data_buffer[1] = DL1B_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 & 0xFF; + dl1b_transfer_8bit_array(data_buffer, 2, data_buffer, 2); + dl1b_distance_temp = data_buffer[0]; + dl1b_distance_temp = (dl1b_distance_temp << 8) | data_buffer[1]; + + if(dl1b_distance_temp > 4000 || dl1b_distance_temp < 0) + { + dl1b_distance_mm = 8192; + dl1b_finsh_flag = 0; + } + else + { + dl1b_distance_mm = dl1b_distance_temp; + dl1b_finsh_flag = 1; + } + } + else + { + dl1b_distance_mm = 8192; + dl1b_finsh_flag = 0; + } + } + else + { + dl1b_distance_mm = 8192; + dl1b_finsh_flag = 0; + } + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 DL1B INT 中断响应处理函数 +// 参数说明 void +// 返回参数 void +// 使用示例 dl1b_int_handler(); +// 备注信息 本函数需要在 DL1B_INT_PIN 对应的外部中断处理函数中调用 +//------------------------------------------------------------------------------------------------------------------- +void dl1b_int_handler (void) +{ +#if DL1B_INT_ENABLE + dl1b_get_distance(); +#endif +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 初始化 DL1B +// 参数说明 void +// 返回参数 uint8 1-初始化失败 0-初始化成功 +// 使用示例 dl1b_init(); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +uint8 dl1b_init (void) +{ + uint8 return_state = 0; + uint8 data_buffer[2 + sizeof(dl1b_config_file)]; + uint16 time_out_count = 0; + +#if DL1B_USE_SOFT_IIC + soft_iic_init(&dl1b_iic_struct, DL1B_DEV_ADDR, DL1B_SOFT_IIC_DELAY, DL1B_SCL_PIN, DL1B_SDA_PIN); +#else + iic_init(DL1B_IIC, DL1B_DEV_ADDR, DL1B_IIC_SPEED, DL1B_SCL_PIN, DL1B_SDA_PIN); +#endif + gpio_init(DL1B_XS_PIN, GPO, GPIO_HIGH, GPO_PUSH_PULL); + + do + { + system_delay_ms(50); + gpio_low(DL1B_XS_PIN); + system_delay_ms(10); + gpio_high(DL1B_XS_PIN); + system_delay_ms(50); + + data_buffer[0] = DL1B_FIRMWARE__SYSTEM_STATUS >> 8; + data_buffer[1] = DL1B_FIRMWARE__SYSTEM_STATUS & 0xFF; + dl1b_transfer_8bit_array(data_buffer, 2, &data_buffer[2], 1); + return_state = (0x01 == (data_buffer[2] & 0x01)) ? (0) : (1); + if(1 == return_state) + { + break; + } + + data_buffer[0] = DL1B_I2C_SLAVE__DEVICE_ADDRESS >> 8; + data_buffer[1] = DL1B_I2C_SLAVE__DEVICE_ADDRESS & 0xFF; + memcpy(&data_buffer[2], (uint8 *)dl1b_config_file, sizeof(dl1b_config_file)); + dl1b_transfer_8bit_array(data_buffer, 2 + sizeof(dl1b_config_file), data_buffer, 0); + + while(1) + { + data_buffer[0] = DL1B_GPIO__TIO_HV_STATUS >> 8; + data_buffer[1] = DL1B_GPIO__TIO_HV_STATUS & 0xFF; + dl1b_transfer_8bit_array(data_buffer, 2, &data_buffer[2], 1); + if(0x00 == (data_buffer[2] & 0x01)) + { + time_out_count = 0; + break; + } + if(DL1B_TIMEOUT_COUNT < time_out_count ++) + { + return_state = 1; + break; + } + system_delay_ms(1); + } + + dl1b_init_flag = 1; + +#if DL1B_INT_ENABLE + exti_init(DL1B_INT_PIN, EXTI_TRIGGER_FALLING); + dl1b_int_handler(); + dl1b_finsh_flag = 0; +#endif + set_tof_type(TOF_DL1B, dl1b_int_handler); + }while(0); + + return return_state; +} diff --git a/libraries/zf_device/zf_device_dl1b.h b/libraries/zf_device/zf_device_dl1b.h new file mode 100644 index 0000000..6b4089b --- /dev/null +++ b/libraries/zf_device/zf_device_dl1b.h @@ -0,0 +1,104 @@ + /********************************************************************************************************************* +* MM32F527X-E9P Opensourec Library 即（MM32F527X-E9P 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是 MM32F527X-E9P 开源库的一部分 +* +* MM32F527X-E9P 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_dl1b +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-08-10 Teternal first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* SCL 查看 zf_device_dl1b.h 中 DL1B_SCL_PIN 宏定义 +* SDA 查看 zf_device_dl1b.h 中 DL1B_SDA_PIN 宏定义 +* XS 查看 zf_device_dl1b.h 中 DL1B_XS_PIN 宏定义 +* VCC 5V 电源 +* GND 电源地 +* ------------------------------------ +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _ZF_DEVICE_DL1B_H_ +#define _ZF_DEVICE_DL1B_H_ + +#include "zf_common_typedef.h" + +// 需要注意的是 DL1B 最高支持 400KHz 的 IIC 通信速率 +// 需要注意的是 DL1B 最高支持 400KHz 的 IIC 通信速率 +// 需要注意的是 DL1B 最高支持 400KHz 的 IIC 通信速率 + +#define DL1B_USE_SOFT_IIC ( 1 ) // 默认使用软件 IIC 方式驱动 建议使用软件 IIC 方式 +#if DL1B_USE_SOFT_IIC // 这两段 颜色正常的才是正确的 颜色灰的就是没有用的 +//====================================================软件 IIC 驱动==================================================== +#define DL1B_SOFT_IIC_DELAY ( 10 ) // 软件 IIC 的时钟延时周期 数值越小 IIC 通信速率越快 +#define DL1B_SCL_PIN ( D6 ) // 软件 IIC SCL 引脚 连接 DL1B 的 SCL 引脚 +#define DL1B_SDA_PIN ( D5 ) // 软件 IIC SDA 引脚 连接 DL1B 的 SDA 引脚 +//====================================================软件 IIC 驱动==================================================== +#else +//====================================================硬件 IIC 驱动==================================================== +#define DL1B_IIC_SPEED ( 400 * 1000 ) // 硬件 IIC 通信速率 最高 400KHz 不建议低于 40KHz +#define DL1B_IIC ( 暂不支持 ) // 硬件 IIC SCL 引脚 连接 DL1B 的 SCL 引脚 +#define DL1B_SCL_PIN ( 暂不支持 ) // 硬件 IIC SCL 引脚 连接 DL1B 的 SCL 引脚 +#define DL1B_SDA_PIN ( 暂不支持 ) // 硬件 IIC SDA 引脚 连接 DL1B 的 SDA 引脚 +//====================================================硬件 IIC 驱动==================================================== +#endif + +#define DL1B_XS_PIN ( E10 ) + +#define DL1B_INT_ENABLE ( 0 ) // 是否启用 INT 引脚 启用则会自动更新数据 +#if DL1B_INT_ENABLE +#define DL1B_INT_PIN ( C13 ) +#endif + +#define DL1B_TIMEOUT_COUNT ( 1000 ) // DL1B 超时计数 + +//================================================定义 DL1B 内部地址================================================ + +#define DL1B_DEV_ADDR ( 0x52 >> 1 ) // 0b0101001 + +#define DL1B_I2C_SLAVE__DEVICE_ADDRESS ( 0x0001 ) +#define DL1B_GPIO__TIO_HV_STATUS ( 0x0031 ) +#define DL1B_SYSTEM__INTERRUPT_CLEAR ( 0x0086 ) +#define DL1B_RESULT__RANGE_STATUS ( 0x0089 ) +#define DL1B_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 ( 0x0096 ) +#define DL1B_FIRMWARE__SYSTEM_STATUS ( 0x00E5 ) + +//================================================定义 DL1B 内部地址================================================ + +extern uint8 dl1b_finsh_flag; +extern uint16 dl1b_distance_mm; + +void dl1b_get_distance (void); + +void dl1b_int_handler (void); +uint8 dl1b_init (void); + +#endif + diff --git a/libraries/zf_device/zf_device_dm1xa.c b/libraries/zf_device/zf_device_dm1xa.c new file mode 100644 index 0000000..61126ef --- /dev/null +++ b/libraries/zf_device/zf_device_dm1xa.c @@ -0,0 +1,255 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_dm1xa +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2023-03-18 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 有去模块(无MCU版本 模块标识型号) +* 模块管脚 单片机管脚 +* FB 查看 zf_device_dm1xa.h 中 DM1XA_FB_PIN 宏定义 +* EN 查看 zf_device_dm1xa.h 中 DM1XA_EN_PIN 宏定义 +* 5V 5V 电源 +* GND 电源地 +* ------------------------------------ +* ------------------------------------ +* 有来模块(无MCU版本 模块标识型号) +* 模块管脚 单片机管脚 +* S 查看 zf_device_dm1xa.h 中 DM1XA_S_PIN 宏定义 +* L 查看 zf_device_dm1xa.h 中 DM1XA_L_PIN 宏定义 +* 5V 5V 电源 +* GND 电源地 +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_debug.h" +#include "zf_driver_delay.h" +#include "zf_driver_exti.h" +#include "zf_driver_timer.h" + +#include "zf_device_dm1xa.h" + +static uint16 dm1xa_distance_mm = 6800; +static uint32 dm1xa_plus_count = 0; +//static uint32 dm1xa_match_count = 0; +static dm1xa_type_enum dm1xa_type = DM1XA_NO_INIT; +static dm1xa_ranging_state_enum dm1xa_ranging_state = DM1XA_RECEIVER_RANGING_NO_SIGNAL; + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 DM1XA 声信号 / 反馈信号 外部中断回调函数 +// 参数说明 void 无 +// 参数说明 void 无 +// 使用示例 dm1xa_sound_callback(); +// 备注信息 这个函数需要放在 DM1XA_FB_PIN / DM1XA_S_PIN 对应的外部中断服务函数里 +//------------------------------------------------------------------------------------------------------------------- +void dm1xa_sound_callback (void) +{ + switch(dm1xa_type) + { + case DM1XA_NO_INIT: // 未初始化 退出 + { + }break; + case DM1XA_CHECK_TYPE: // 初始化阶段 + { + dm1xa_plus_count ++; // 对 FB 或者 sound 信号计数 + }break; + case DM1XA_TRANSMITTER: // DM1TA 模块发起测距 + { + dm1xa_plus_count ++; // 对 FB 信号计数 + if(DM1XA_FB_SEND <= dm1xa_plus_count) // 达到规定的 DM1XA_FB_SEND 计数 + { + gpio_low(DM1XA_EN_PIN); // 停止发送测距信号 + dm1xa_plus_count = 0; // 清空计数 + } + }break; + case DM1XA_RECEIVER: // DM1RA 获取测距信号 + { + if(DM1XA_RECEIVER_RANGING_WAIT_SOUND == dm1xa_ranging_state) // 已经获取光信号 证明本次信号有效 + { + if(gpio_get_level(DM1XA_S_PIN)) // 声信号为高 是一个完整脉冲 + { + if(150 < timer_get(DM1XA_TIM_INDEX) - dm1xa_plus_count) // 判断这个声信号脉冲是否是低于 150us 的干扰噪声 + { + timer_clear(DM1XA_TIM_INDEX); // 清空时间 + dm1xa_distance_mm = (float)dm1xa_plus_count * DM1XA_SOUND_SPEED_MM_PER_US; // 计算距离值 毫米单位 + dm1xa_ranging_state = DM1XA_RECEIVER_RANGING_SUCCESS; // 测距信息更新为完成测距 + } + } + else // 声信号为低 证明是脉冲起始 + { + dm1xa_plus_count = timer_get(DM1XA_TIM_INDEX); // 记录声光时间差 + } + } + }break; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 DM1XA 光信号 外部中断回调函数 +// 参数说明 void 无 +// 参数说明 void 无 +// 使用示例 dm1xa_light_callback(); +// 备注信息 这个函数需要放在 DM1XA_EN_PIN / DM1XA_L_PIN 对应的外部中断服务函数里 +//------------------------------------------------------------------------------------------------------------------- +void dm1xa_light_callback (void) +{ + switch(dm1xa_type) + { + case DM1XA_NO_INIT: // 未初始化 退出 + case DM1XA_CHECK_TYPE: // 初始化阶段 + case DM1XA_TRANSMITTER: // DM1TA 模块发起测距 + { + }break; + case DM1XA_RECEIVER: // DM1RA 获取测距信号 + { + timer_clear(DM1XA_TIM_INDEX); // 清空时间 准备获取声光时间差 + dm1xa_ranging_state = DM1XA_RECEIVER_RANGING_WAIT_SOUND; // 标记获取到光信号 + }break; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 DM1RA 模块 获取测距结果数据 +// 参数说明 void 无 +// 返回参数 uint16 距离信息 6800 为超时默认距离 +// 使用示例 uint16 distance_mm = dm1xa_receiver_ranging(); +// 备注信息 更新距离信息 +// +// 需要注意 dm1xa_receiver_ranging 的调用周期务必控制在 10-20ms 这个区间 +// 调用周期决定了最大测距距离 换算公式基本等于 period * 343.2 mm +// 那么 10-20ms 的调用周期区间对应 3432-6864mm 的最大测距范围 +// 如果 dm1xa_receiver_ranging 的调用周期不在这个范围 +// 那么可能出现本驱动的测距信息异常 +//------------------------------------------------------------------------------------------------------------------- +uint16 dm1xa_receiver_ranging (void) +{ + switch(dm1xa_ranging_state) + { + case DM1XA_RECEIVER_RANGING_NO_SIGNAL: // 无测距信号 + case DM1XA_RECEIVER_RANGING_WAIT_SOUND: // 正获取测距信号 + { + if(DM1XA_RECEIVER_TIMEROUT_US <= timer_get(DM1XA_TIM_INDEX)) // 如果距离上次光信号不超过 30ms + { + dm1xa_distance_mm = 6800; // 恢复默认最大输出值 + } + }break; + case DM1XA_RECEIVER_RANGING_SUCCESS: // 完成测距信息 + { + dm1xa_ranging_state = DM1XA_RECEIVER_RANGING_NO_SIGNAL; // 标记测距信号恢复默认 + }break; + default: + { + }break; + } + return dm1xa_distance_mm; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 DM1TA 模块 发送一组测距信号 +// 参数说明 void 无 +// 返回参数 void 无 +// 使用示例 dm1xa_transmitter_ranging(); +// 备注信息 发送完成后它会自己通过定时器控制 +// 这个函数用于使用 DM1TA 发起一次测距 +// 随后 DM1RA 将自动触发一次测距更新距离信息 +// +// 需要注意 dm1xa_transmitter_ranging 的调用周期务必控制在 10-20ms 这个区间 +// 调用周期决定了最大测距距离 换算公式基本等于 period * 343.2 mm +// 那么 10-20ms 的调用周期区间对应 3432-6864mm 的最大测距范围 +// 如果 dm1xa_transmitter_ranging 的调用周期不在这个范围 +// 那么可能出现本驱动的测距信息异常 +//------------------------------------------------------------------------------------------------------------------- +void dm1xa_transmitter_ranging (void) +{ + gpio_high(DM1XA_EN_PIN); // 拉高 EN 开启一次测距信息发送 +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 初始化 超声波 模块 +// 参数说明 void 无 +// 返回参数 dm1xa_error_code_enum DM1XA_NO_ERROR-初始化成功 +// 使用示例 dm1xa_init(); +// 备注信息 会自动识别是 DM1TA 模块还是 DM1RA 模块 +//------------------------------------------------------------------------------------------------------------------- +dm1xa_error_code_enum dm1xa_init (void) +{ + dm1xa_error_code_enum return_state = DM1XA_NO_ERROR; + + do + { + dm1xa_distance_mm = 0; + dm1xa_type = DM1XA_CHECK_TYPE; // 模块状态标记为类型确认模式 + + gpio_init(DM1XA_S_PIN, GPI, GPIO_LOW, GPI_PULL_DOWN); // 两个引脚设置为下拉输入模式 + gpio_init(DM1XA_L_PIN, GPI, GPIO_LOW, GPI_PULL_DOWN); // 两个引脚设置为下拉输入模式 + + int16 i = DM1XA_INIT_MAX_COUNT; + while(i --) + { + if(gpio_get_level(DM1XA_S_PIN) && gpio_get_level(DM1XA_L_PIN)) // 两个都是高电平 那么可能是 DM1RA 模块 + { + dm1xa_type = DM1XA_RECEIVER; + dm1xa_ranging_state = DM1XA_RECEIVER_RANGING_NO_SIGNAL; + exti_init(DM1XA_S_PIN, EXTI_TRIGGER_BOTH); // 引脚初始化为外部中断输入 + exti_init(DM1XA_L_PIN, EXTI_TRIGGER_FALLING); // 引脚初始化为外部中断输入 + timer_init(DM1XA_TIM_INDEX, TIMER_US); // 微秒计时 + timer_clear(DM1XA_TIM_INDEX); // 清空计数 + timer_start(DM1XA_TIM_INDEX); // 启动定时器 + break; + } + system_delay_us(100); + } + if(0 > i) + { + exti_init(DM1XA_FB_PIN, EXTI_TRIGGER_FALLING); + gpio_init(DM1XA_EN_PIN, GPO, GPIO_LOW, GPO_PUSH_PULL); + dm1xa_plus_count = 0; + gpio_high(DM1XA_EN_PIN); + system_delay_us(210); + gpio_low(DM1XA_EN_PIN); + if(6 < dm1xa_plus_count && 10 > dm1xa_plus_count) + { + dm1xa_type = DM1XA_TRANSMITTER; + dm1xa_plus_count = 0; + } + else + { + dm1xa_type = DM1XA_NO_INIT; + return_state = DM1XA_TYPE_ERROR; + break; + } + } + }while(0); + + return return_state; +} diff --git a/libraries/zf_device/zf_device_dm1xa.h b/libraries/zf_device/zf_device_dm1xa.h new file mode 100644 index 0000000..bbdf863 --- /dev/null +++ b/libraries/zf_device/zf_device_dm1xa.h @@ -0,0 +1,121 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_dm1xa +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2023-03-18 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 有去模块(无MCU版本 模块标识型号) +* 模块管脚 单片机管脚 +* FB 查看 zf_device_dm1xa.h 中 DM1XA_FB_PIN 宏定义 +* EN 查看 zf_device_dm1xa.h 中 DM1XA_EN_PIN 宏定义 +* 5V 5V 电源 +* GND 电源地 +* ------------------------------------ +* ------------------------------------ +* 有来模块(无MCU版本 模块标识型号) +* 模块管脚 单片机管脚 +* S 查看 zf_device_dm1xa.h 中 DM1XA_S_PIN 宏定义 +* L 查看 zf_device_dm1xa.h 中 DM1XA_L_PIN 宏定义 +* 5V 5V 电源 +* GND 电源地 +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _ZF_DEVICE_DM1XA_H_ +#define _ZF_DEVICE_DM1XA_H_ + +#include "zf_common_typedef.h" + +// 需要注意 dm1xa_transmitter_ranging / dm1xa_receiver_ranging 的调用周期 +// 务必控制在 10-20ms 这个区间 +// +// 调用周期决定了最大测距距离 换算公式基本等于 period * 343.2 mm +// 那么 10-20ms 的调用周期区间对应 3432-6864mm 的最大测距范围 +// +// 如果 dm1xa_transmitter_ranging / dm1xa_receiver_ranging +// 的调用周期不在 10-20ms 这个区间 +// 那么可能出现本驱动的测距信息异常 + +// DM1TA 模块 引脚对应 +#define DM1XA_FB_PIN ( E15 ) +#define DM1XA_EN_PIN ( E14 ) + +// DM1RA 模块 引脚对应 +#define DM1XA_S_PIN ( E15 ) +#define DM1XA_L_PIN ( E14 ) + +#define DM1XA_TIM_INDEX ( TIM_7 ) // 固定使用一个定时器 + +#define DM1XA_SOUND_SPEED_MM_PER_US ( 0.34 ) // 定义声速 340M/s = 0.34 mm/us + +#define DM1XA_FB_SEND ( 10 ) // 每次测距 EN 上脉冲时长为 DM1XA_FB_SEND * 1000 / 38 微秒 +#if (DM1XA_FB_SEND < 6 || DM1XA_FB_SEND > 100) // 每次测距的载波数 最小 6 最大 100 +#error "DM1XA_FB_SEND error, it must be between 6 and 100" +#endif + +#define DM1XA_INIT_MAX_COUNT ( 100 ) // 初始化尝试次数 +#define DM1XA_RECEIVER_TIMEROUT_US ( 30000 ) // 超时设置 这里不允许用户修改 + +// DM1XA 模块错误识别码 用户不允许更改 +typedef enum +{ + DM1XA_NO_ERROR, + DM1XA_TYPE_ERROR, +}dm1xa_error_code_enum; + +// DM1XA 模块错误识别码 用户不允许更改 +typedef enum +{ + DM1XA_RECEIVER_RANGING_NO_SIGNAL, + DM1XA_RECEIVER_RANGING_WAIT_SOUND, + DM1XA_RECEIVER_RANGING_SUCCESS, +}dm1xa_ranging_state_enum; + +// DM1XA 模块类型 用户不允许更改 +typedef enum +{ + DM1XA_NO_INIT, + DM1XA_CHECK_TYPE, + DM1XA_TRANSMITTER, + DM1XA_RECEIVER, +}dm1xa_type_enum; + +void dm1xa_sound_callback (void); +void dm1xa_light_callback (void); + +uint16 dm1xa_receiver_ranging (void); +void dm1xa_transmitter_ranging (void); +dm1xa_error_code_enum dm1xa_init (void); + +#endif diff --git a/libraries/zf_device/zf_device_gps_tau1201.c b/libraries/zf_device/zf_device_gps_tau1201.c new file mode 100644 index 0000000..97861e0 --- /dev/null +++ b/libraries/zf_device/zf_device_gps_tau1201.c @@ -0,0 +1,540 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 isr +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-08-10 Teternal first version +* 2022-09-21 SeekFree 修改了处理结构 使得指令区分存放 解决了随机解析时丢失指令的问题 +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* RX 查看 zf_device_gps_tau1201.h 中 GPS_TAU1201_RX 宏定义 +* TX 查看 zf_device_gps_tau1201.h 中 GPS_TAU1201_TX 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* ------------------------------------ +********************************************************************************************************************/ + +#include "math.h" +#include "zf_common_function.h" +#include "zf_common_fifo.h" +#include "zf_driver_delay.h" +#include "zf_driver_uart.h" + +#include "zf_device_gps_tau1201.h" + +#define GPS_TAU1201_BUFFER_SIZE ( 128 ) + +uint8 gps_tau1201_flag = 0; // 1：采集完成等待处理数据 0：没有采集完成 +gps_info_struct gps_tau1201; // GPS解析之后的数据 + +static uint8 gps_tau1201_state = 0; // 1：GPS初始化完成 +static fifo_struct gps_tau1201_receiver_fifo; // +static uint8 gps_tau1201_receiver_buffer[GPS_TAU1201_BUFFER_SIZE]; // 数据存放数组 + +gps_state_enum gps_gga_state = GPS_STATE_RECEIVING; // gga 语句状态 +gps_state_enum gps_rmc_state = GPS_STATE_RECEIVING; // rmc 语句状态 + +static uint8 gps_gga_buffer[GPS_TAU1201_BUFFER_SIZE]; +static uint8 gps_rmc_buffer[GPS_TAU1201_BUFFER_SIZE]; + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 获取指定 ',' 后面的索引 +// 参数说明 num 第几个逗号 +// 参数说明 *str 字符串 +// 返回参数 uint8 返回索引 +// 使用示例 get_parameter_index(1, s); +// 备注信息 内部使用 +//------------------------------------------------------------------------------------------------------------------- +static uint8 get_parameter_index (uint8 num, char *str) +{ + uint8 i = 0, j = 0; + char *temp = strchr(str, '\n'); + uint8 len = 0, len1 = 0; + + if(NULL != temp) + { + len = (uint8)((uint32)temp - (uint32)str + 1); + } + + for(i = 0; i < len; i ++) + { + if(',' == str[i]) + { + j ++; + } + if(j == num) + { + len1 = i + 1; + break; + } + } + + return len1; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 给定字符串第一个 ',' 之前的数据转换为int +// 参数说明 *s 字符串 +// 返回参数 float 返回数值 +// 使用示例 get_int_number(&buf[get_parameter_index(7, buf)]); +// 备注信息 内部使用 +//------------------------------------------------------------------------------------------------------------------- +static int get_int_number (char *s) +{ + char buf[10]; + uint8 i = 0; + int return_value = 0; + i = get_parameter_index(1, s); + i = i - 1; + strncpy(buf, s, i); + buf[i] = 0; + return_value = func_str_to_int(buf); + return return_value; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 给定字符串第一个 ',' 之前的数据转换为float +// 参数说明 *s 字符串 +// 返回参数 float 返回数值 +// 使用示例 get_float_number(&buf[get_parameter_index(8, buf)]); +// 备注信息 内部使用 +//------------------------------------------------------------------------------------------------------------------- +static float get_float_number (char *s) +{ + uint8 i = 0; + char buf[15]; + float return_value = 0; + + i = get_parameter_index(1, s); + i = i - 1; + strncpy(buf, s, i); + buf[i] = 0; + return_value = (float)func_str_to_double(buf); + return return_value; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 给定字符串第一个 ',' 之前的数据转换为double +// 参数说明 *s 字符串 +// 返回参数 double 返回数值 +// 使用示例 get_double_number(&buf[get_parameter_index(3, buf)]); +// 备注信息 内部使用 +//------------------------------------------------------------------------------------------------------------------- +static double get_double_number (char *s) +{ + uint8 i = 0; + char buf[15]; + double return_value = 0; + + i = get_parameter_index(1, s); + i = i - 1; + strncpy(buf, s, i); + buf[i] = 0; + return_value = func_str_to_double(buf); + return return_value; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 世界时间转换为北京时间 +// 参数说明 *time 保存的时间 +// 返回参数 void +// 使用示例 utc_to_btc(&gps->time); +// 备注信息 内部使用 +//------------------------------------------------------------------------------------------------------------------- +static void utc_to_btc (gps_time_struct *time) +{ + uint8 day_num = 0; + + time->hour = time->hour + 8; + if(23 < time->hour) + { + time->hour -= 24; + time->day += 1; + + if(2 == time->month) + { + day_num = 28; + if((0 == time->year % 4 && 0 != time->year % 100) || 0 == time->year % 400) // 判断是否为闰年 + { + day_num ++; // 闰月 2月为29天 + } + } + else + { + day_num = 31; // 1 3 5 7 8 10 12这些月份为31天 + if(4 == time->month || 6 == time->month || 9 == time->month || 11 == time->month ) + { + day_num = 30; + } + } + + if(time->day > day_num) + { + time->day = 1; + time->month ++; + if(12 < time->month) + { + time->month -= 12; + time->year ++; + } + } + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 RMC语句解析 +// 参数说明 *line 接收到的语句信息 +// 参数说明 *gps 保存解析后的数据 +// 返回参数 uint8 1：解析成功 0：数据有问题不能解析 +// 使用示例 gps_gnrmc_parse((char *)data_buffer, &gps_tau1201); +// 备注信息 内部使用 +//------------------------------------------------------------------------------------------------------------------- +static uint8 gps_gnrmc_parse (char *line, gps_info_struct *gps) +{ + uint8 state = 0, temp = 0; + + double latitude = 0; // 纬度 + double longitude = 0; // 经度 + + float lati_cent_tmp = 0, lati_second_tmp = 0; + float long_cent_tmp = 0, long_second_tmp = 0; + float speed_tmp = 0; + char *buf = line; + uint8 return_state = 0; + + state = buf[get_parameter_index(2, buf)]; + + gps->state = 0; + if('A' == state) // 如果数据有效 则解析数据 + { + return_state = 1; + gps->state = 1; + gps -> ns = buf[get_parameter_index(4, buf)]; + gps -> ew = buf[get_parameter_index(6, buf)]; + + latitude = get_double_number(&buf[get_parameter_index(3, buf)]); + longitude = get_double_number(&buf[get_parameter_index(5, buf)]); + + gps->latitude_degree = (int)latitude / 100; // 纬度转换为度分秒 + lati_cent_tmp = (latitude - gps->latitude_degree * 100); + gps->latitude_cent = (int)lati_cent_tmp; + lati_second_tmp = (lati_cent_tmp - gps->latitude_cent) * 10000; + gps->latitude_second = (int)lati_second_tmp; + + gps->longitude_degree = (int)longitude / 100; // 经度转换为度分秒 + long_cent_tmp = (longitude - gps->longitude_degree * 100); + gps->longitude_cent = (int)long_cent_tmp; + long_second_tmp = (long_cent_tmp - gps->longitude_cent) * 10000; + gps->longitude_second = (int)long_second_tmp; + + gps->latitude = gps->latitude_degree + (double)gps->latitude_cent / 60 + (double)gps->latitude_second / 600000; + gps->longitude = gps->longitude_degree + (double)gps->longitude_cent / 60 + (double)gps->longitude_second / 600000; + + speed_tmp = get_float_number(&buf[get_parameter_index(7, buf)]); // 速度(海里/小时) + gps->speed = speed_tmp * 1.85f; // 转换为公里/小时 + gps->direction = get_float_number(&buf[get_parameter_index(8, buf)]); // 角度 + } + + // 在定位没有生效前也是有时间数据的，可以直接解析 + gps->time.hour = (buf[7] - '0') * 10 + (buf[8] - '0'); // 时间 + gps->time.minute = (buf[9] - '0') * 10 + (buf[10] - '0'); + gps->time.second = (buf[11] - '0') * 10 + (buf[12] - '0'); + temp = get_parameter_index(9, buf); + gps->time.day = (buf[temp + 0] - '0') * 10 + (buf[temp + 1] - '0'); // 日期 + gps->time.month = (buf[temp + 2] - '0') * 10 + (buf[temp + 3] - '0'); + gps->time.year = (buf[temp + 4] - '0') * 10 + (buf[temp + 5] - '0') + 2000; + + utc_to_btc(&gps->time); + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 GGA语句解析 +// 参数说明 *line 接收到的语句信息 +// 参数说明 *gps 保存解析后的数据 +// 返回参数 uint8 1：解析成功 0：数据有问题不能解析 +// 使用示例 gps_gngga_parse((char *)data_buffer, &gps_tau1201); +// 备注信息 内部使用 +//------------------------------------------------------------------------------------------------------------------- +static uint8 gps_gngga_parse (char *line, gps_info_struct *gps) +{ + uint8 state = 0; + char *buf = line; + uint8 return_state = 0; + + state = buf[get_parameter_index(2, buf)]; + + if(',' != state) + { + gps->satellite_used = (uint8)get_int_number(&buf[get_parameter_index(7, buf)]); + gps->height = get_float_number(&buf[get_parameter_index(9, buf)]) + get_float_number(&buf[get_parameter_index(11, buf)]); // 高度 = 海拔高度 + 地球椭球面相对大地水准面的高度 + return_state = 1; + } + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 计算从第一个点到第二个点的距离 +// 参数说明 latitude1 第一个点的纬度 +// 参数说明 longitude1 第一个点的经度 +// 参数说明 latitude2 第二个点的纬度 +// 参数说明 longitude2 第二个点的经度 +// 返回参数 double 返回两点距离 +// 使用示例 get_two_points_distance(latitude1_1, longitude1, latitude2, longitude2); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +double get_two_points_distance (double latitude1, double longitude1, double latitude2, double longitude2) +{ + const double EARTH_RADIUS = 6378137; // 地球半径(单位：m) + double rad_latitude1 = 0; + double rad_latitude2 = 0; + double rad_longitude1 = 0; + double rad_longitude2 = 0; + double distance = 0; + double a = 0; + double b = 0; + + rad_latitude1 = ANGLE_TO_RAD(latitude1); // 根据角度计算弧度 + rad_latitude2 = ANGLE_TO_RAD(latitude2); + rad_longitude1 = ANGLE_TO_RAD(longitude1); + rad_longitude2 = ANGLE_TO_RAD(longitude2); + + a = rad_latitude1 - rad_latitude2; + b = rad_longitude1 - rad_longitude2; + + distance = 2 * asin(sqrt(pow(sin(a / 2), 2) + cos(rad_latitude1) * cos(rad_latitude2) * pow(sin(b / 2), 2))); // google maps 里面实现的算法 + distance = distance * EARTH_RADIUS; + + return distance; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 计算从第一个点到第二个点的方位角 +// 参数说明 latitude1 第一个点的纬度 +// 参数说明 longitude1 第一个点的经度 +// 参数说明 latitude2 第二个点的纬度 +// 参数说明 longitude2 第二个点的经度 +// 返回参数 double 返回方位角（0至360） +// 使用示例 get_two_points_azimuth(latitude1_1, longitude1, latitude2, longitude2); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +double get_two_points_azimuth (double latitude1, double longitude1, double latitude2, double longitude2) +{ + latitude1 = ANGLE_TO_RAD(latitude1); + latitude2 = ANGLE_TO_RAD(latitude2); + longitude1 = ANGLE_TO_RAD(longitude1); + longitude2 = ANGLE_TO_RAD(longitude2); + + double x = sin(longitude2 - longitude1) * cos(latitude2); + double y = cos(latitude1) * sin(latitude2) - sin(latitude1) * cos(latitude2) * cos(longitude2 - longitude1); + double angle = RAD_TO_ANGLE(atan2(x, y)); + return ((0 < angle) ? angle : (angle + 360)); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 解析GPS数据 +// 参数说明 void +// 返回参数 uint8 0-解析成功 1-解析失败 可能数据包错误 +// 使用示例 gps_data_parse(); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +uint8 gps_data_parse (void) +{ + uint8 return_state = 0; + uint8 check_buffer[5] = {'0', 'x', 0x00, 0x00, 0x00}; + uint8 bbc_xor_origin = 0; + uint8 bbc_xor_calculation = 0; + uint32 data_len = 0; + + do + { + if(GPS_STATE_RECEIVED == gps_rmc_state) + { + gps_rmc_state = GPS_STATE_PARSING; + strncpy((char *)&check_buffer[2], strchr((const char *)gps_rmc_buffer, '*') + 1, 2); + bbc_xor_origin = (uint8)func_str_to_hex((char *)check_buffer); + for(bbc_xor_calculation = gps_rmc_buffer[1], data_len = 2; '*' != gps_rmc_buffer[data_len]; data_len ++) + { + bbc_xor_calculation ^= gps_rmc_buffer[data_len]; + } + if(bbc_xor_calculation != bbc_xor_origin) + { + // 数据校验失败 + return_state = 1; + break; + } + + gps_gnrmc_parse((char *)gps_rmc_buffer, &gps_tau1201); + } + gps_rmc_state = GPS_STATE_RECEIVING; + + if(GPS_STATE_RECEIVED == gps_gga_state) + { + gps_gga_state = GPS_STATE_PARSING; + strncpy((char *)&check_buffer[2], strchr((const char *)gps_gga_buffer, '*') + 1, 2); + bbc_xor_origin = (uint8)func_str_to_hex((char *)check_buffer); + + for(bbc_xor_calculation = gps_gga_buffer[1], data_len = 2; '*' != gps_gga_buffer[data_len]; data_len ++) + { + bbc_xor_calculation ^= gps_gga_buffer[data_len]; + } + if(bbc_xor_calculation != bbc_xor_origin) + { + // 数据校验失败 + return_state = 1; + break; + } + + gps_gngga_parse((char *)gps_gga_buffer, &gps_tau1201); + } + gps_gga_state = GPS_STATE_RECEIVING; + + }while(0); + return return_state; +} + + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 GPS串口回调函数 +// 参数说明 void +// 返回参数 void +// 使用示例 gps_uart_callback(); +// 备注信息 此函数需要在串口接收中断内进行调用 +//------------------------------------------------------------------------------------------------------------------- +void gps_uart_callback (void) +{ + uint8 temp_gps[6]; + uint32 temp_length = 0; + + if(gps_tau1201_state) + { + uint8 dat; + while(uart_query_byte(GPS_TAU1201_UART, &dat)) + { + fifo_write_buffer(&gps_tau1201_receiver_fifo, &dat, 1); + } + + if('\n' == dat) + { + // 读取前6个数据 用于判断语句类型 + temp_length = 6; + fifo_read_buffer(&gps_tau1201_receiver_fifo, temp_gps, &temp_length, FIFO_READ_ONLY); + + // 根据不同类型将数据拷贝到不同的缓冲区 + if(0 == strncmp((char *)&temp_gps[3], "RMC", 3)) + { + // 如果没有在解析数据则更新缓冲区的数据 + if(GPS_STATE_PARSING != gps_rmc_state) + { + gps_rmc_state = GPS_STATE_RECEIVED; + temp_length = fifo_used(&gps_tau1201_receiver_fifo); + fifo_read_buffer(&gps_tau1201_receiver_fifo, gps_rmc_buffer, &temp_length, FIFO_READ_AND_CLEAN); + } + } + else if(0 == strncmp((char *)&temp_gps[3], "GGA", 3)) + { + // 如果没有在解析数据则更新缓冲区的数据 + if(GPS_STATE_PARSING != gps_gga_state) + { + gps_gga_state = GPS_STATE_RECEIVED; + temp_length = fifo_used(&gps_tau1201_receiver_fifo); + fifo_read_buffer(&gps_tau1201_receiver_fifo, gps_gga_buffer, &temp_length, FIFO_READ_AND_CLEAN); + } + } + + // 统一将FIFO清空 + fifo_clear(&gps_tau1201_receiver_fifo); + + gps_tau1201_flag = 1; + } + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 GPS初始化 +// 参数说明 void +// 返回参数 void +// 使用示例 gps_init(); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void gps_init (void) +{ + const uint8 set_rate[] = {0xF1, 0xD9, 0x06, 0x42, 0x14, 0x00, 0x00, 0x0A, 0x05, 0x00, 0x64, 0x00, 0x00, 0x00, 0x60, 0xEA, 0x00, 0x00, 0xD0, 0x07, 0x00, 0x00, 0xC8, 0x00, 0x00, 0x00, 0xB8, 0xED}; + const uint8 open_gga[] = {0xF1, 0xD9, 0x06, 0x01, 0x03, 0x00, 0xF0, 0x00, 0x01, 0xFB, 0x10}; + const uint8 open_rmc[] = {0xF1, 0xD9, 0x06, 0x01, 0x03, 0x00, 0xF0, 0x05, 0x01, 0x00, 0x1A}; + + const uint8 close_gll[] = {0xF1, 0xD9, 0x06, 0x01, 0x03, 0x00, 0xF0, 0x01, 0x00, 0xFB, 0x11}; + const uint8 close_gsa[] = {0xF1, 0xD9, 0x06, 0x01, 0x03, 0x00, 0xF0, 0x02, 0x00, 0xFC, 0x13}; + const uint8 close_grs[] = {0xF1, 0xD9, 0x06, 0x01, 0x03, 0x00, 0xF0, 0x03, 0x00, 0xFD, 0x15}; + const uint8 close_gsv[] = {0xF1, 0xD9, 0x06, 0x01, 0x03, 0x00, 0xF0, 0x04, 0x00, 0xFE, 0x17}; + const uint8 close_vtg[] = {0xF1, 0xD9, 0x06, 0x01, 0x03, 0x00, 0xF0, 0x06, 0x00, 0x00, 0x1B}; + const uint8 close_zda[] = {0xF1, 0xD9, 0x06, 0x01, 0x03, 0x00, 0xF0, 0x07, 0x00, 0x01, 0x1D}; + const uint8 close_gst[] = {0xF1, 0xD9, 0x06, 0x01, 0x03, 0x00, 0xF0, 0x08, 0x00, 0x02, 0x1F}; + const uint8 close_txt[] = {0xF1, 0xD9, 0x06, 0x01, 0x03, 0x00, 0xF0, 0x40, 0x00, 0x3A, 0x8F}; + const uint8 close_txt_ant[] = {0xF1, 0xD9, 0x06, 0x01, 0x03, 0x00, 0xF0, 0x20, 0x00, 0x1A, 0x4F}; + + fifo_init(&gps_tau1201_receiver_fifo, FIFO_DATA_8BIT, gps_tau1201_receiver_buffer, GPS_TAU1201_BUFFER_SIZE); + system_delay_ms(500); // 等待GPS启动后开始初始化 + uart_init(GPS_TAU1201_UART, 115200, GPS_TAU1201_RX, GPS_TAU1201_TX); + + uart_write_buffer(GPS_TAU1201_UART, (uint8 *)set_rate, sizeof(set_rate)); // 设置GPS更新速率为10hz 如果不调用此语句则默认为1hz + system_delay_ms(200); + + uart_write_buffer(GPS_TAU1201_UART, (uint8 *)open_rmc, sizeof(open_rmc)); // 开启rmc语句 + system_delay_ms(50); + uart_write_buffer(GPS_TAU1201_UART, (uint8 *)open_gga, sizeof(open_gga)); // 开启gga语句 + system_delay_ms(50); + uart_write_buffer(GPS_TAU1201_UART, (uint8 *)close_gll, sizeof(close_gll)); + system_delay_ms(50); + uart_write_buffer(GPS_TAU1201_UART, (uint8 *)close_gsa, sizeof(close_gsa)); + system_delay_ms(50); + uart_write_buffer(GPS_TAU1201_UART, (uint8 *)close_grs, sizeof(close_grs)); + system_delay_ms(50); + uart_write_buffer(GPS_TAU1201_UART, (uint8 *)close_gsv, sizeof(close_gsv)); + system_delay_ms(50); + uart_write_buffer(GPS_TAU1201_UART, (uint8 *)close_vtg, sizeof(close_vtg)); + system_delay_ms(50); + uart_write_buffer(GPS_TAU1201_UART, (uint8 *)close_zda, sizeof(close_zda)); + system_delay_ms(50); + uart_write_buffer(GPS_TAU1201_UART, (uint8 *)close_gst, sizeof(close_gst)); + system_delay_ms(50); + uart_write_buffer(GPS_TAU1201_UART, (uint8 *)close_txt, sizeof(close_txt)); + system_delay_ms(50); + uart_write_buffer(GPS_TAU1201_UART, (uint8 *)close_txt_ant, sizeof(close_txt_ant)); + system_delay_ms(50); + + gps_tau1201_state = 1; + uart_rx_interrupt(GPS_TAU1201_UART, 1); +} diff --git a/libraries/zf_device/zf_device_gps_tau1201.h b/libraries/zf_device/zf_device_gps_tau1201.h new file mode 100644 index 0000000..1c835c4 --- /dev/null +++ b/libraries/zf_device/zf_device_gps_tau1201.h @@ -0,0 +1,120 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 isr +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-08-10 Teternal first version +* 2022-09-21 SeekFree 修改了处理结构 使得指令区分存放 解决了随机解析时丢失指令的问题 +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* RX 查看 zf_device_gps_tau1201.h 中 GPS_TAU1201_RX 宏定义 +* TX 查看 zf_device_gps_tau1201.h 中 GPS_TAU1201_TX 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_gps_tau1201_h_ +#define _zf_device_gps_tau1201_h_ + +#include "zf_common_typedef.h" + +//-------------------------------------------------------------------------------------------------- +//引脚配置 +//-------------------------------------------------------------------------------------------------- +#define GPS_TAU1201_UART (UART_8) +#define GPS_TAU1201_RX (UART8_MAP3_TX_E14) // GPS RX引脚连接到单片机此 +#define GPS_TAU1201_TX (UART8_MAP3_RX_E15) // GPS TX串口引脚 + +#define ANGLE_TO_RAD(x) ((x) * PI / 180.0) // 角度转换为弧度 +#define RAD_TO_ANGLE(x) ((x) * 180.0 / PI) // 弧度转换为角度 +#define PI (3.1415926535898) + +typedef struct +{ + uint16 year; + uint8 month; + uint8 day; + uint8 hour; + uint8 minute; + uint8 second; +}gps_time_struct; + +typedef struct +{ + gps_time_struct time; // 时间 + + uint8 state; // 有效状态 1：定位有效 0：定位无效 + + uint16 latitude_degree; // 度 + uint16 latitude_cent; // 分 + uint16 latitude_second; // 秒 + uint16 longitude_degree; // 度 + uint16 longitude_cent; // 分 + uint16 longitude_second; // 秒 + + double latitude; // 经度 + double longitude; // 纬度 + + int8 ns; // 纬度半球 N（北半球）或 S（南半球） + int8 ew; // 经度半球 E（东经）或 W（西经） + + float speed; // 速度（公里/每小时） + float direction; // 地面航向（000.0~359.9 度，以真北方为参考基准） + + // 下面两个个信息从GNGGA语句中获取 + uint8 satellite_used; // 用于定位的卫星数量 + float height; // 高度 +}gps_info_struct; + +typedef enum +{ + GPS_STATE_RECEIVING, // 正在接收数据 + GPS_STATE_RECEIVED, // 数据接收完成 + GPS_STATE_PARSING, // 正在解析 +}gps_state_enum; + +extern gps_info_struct gps_tau1201; +extern uint8 gps_tau1201_flag; + + +double get_two_points_distance (double lat1, double lng1, double lat2, double lng2); +double get_two_points_azimuth (double lat1, double lon1, double lat2, double lon2); + +uint8 gps_data_parse (void); + +void gps_uart_callback (void); + +void gps_init (void); + +#endif diff --git a/libraries/zf_device/zf_device_icm20602.c b/libraries/zf_device/zf_device_icm20602.c new file mode 100644 index 0000000..6ef5fea --- /dev/null +++ b/libraries/zf_device/zf_device_icm20602.c @@ -0,0 +1,345 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_icm20602 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶: +* ------------------------------------ +* ģܽ Ƭܽ +* //------------------Ӳ SPI ------------------// +* SCL/SPC 鿴 zf_device_icm20602.h ICM20602_SPC_PIN 궨 +* SDA/DSI 鿴 zf_device_icm20602.h ICM20602_SDI_PIN 궨 +* SA0/SDO 鿴 zf_device_icm20602.h ICM20602_SDO_PIN 궨 +* CS 鿴 zf_device_icm20602.h IPS114_CS_PIN 궨 +* //------------------Ӳ SPI ------------------// +* //------------------ IIC ------------------// +* SCL/SPC 鿴 zf_device_icm20602.h ICM20602_SCL_PIN 궨 +* SDA/DSI 鿴 zf_device_icm20602.h ICM20602_SDA_PIN 궨 +* //------------------ IIC ------------------// +* Դ +* VCC 3.3VԴ +* GND Դ +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_driver_delay.h" +#include "zf_driver_spi.h" +#include "zf_driver_soft_iic.h" + +#include "zf_device_icm20602.h" + +int16 icm20602_gyro_x = 0, icm20602_gyro_y = 0, icm20602_gyro_z = 0; // gyro () +int16 icm20602_acc_x = 0, icm20602_acc_y = 0, icm20602_acc_z = 0; // ٶȼ acc (accelerometer ٶȼ) +float icm20602_transition_factor[2] = {4096, 16.4}; + +#if ICM20602_USE_SOFT_IIC +static soft_iic_info_struct icm20602_iic_struct; + +//------------------------------------------------------------------------------------------------------------------- +// ICM20602 дĴ +// ˵ reg Ĵַ +// ˵ data +// ز void +// ʹʾ icm20602_write_register(ICM20602_PWR_MGMT_1, 0x80); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +#define icm20602_write_register(reg, data) (soft_iic_write_8bit_register(&icm20602_iic_struct, (reg), (data))) + +//------------------------------------------------------------------------------------------------------------------- +// ICM20602 Ĵ +// ˵ reg Ĵַ +// ز uint8 +// ʹʾ icm20602_read_register(ICM20602_WHO_AM_I); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +#define icm20602_read_register(reg) (soft_iic_read_8bit_register(&icm20602_iic_struct, (reg))) + +//------------------------------------------------------------------------------------------------------------------- +// ICM20602 +// ˵ reg Ĵַ +// ˵ data ݻ +// ˵ len ݳ +// ز void +// ʹʾ icm20602_read_registers(ICM20602_ACCEL_XOUT_H, dat, 6); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +#define icm20602_read_registers(reg, data, len) (soft_iic_read_8bit_registers(&icm20602_iic_struct, (reg), (data), (len))) +#else +//------------------------------------------------------------------------------------------------------------------- +// ICM20602 дĴ +// ˵ reg Ĵַ +// ˵ data +// ز void +// ʹʾ icm20602_write_register(ICM20602_PWR_MGMT_1, 0x80); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static void icm20602_write_register (uint8 reg, uint8 data) +{ + ICM20602_CS(0); + spi_write_8bit_register(ICM20602_SPI, reg | ICM20602_SPI_W, data); + ICM20602_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// ICM20602 Ĵ +// ˵ reg Ĵַ +// ز uint8 +// ʹʾ icm20602_read_register(ICM20602_WHO_AM_I); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static uint8 icm20602_read_register (uint8 reg) +{ + uint8 data = 0; + ICM20602_CS(0); + data = spi_read_8bit_register(ICM20602_SPI, reg | ICM20602_SPI_R); + ICM20602_CS(1); + return data; +} + +//------------------------------------------------------------------------------------------------------------------- +// ICM20602 +// ˵ reg Ĵַ +// ˵ data ݻ +// ˵ len ݳ +// ز void +// ʹʾ icm20602_read_registers(ICM20602_ACCEL_XOUT_H, dat, 6); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static void icm20602_read_registers (uint8 reg, uint8 *data, uint32 len) +{ + ICM20602_CS(0); + spi_read_8bit_registers(ICM20602_SPI, reg | ICM20602_SPI_R, data, len); + ICM20602_CS(1); +} +#endif + +//------------------------------------------------------------------------------------------------------------------- +// ICM20602 Լ +// ˵ void +// ز uint8 1-Լʧ 0-Լɹ +// ʹʾ icm20602_self_check(); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static uint8 icm20602_self_check (void) +{ + uint8 dat = 0, return_state = 0; + uint16 timeout_count = 0; + + while(0x12 != dat) // ж ID Ƿȷ + { + if(ICM20602_TIMEOUT_COUNT < timeout_count ++) + { + return_state = 1; + break; + } + dat = icm20602_read_register(ICM20602_WHO_AM_I); + system_delay_ms(10); + } + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// ȡ ICM20602 ٶȼ +// ˵ void +// ز void +// ʹʾ icm20602_get_acc(); // ִиúֱӲ鿴Ӧı +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void icm20602_get_acc (void) +{ + uint8 dat[6]; + + icm20602_read_registers(ICM20602_ACCEL_XOUT_H, dat, 6); + icm20602_acc_x = (int16)(((uint16)dat[0] << 8 | dat[1])); + icm20602_acc_y = (int16)(((uint16)dat[2] << 8 | dat[3])); + icm20602_acc_z = (int16)(((uint16)dat[4] << 8 | dat[5])); +} + +//------------------------------------------------------------------------------------------------------------------- +// ȡICM20602 +// ˵ void +// ز void +// ʹʾ icm20602_get_gyro(); // ִиúֱӲ鿴Ӧı +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void icm20602_get_gyro (void) +{ + uint8 dat[6]; + + icm20602_read_registers(ICM20602_GYRO_XOUT_H, dat, 6); + icm20602_gyro_x = (int16)(((uint16)dat[0] << 8 | dat[1])); + icm20602_gyro_y = (int16)(((uint16)dat[2] << 8 | dat[3])); + icm20602_gyro_z = (int16)(((uint16)dat[4] << 8 | dat[5])); +} + +//------------------------------------------------------------------------------------------------------------------- +// ʼ ICM20602 +// ˵ void +// ز uint8 1-ʼʧ 0-ʼɹ +// ʹʾ icm20602_init(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 icm20602_init (void) +{ + uint8 val = 0x0, return_state = 0; + uint16 timeout_count = 0; + + system_delay_ms(10); // ϵʱ + +#if ICM20602_USE_SOFT_IIC + soft_iic_init(&icm20602_iic_struct, ICM20602_DEV_ADDR, ICM20602_SOFT_IIC_DELAY, ICM20602_SCL_PIN, ICM20602_SDA_PIN); +#else + spi_init(ICM20602_SPI, SPI_MODE0, ICM20602_SPI_SPEED, ICM20602_SPC_PIN, ICM20602_SDI_PIN, ICM20602_SDO_PIN, SPI_CS_NULL); + gpio_init(ICM20602_CS_PIN, GPO, GPIO_HIGH, GPO_PUSH_PULL); +#endif + + do + { + if(icm20602_self_check()) + { + // ˶Ϣ ʾλ + // ô ICM20602 Լʱ˳ + // һ½û ûܾǻ + zf_log(0, "icm20602 self check error."); + return_state = 1; + break; + } + + icm20602_write_register(ICM20602_PWR_MGMT_1, 0x80); // λ豸 + system_delay_ms(2); + + do + { // ȴλɹ + val = icm20602_read_register(ICM20602_PWR_MGMT_1); + if(ICM20602_TIMEOUT_COUNT < timeout_count ++) + { + // ˶Ϣ ʾλ + // ô ICM20602 Լʱ˳ + // һ½û ûܾǻ + zf_log(0, "icm20602 reset error."); + return_state = 1; + break; + } + }while(0x41 != val); + if(1 == return_state) + { + break; + } + + icm20602_write_register(ICM20602_PWR_MGMT_1, 0x01); // ʱ + icm20602_write_register(ICM20602_PWR_MGMT_2, 0x00); // Ǻͼٶȼ + icm20602_write_register(ICM20602_CONFIG, 0x01); // 176HZ 1KHZ + icm20602_write_register(ICM20602_SMPLRT_DIV, 0x07); // SAMPLE_RATE = INTERNAL_SAMPLE_RATE / (1 + SMPLRT_DIV) + + // ICM20602_ACCEL_CONFIG Ĵ + // Ϊ 0x00 ٶȼΪ 2 g ȡļٶȼݳ 16384 תΪλ λ g(m/s^2) + // Ϊ 0x08 ٶȼΪ 4 g ȡļٶȼݳ 8192 תΪλ λ g(m/s^2) + // Ϊ 0x10 ٶȼΪ 8 g ȡļٶȼݳ 4096 תΪλ λ g(m/s^2) + // Ϊ 0x18 ٶȼΪ 16 g ȡļٶȼݳ 2048 תΪλ λ g(m/s^2) + switch(ICM20602_ACC_SAMPLE_DEFAULT) + { + default: + { + zf_log(0, "ICM20602_ACC_SAMPLE_DEFAULT set error."); + return_state = 1; + }break; + case ICM20602_ACC_SAMPLE_SGN_2G: + { + icm20602_write_register(ICM20602_ACCEL_CONFIG, 0x00); + icm20602_transition_factor[0] = 16384; + }break; + case ICM20602_ACC_SAMPLE_SGN_4G: + { + icm20602_write_register(ICM20602_ACCEL_CONFIG, 0x08); + icm20602_transition_factor[0] = 8192; + }break; + case ICM20602_ACC_SAMPLE_SGN_8G: + { + icm20602_write_register(ICM20602_ACCEL_CONFIG, 0x10); + icm20602_transition_factor[0] = 4096; + }break; + case ICM20602_ACC_SAMPLE_SGN_16G: + { + icm20602_write_register(ICM20602_ACCEL_CONFIG, 0x18); + icm20602_transition_factor[0] = 2048; + }break; + } + if(1 == return_state) + { + break; + } + + // ICM20602_GYRO_CONFIG Ĵ + // Ϊ 0x00 Ϊ 250 dps ȡݳ 131 תΪλ λΪ /s + // Ϊ 0x08 Ϊ 500 dps ȡݳ 65.5 תΪλ λΪ /s + // Ϊ 0x10 Ϊ 1000 dps ȡݳ 32.8 תΪλ λΪ /s + // Ϊ 0x18 Ϊ 2000 dps ȡݳ 16.4 תΪλ λΪ /s + switch(ICM20602_GYRO_SAMPLE_DEFAULT) + { + default: + { + zf_log(0, "ICM20602_GYRO_SAMPLE_DEFAULT set error."); + return_state = 1; + }break; + case ICM20602_GYRO_SAMPLE_SGN_250DPS: + { + icm20602_write_register(ICM20602_GYRO_CONFIG, 0x00); + icm20602_transition_factor[1] = 131.0; + }break; + case ICM20602_GYRO_SAMPLE_SGN_500DPS: + { + icm20602_write_register(ICM20602_GYRO_CONFIG, 0x08); + icm20602_transition_factor[1] = 65.5; + }break; + case ICM20602_GYRO_SAMPLE_SGN_1000DPS: + { + icm20602_write_register(ICM20602_GYRO_CONFIG, 0x10); + icm20602_transition_factor[1] = 32.8; + }break; + case ICM20602_GYRO_SAMPLE_SGN_2000DPS: + { + icm20602_write_register(ICM20602_GYRO_CONFIG, 0x18); + icm20602_transition_factor[1] = 16.4; + }break; + } + if(1 == return_state) + { + break; + } + + icm20602_write_register(ICM20602_ACCEL_CONFIG_2, 0x03); // Average 4 samples 44.8HZ //0x23 Average 16 samples + }while(0); + return return_state; +} diff --git a/libraries/zf_device/zf_device_icm20602.h b/libraries/zf_device/zf_device_icm20602.h new file mode 100644 index 0000000..b109c0c --- /dev/null +++ b/libraries/zf_device/zf_device_icm20602.h @@ -0,0 +1,201 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_icm20602 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶: +* ------------------------------------ +* ģܽ Ƭܽ +* //------------------Ӳ SPI ------------------// +* SCL/SPC 鿴 zf_device_icm20602.h ICM20602_SPC_PIN 궨 +* SDA/DSI 鿴 zf_device_icm20602.h ICM20602_SDI_PIN 궨 +* SA0/SDO 鿴 zf_device_icm20602.h ICM20602_SDO_PIN 궨 +* CS 鿴 zf_device_icm20602.h IPS114_CS_PIN 궨 +* //------------------Ӳ SPI ------------------// +* //------------------ IIC ------------------// +* SCL/SPC 鿴 zf_device_icm20602.h ICM20602_SCL_PIN 궨 +* SDA/DSI 鿴 zf_device_icm20602.h ICM20602_SDA_PIN 궨 +* //------------------ IIC ------------------// +* Դ +* VCC 3.3VԴ +* GND Դ +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_icm20602_h_ +#define _zf_device_icm20602_h_ + +#include "zf_common_typedef.h" + + +#define ICM20602_USE_SOFT_IIC 0 // ĬʹӲ SPI ʽ +#if ICM20602_USE_SOFT_IIC // ɫIJȷ ɫҵľûõ +//==================================================== IIC ==================================================== +#define ICM20602_SOFT_IIC_DELAY 100 // IIC ʱʱ ֵԽС IIC ͨԽ +#define ICM20602_SCL_PIN B3 // IIC SCL MPU6050 SCL +#define ICM20602_SDA_PIN B5 // IIC SDA MPU6050 SDA +//==================================================== IIC ==================================================== +#else +//====================================================Ӳ SPI ==================================================== +#define ICM20602_SPI_SPEED (10*1000*1000) // Ӳ SPI +#define ICM20602_SPI SPI_3 // Ӳ SPI +#define ICM20602_SPC_PIN SPI3_MAP0_SCK_B3 // Ӳ SPI SCK +#define ICM20602_SDI_PIN SPI3_MAP0_MOSI_B5 // Ӳ SPI MOSI +#define ICM20602_SDO_PIN SPI3_MAP0_MISO_B4 // Ӳ SPI MISO +//====================================================Ӳ SPI ==================================================== +#endif +#define ICM20602_CS_PIN C10 // CS Ƭѡ +#define ICM20602_CS(x) (x? (gpio_high(ICM20602_CS_PIN)): (gpio_low(ICM20602_CS_PIN))) + +typedef enum +{ + ICM20602_ACC_SAMPLE_SGN_2G , // ٶȼ 2G (ACC = Accelerometer ٶȼ) (SGN = signum ʾΧ) (G = g ٶ g9.80 m/s^2) + ICM20602_ACC_SAMPLE_SGN_4G , // ٶȼ 4G (ACC = Accelerometer ٶȼ) (SGN = signum ʾΧ) (G = g ٶ g9.80 m/s^2) + ICM20602_ACC_SAMPLE_SGN_8G , // ٶȼ 8G (ACC = Accelerometer ٶȼ) (SGN = signum ʾΧ) (G = g ٶ g9.80 m/s^2) + ICM20602_ACC_SAMPLE_SGN_16G, // ٶȼ 16G (ACC = Accelerometer ٶȼ) (SGN = signum ʾΧ) (G = g ٶ g9.80 m/s^2) +}icm20602_acc_sample_config; + +typedef enum +{ + ICM20602_GYRO_SAMPLE_SGN_250DPS , // 250DPS (GYRO = Gyroscope ) (SGN = signum ʾΧ) (DPS = Degree Per Second ٶȵλ /S) + ICM20602_GYRO_SAMPLE_SGN_500DPS , // 500DPS (GYRO = Gyroscope ) (SGN = signum ʾΧ) (DPS = Degree Per Second ٶȵλ /S) + ICM20602_GYRO_SAMPLE_SGN_1000DPS, // 1000DPS (GYRO = Gyroscope ) (SGN = signum ʾΧ) (DPS = Degree Per Second ٶȵλ /S) + ICM20602_GYRO_SAMPLE_SGN_2000DPS, // 2000DPS (GYRO = Gyroscope ) (SGN = signum ʾΧ) (DPS = Degree Per Second ٶȵλ /S) +}icm20602_gyro_sample_config; + +#define ICM20602_ACC_SAMPLE_DEFAULT ( ICM20602_ACC_SAMPLE_SGN_8G ) // Ĭϵ ٶȼ ʼ +#define ICM20602_GYRO_SAMPLE_DEFAULT ( ICM20602_GYRO_SAMPLE_SGN_2000DPS ) // Ĭϵ ʼ + +#define ICM20602_TIMEOUT_COUNT ( 0x00FF ) // ICM20602 ʱ + +//================================================ ICM20602 ڲַ================================================ +#define ICM20602_DEV_ADDR ( 0x69 ) // SA0ӵأ0x68 SA00x69 ģĬ +#define ICM20602_SPI_W ( 0x00 ) +#define ICM20602_SPI_R ( 0x80 ) + +#define ICM20602_XG_OFFS_TC_H ( 0x04 ) +#define ICM20602_XG_OFFS_TC_L ( 0x05 ) +#define ICM20602_YG_OFFS_TC_H ( 0x07 ) +#define ICM20602_YG_OFFS_TC_L ( 0x08 ) +#define ICM20602_ZG_OFFS_TC_H ( 0x0A ) +#define ICM20602_ZG_OFFS_TC_L ( 0x0B ) +#define ICM20602_SELF_TEST_X_ACCEL ( 0x0D ) +#define ICM20602_SELF_TEST_Y_ACCEL ( 0x0E ) +#define ICM20602_SELF_TEST_Z_ACCEL ( 0x0F ) +#define ICM20602_XG_OFFS_USRH ( 0x13 ) +#define ICM20602_XG_OFFS_USRL ( 0x14 ) +#define ICM20602_YG_OFFS_USRH ( 0x15 ) +#define ICM20602_YG_OFFS_USRL ( 0x16 ) +#define ICM20602_ZG_OFFS_USRH ( 0x17 ) +#define ICM20602_ZG_OFFS_USRL ( 0x18 ) +#define ICM20602_SMPLRT_DIV ( 0x19 ) +#define ICM20602_CONFIG ( 0x1A ) +#define ICM20602_GYRO_CONFIG ( 0x1B ) +#define ICM20602_ACCEL_CONFIG ( 0x1C ) +#define ICM20602_ACCEL_CONFIG_2 ( 0x1D ) +#define ICM20602_LP_MODE_CFG ( 0x1E ) +#define ICM20602_ACCEL_WOM_X_THR ( 0x20 ) +#define ICM20602_ACCEL_WOM_Y_THR ( 0x21 ) +#define ICM20602_ACCEL_WOM_Z_THR ( 0x22 ) +#define ICM20602_FIFO_EN ( 0x23 ) +#define ICM20602_FSYNC_INT ( 0x36 ) +#define ICM20602_INT_PIN_CFG ( 0x37 ) +#define ICM20602_INT_ENABLE ( 0x38 ) +#define ICM20602_FIFO_WM_INT_STATUS ( 0x39 ) +#define ICM20602_INT_STATUS ( 0x3A ) +#define ICM20602_ACCEL_XOUT_H ( 0x3B ) +#define ICM20602_ACCEL_XOUT_L ( 0x3C ) +#define ICM20602_ACCEL_YOUT_H ( 0x3D ) +#define ICM20602_ACCEL_YOUT_L ( 0x3E ) +#define ICM20602_ACCEL_ZOUT_H ( 0x3F ) +#define ICM20602_ACCEL_ZOUT_L ( 0x40 ) +#define ICM20602_TEMP_OUT_H ( 0x41 ) +#define ICM20602_TEMP_OUT_L ( 0x42 ) +#define ICM20602_GYRO_XOUT_H ( 0x43 ) +#define ICM20602_GYRO_XOUT_L ( 0x44 ) +#define ICM20602_GYRO_YOUT_H ( 0x45 ) +#define ICM20602_GYRO_YOUT_L ( 0x46 ) +#define ICM20602_GYRO_ZOUT_H ( 0x47 ) +#define ICM20602_GYRO_ZOUT_L ( 0x48 ) +#define ICM20602_SELF_TEST_X_GYRO ( 0x50 ) +#define ICM20602_SELF_TEST_Y_GYRO ( 0x51 ) +#define ICM20602_SELF_TEST_Z_GYRO ( 0x52 ) +#define ICM20602_FIFO_WM_TH1 ( 0x60 ) +#define ICM20602_FIFO_WM_TH2 ( 0x61 ) +#define ICM20602_SIGNAL_PATH_RESET ( 0x68 ) +#define ICM20602_ACCEL_INTEL_CTRL ( 0x69 ) +#define ICM20602_USER_CTRL ( 0x6A ) +#define ICM20602_PWR_MGMT_1 ( 0x6B ) +#define ICM20602_PWR_MGMT_2 ( 0x6C ) +#define ICM20602_I2C_IF ( 0x70 ) +#define ICM20602_FIFO_COUNTH ( 0x72 ) +#define ICM20602_FIFO_COUNTL ( 0x73 ) +#define ICM20602_FIFO_R_W ( 0x74 ) +#define ICM20602_WHO_AM_I ( 0x75 ) +#define ICM20602_XA_OFFSET_H ( 0x77 ) +#define ICM20602_XA_OFFSET_L ( 0x78 ) +#define ICM20602_YA_OFFSET_H ( 0x7A ) +#define ICM20602_YA_OFFSET_L ( 0x7B ) +#define ICM20602_ZA_OFFSET_H ( 0x7D ) +#define ICM20602_ZA_OFFSET_L ( 0x7E ) +//================================================ ICM20602 ڲַ================================================ + +extern int16 icm20602_gyro_x, icm20602_gyro_y, icm20602_gyro_z; // +extern int16 icm20602_acc_x, icm20602_acc_y, icm20602_acc_z; // ٶȼ +extern float icm20602_transition_factor[2]; + +void icm20602_get_acc (void); +void icm20602_get_gyro (void); + +//------------------------------------------------------------------------------------------------------------------- +// ICM20602 ٶȼתΪʵ +// ˵ acc_value ļٶȼ +// ز void +// ʹʾ float data = icm20602_acc_transition(icm20602_acc_x); // λΪ g(m/s^2) +// עϢ +//------------------------------------------------------------------------------------------------------------------- +#define icm20602_acc_transition(acc_value) ((float)(acc_value) / icm20602_transition_factor[0]) + +//------------------------------------------------------------------------------------------------------------------- +// ICM20602 תΪʵ +// ˵ gyro_value +// ز void +// ʹʾ float data = icm20602_gyro_transition(icm20602_gyro_x); // λΪ /s +// עϢ +//------------------------------------------------------------------------------------------------------------------- +#define icm20602_gyro_transition(gyro_value) ((float)(gyro_value) / icm20602_transition_factor[1]) + +uint8 icm20602_init (void); + +#endif + diff --git a/libraries/zf_device/zf_device_imu660ra.c b/libraries/zf_device/zf_device_imu660ra.c new file mode 100644 index 0000000..6fdf9f1 --- /dev/null +++ b/libraries/zf_device/zf_device_imu660ra.c @@ -0,0 +1,338 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_imu660ra +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* // 硬件 SPI 引脚 +* SCL/SPC 查看 zf_device_imu660ra.h 中 IMU660RA_SPC_PIN 宏定义 +* SDA/DSI 查看 zf_device_imu660ra.h 中 IMU660RA_SDI_PIN 宏定义 +* SA0/SDO 查看 zf_device_imu660ra.h 中 IMU660RA_SDO_PIN 宏定义 +* CS 查看 zf_device_imu660ra.h 中 IMU660RA_CS_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* 其余引脚悬空 +* +* // 软件 IIC 引脚 +* SCL/SPC 查看 zf_device_imu660ra.h 中 IMU660RA_SCL_PIN 宏定义 +* SDA/DSI 查看 zf_device_imu660ra.h 中 IMU660RA_SDA_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* 其余引脚悬空 +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_debug.h" +#include "zf_driver_delay.h" +#include "zf_driver_spi.h" +#include "zf_driver_gpio.h" +#include "zf_driver_soft_iic.h" +#include "zf_device_config.h" + +#include "zf_device_imu660ra.h" + +int16 imu660ra_gyro_x = 0, imu660ra_gyro_y = 0, imu660ra_gyro_z = 0; // 三轴陀螺仪数据 gyro (陀螺仪) +int16 imu660ra_acc_x = 0, imu660ra_acc_y = 0, imu660ra_acc_z = 0; // 三轴加速度计数据 acc (accelerometer 加速度计) +float imu660ra_transition_factor[2] = {4096, 16.4}; + +#if IMU660RA_USE_SOFT_IIC +static soft_iic_info_struct imu660ra_iic_struct; + +#define imu660ra_write_register(reg, data) (soft_iic_write_8bit_register(&imu660ra_iic_struct, (reg), (data))) +#define imu660ra_write_registers(reg, data, len) (soft_iic_write_8bit_registers(&imu660ra_iic_struct, (reg), (data), (len))) +#define imu660ra_read_register(reg) (soft_iic_read_8bit_register(&imu660ra_iic_struct, (reg))) +#define imu660ra_read_registers(reg, data, len) (soft_iic_read_8bit_registers(&imu660ra_iic_struct, (reg), (data), (len))) +#else +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU660RA 写寄存器 +// 参数说明 reg 寄存器地址 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 imu660ra_write_register(IMU660RA_PWR_CONF, 0x00); // 关闭高级省电模式 +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static void imu660ra_write_register(uint8 reg, uint8 data) +{ + IMU660RA_CS(0); + spi_write_8bit_register(IMU660RA_SPI, reg | IMU660RA_SPI_W, data); + IMU660RA_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU660RA 写数据 +// 参数说明 reg 寄存器地址 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 imu660ra_write_registers(IMU660RA_INIT_DATA, imu660ra_config_file, sizeof(imu660ra_config_file)); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static void imu660ra_write_registers(uint8 reg, const uint8 *data, uint32 len) +{ + IMU660RA_CS(0); + spi_write_8bit_registers(IMU660RA_SPI, reg | IMU660RA_SPI_W, data, len); + IMU660RA_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU660RA 读寄存器 +// 参数说明 reg 寄存器地址 +// 返回参数 uint8 数据 +// 使用示例 imu660ra_read_register(IMU660RA_CHIP_ID); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static uint8 imu660ra_read_register(uint8 reg) +{ + uint8 data[2]; + IMU660RA_CS(0); + spi_read_8bit_registers(IMU660RA_SPI, reg | IMU660RA_SPI_R, data, 2); + IMU660RA_CS(1); + return data[1]; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU660RA 读数据 +// 参数说明 reg 寄存器地址 +// 参数说明 data 数据缓冲区 +// 参数说明 len 数据长度 +// 返回参数 void +// 使用示例 imu660ra_read_registers(IMU660RA_ACC_ADDRESS, dat, 6); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static void imu660ra_read_registers(uint8 reg, uint8 *data, uint32 len) +{ + uint8 temp_data[8]; + IMU660RA_CS(0); + spi_read_8bit_registers(IMU660RA_SPI, reg | IMU660RA_SPI_R, temp_data, len + 1); + IMU660RA_CS(1); + for(int i = 0; i < len; i ++) + { + *(data ++) = temp_data[i + 1]; + } +} +#endif + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU660RA 自检 +// 参数说明 void +// 返回参数 uint8 1-自检失败 0-自检成功 +// 使用示例 imu660ra_self_check(); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static uint8 imu660ra_self_check (void) +{ + uint8 dat = 0, return_state = 0; + uint16 timeout_count = 0; + do + { + if(timeout_count ++ > IMU660RA_TIMEOUT_COUNT) + { + return_state = 1; + break; + } + dat = imu660ra_read_register(IMU660RA_CHIP_ID); + system_delay_ms(1); + }while(0x24 != dat); // 读取设备ID是否等于0X24，如果不是0X24则认为没检测到设备 + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 获取 IMU660RA 加速度计数据 +// 参数说明 void +// 返回参数 void +// 使用示例 imu660ra_get_acc(); // 执行该函数后，直接查看对应的变量即可 +// 备注信息 使用 SPI 的采集时间为69us +// 使用 IIC 的采集时间为126us 采集加速度计的时间与采集陀螺仪的时间一致的原因是都只是读取寄存器数据 +//------------------------------------------------------------------------------------------------------------------- +void imu660ra_get_acc (void) +{ + uint8 dat[6]; + + imu660ra_read_registers(IMU660RA_ACC_ADDRESS, dat, 6); + imu660ra_acc_x = (int16)(((uint16)dat[1]<<8 | dat[0])); + imu660ra_acc_y = (int16)(((uint16)dat[3]<<8 | dat[2])); + imu660ra_acc_z = (int16)(((uint16)dat[5]<<8 | dat[4])); +} +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 获取 IMU660RA 陀螺仪数据 +// 参数说明 void +// 返回参数 void +// 使用示例 imu660ra_get_gyro(); // 执行该函数后，直接查看对应的变量即可 +// 备注信息 使用 SPI 的采集时间为69us +// 使用 IIC 的采集时间为126us +//------------------------------------------------------------------------------------------------------------------- +void imu660ra_get_gyro (void) +{ + uint8 dat[6]; + + imu660ra_read_registers(IMU660RA_GYRO_ADDRESS, dat, 6); + imu660ra_gyro_x = (int16)(((uint16)dat[1]<<8 | dat[0])); + imu660ra_gyro_y = (int16)(((uint16)dat[3]<<8 | dat[2])); + imu660ra_gyro_z = (int16)(((uint16)dat[5]<<8 | dat[4])); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 初始化 IMU660RA +// 参数说明 void +// 返回参数 uint8 1-初始化失败 0-初始化成功 +// 使用示例 imu660ra_init(); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +uint8 imu660ra_init (void) +{ + uint8 return_state = 0; + system_delay_ms(20); // 等待设备上电成功 + +#if IMU660RA_USE_SOFT_IIC + soft_iic_init(&imu660ra_iic_struct, IMU660RA_DEV_ADDR, IMU660RA_SOFT_IIC_DELAY, IMU660RA_SCL_PIN, IMU660RA_SDA_PIN); // 配置 IMU660RA 的 IIC 端口 +#else + spi_init(IMU660RA_SPI, SPI_MODE0, IMU660RA_SPI_SPEED, IMU660RA_SPC_PIN, IMU660RA_SDI_PIN, IMU660RA_SDO_PIN, SPI_CS_NULL); // 配置 IMU660RA 的 SPI 端口 + gpio_init(IMU660RA_CS_PIN, GPO, GPIO_HIGH, GPO_PUSH_PULL); // 配置 IMU660RA 的CS端口 + imu660ra_read_register(IMU660RA_CHIP_ID); // 读取一下设备ID 将设备设置为SPI模式 +#endif + do{ + if(imu660ra_self_check()) // IMU660RA 自检 + { + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么就是 IMU660RA 自检出错并超时退出了 + // 检查一下接线有没有问题 如果没问题可能就是坏了 + zf_log(0, "imu660ra self check error."); + return_state = 1; + break; + } + imu660ra_write_register(IMU660RA_PWR_CONF, 0x00); // 关闭高级省电模式 + system_delay_ms(1); + imu660ra_write_register(IMU660RA_INIT_CTRL, 0x00); // 开始对模块进行初始化配置 + imu660ra_write_registers(IMU660RA_INIT_DATA, imu660ra_config_file, sizeof(imu660ra_config_file)); // 输出配置文件 + imu660ra_write_register(IMU660RA_INIT_CTRL, 0x01); // 初始化配置结束 + system_delay_ms(20); + if(1 != imu660ra_read_register(IMU660RA_INT_STA)) // 检查是否配置完成 + { + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么就是 IMU660RA 配置初始化文件出错了 + // 检查一下接线有没有问题 如果没问题可能就是坏了 + zf_log(0, "imu660ra init error."); + return_state = 1; + break; + } + imu660ra_write_register(IMU660RA_PWR_CTRL, 0x0E); // 开启性能模式 使能陀螺仪、加速度、温度传感器 + imu660ra_write_register(IMU660RA_ACC_CONF, 0xA7); // 加速度采集配置 性能模式 正常采集 50Hz 采样频率 + imu660ra_write_register(IMU660RA_GYR_CONF, 0xA9); // 陀螺仪采集配置 性能模式 正常采集 200Hz 采样频率 + + // IMU660RA_ACC_SAMPLE 寄存器 + // 设置为 0x00 加速度计量程为 ±2 g 获取到的加速度计数据除以 16384 可以转化为带物理单位的数据 单位 g(m/s^2) + // 设置为 0x01 加速度计量程为 ±4 g 获取到的加速度计数据除以 8192 可以转化为带物理单位的数据 单位 g(m/s^2) + // 设置为 0x02 加速度计量程为 ±8 g 获取到的加速度计数据除以 4096 可以转化为带物理单位的数据 单位 g(m/s^2) + // 设置为 0x03 加速度计量程为 ±16 g 获取到的加速度计数据除以 2048 可以转化为带物理单位的数据 单位 g(m/s^2) + switch(IMU660RA_ACC_SAMPLE_DEFAULT) + { + default: + { + zf_log(0, "IMU660RA_ACC_SAMPLE_DEFAULT set error."); + return_state = 1; + }break; + case IMU660RA_ACC_SAMPLE_SGN_2G: + { + imu660ra_write_register(IMU660RA_ACC_RANGE, 0x00); + imu660ra_transition_factor[0] = 16384; + }break; + case IMU660RA_ACC_SAMPLE_SGN_4G: + { + imu660ra_write_register(IMU660RA_ACC_RANGE, 0x01); + imu660ra_transition_factor[0] = 8192; + }break; + case IMU660RA_ACC_SAMPLE_SGN_8G: + { + imu660ra_write_register(IMU660RA_ACC_RANGE, 0x02); + imu660ra_transition_factor[0] = 4096; + }break; + case IMU660RA_ACC_SAMPLE_SGN_16G: + { + imu660ra_write_register(IMU660RA_ACC_RANGE, 0x03); + imu660ra_transition_factor[0] = 2048; + }break; + } + if(1 == return_state) + { + break; + } + + // IMU660RA_GYR_RANGE 寄存器 + // 设置为 0x04 陀螺仪量程为 ±125 dps 获取到的陀螺仪数据除以 262.4 可以转化为带物理单位的数据 单位为 °/s + // 设置为 0x03 陀螺仪量程为 ±250 dps 获取到的陀螺仪数据除以 131.2 可以转化为带物理单位的数据 单位为 °/s + // 设置为 0x02 陀螺仪量程为 ±500 dps 获取到的陀螺仪数据除以 65.6 可以转化为带物理单位的数据 单位为 °/s + // 设置为 0x01 陀螺仪量程为 ±1000 dps 获取到的陀螺仪数据除以 32.8 可以转化为带物理单位的数据 单位为 °/s + // 设置为 0x00 陀螺仪量程为 ±2000 dps 获取到的陀螺仪数据除以 16.4 可以转化为带物理单位的数据 单位为 °/s + switch(IMU660RA_GYRO_SAMPLE_DEFAULT) + { + default: + { + zf_log(0, "IMU660RA_GYRO_SAMPLE_DEFAULT set error."); + return_state = 1; + }break; + case IMU660RA_GYRO_SAMPLE_SGN_125DPS: + { + imu660ra_write_register(IMU660RA_GYR_RANGE, 0x04); + imu660ra_transition_factor[1] = 262.4; + }break; + case IMU660RA_GYRO_SAMPLE_SGN_250DPS: + { + imu660ra_write_register(IMU660RA_GYR_RANGE, 0x03); + imu660ra_transition_factor[1] = 131.2; + }break; + case IMU660RA_GYRO_SAMPLE_SGN_500DPS: + { + imu660ra_write_register(IMU660RA_GYR_RANGE, 0x02); + imu660ra_transition_factor[1] = 65.6; + }break; + case IMU660RA_GYRO_SAMPLE_SGN_1000DPS: + { + imu660ra_write_register(IMU660RA_GYR_RANGE, 0x01); + imu660ra_transition_factor[1] = 32.8; + }break; + case IMU660RA_GYRO_SAMPLE_SGN_2000DPS: + { + imu660ra_write_register(IMU660RA_GYR_RANGE, 0x00); + imu660ra_transition_factor[1] = 16.4; + }break; + } + if(1 == return_state) + { + break; + } + }while(0); + return return_state; +} + + diff --git a/libraries/zf_device/zf_device_imu660ra.h b/libraries/zf_device/zf_device_imu660ra.h new file mode 100644 index 0000000..93fe0f7 --- /dev/null +++ b/libraries/zf_device/zf_device_imu660ra.h @@ -0,0 +1,151 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_imu660ra +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* // 硬件 SPI 引脚 +* SCL/SPC 查看 zf_device_imu660ra.h 中 IMU660RA_SPC_PIN 宏定义 +* SDA/DSI 查看 zf_device_imu660ra.h 中 IMU660RA_SDI_PIN 宏定义 +* SA0/SDO 查看 zf_device_imu660ra.h 中 IMU660RA_SDO_PIN 宏定义 +* CS 查看 zf_device_imu660ra.h 中 IMU660RA_CS_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* 其余引脚悬空 +* +* // 软件 IIC 引脚 +* SCL/SPC 查看 zf_device_imu660ra.h 中 IMU660RA_SCL_PIN 宏定义 +* SDA/DSI 查看 zf_device_imu660ra.h 中 IMU660RA_SDA_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* 其余引脚悬空 +* ------------------------------------ +********************************************************************************************************************/ +#ifndef _zf_device_imu660ra_h_ +#define _zf_device_imu660ra_h_ + +#include "zf_common_typedef.h" + +#define IMU660RA_USE_SOFT_IIC (0) // 默认使用硬件 SPI 方式驱动 +#if IMU660RA_USE_SOFT_IIC // 这两段 颜色正常的才是正确的 颜色灰的就是没有用的 +//====================================================软件 IIC 驱动==================================================== +#define IMU660RA_SOFT_IIC_DELAY (10 ) // 软件 IIC 的时钟延时周期 数值越小 IIC 通信速率越快 +#define IMU660RA_SCL_PIN (B13) // 软件 IIC SCL 引脚 连接 IMU660RA 的 SCL 引脚 +#define IMU660RA_SDA_PIN (B15) // 软件 IIC SDA 引脚 连接 IMU660RA 的 SDA 引脚 +//====================================================软件 IIC 驱动==================================================== +#else + +//====================================================硬件 SPI 驱动==================================================== +#define IMU660RA_SPI_SPEED (10*1000*1000) // 硬件 SPI 速率 +#define IMU660RA_SPI SPI_3 // 硬件 SPI 号 +#define IMU660RA_SPC_PIN SPI3_MAP0_SCK_B3 // 硬件 SPI SCK 引脚 +#define IMU660RA_SDI_PIN SPI3_MAP0_MOSI_B5 // 硬件 SPI MOSI 引脚 +#define IMU660RA_SDO_PIN SPI3_MAP0_MISO_B4 // 硬件 SPI MISO 引脚 + +//====================================================硬件 SPI 驱动==================================================== +#endif +#define IMU660RA_CS_PIN (C10) // CS 片选引脚 +#define IMU660RA_CS(x) ((x) ? (gpio_high(IMU660RA_CS_PIN)) : (gpio_low(IMU660RA_CS_PIN))) + +typedef enum +{ + IMU660RA_ACC_SAMPLE_SGN_2G , // 加速度计量程 ±2G (ACC = Accelerometer 加速度计) (SGN = signum 带符号数 表示正负范围) (G = g 重力加速度 g≈9.80 m/s^2) + IMU660RA_ACC_SAMPLE_SGN_4G , // 加速度计量程 ±4G (ACC = Accelerometer 加速度计) (SGN = signum 带符号数 表示正负范围) (G = g 重力加速度 g≈9.80 m/s^2) + IMU660RA_ACC_SAMPLE_SGN_8G , // 加速度计量程 ±8G (ACC = Accelerometer 加速度计) (SGN = signum 带符号数 表示正负范围) (G = g 重力加速度 g≈9.80 m/s^2) + IMU660RA_ACC_SAMPLE_SGN_16G, // 加速度计量程 ±16G (ACC = Accelerometer 加速度计) (SGN = signum 带符号数 表示正负范围) (G = g 重力加速度 g≈9.80 m/s^2) +}imu660ra_acc_sample_config; + +typedef enum +{ + IMU660RA_GYRO_SAMPLE_SGN_125DPS , // 陀螺仪量程 ±125DPS (GYRO = Gyroscope 陀螺仪) (SGN = signum 带符号数 表示正负范围) (DPS = Degree Per Second 角速度单位 °/S) + IMU660RA_GYRO_SAMPLE_SGN_250DPS , // 陀螺仪量程 ±250DPS (GYRO = Gyroscope 陀螺仪) (SGN = signum 带符号数 表示正负范围) (DPS = Degree Per Second 角速度单位 °/S) + IMU660RA_GYRO_SAMPLE_SGN_500DPS , // 陀螺仪量程 ±500DPS (GYRO = Gyroscope 陀螺仪) (SGN = signum 带符号数 表示正负范围) (DPS = Degree Per Second 角速度单位 °/S) + IMU660RA_GYRO_SAMPLE_SGN_1000DPS, // 陀螺仪量程 ±1000DPS (GYRO = Gyroscope 陀螺仪) (SGN = signum 带符号数 表示正负范围) (DPS = Degree Per Second 角速度单位 °/S) + IMU660RA_GYRO_SAMPLE_SGN_2000DPS, // 陀螺仪量程 ±2000DPS (GYRO = Gyroscope 陀螺仪) (SGN = signum 带符号数 表示正负范围) (DPS = Degree Per Second 角速度单位 °/S) +}imu660ra_gyro_sample_config; + +#define IMU660RA_ACC_SAMPLE_DEFAULT ( IMU660RA_ACC_SAMPLE_SGN_8G ) // 在这设置默认的 加速度计 初始化量程 +#define IMU660RA_GYRO_SAMPLE_DEFAULT ( IMU660RA_GYRO_SAMPLE_SGN_2000DPS ) // 在这设置默认的 陀螺仪 初始化量程 + +#define IMU660RA_TIMEOUT_COUNT ( 0x00FF ) // IMU660RA 超时计数 + +//================================================定义 IMU660RA 内部地址================================================ +#define IMU660RA_DEV_ADDR ( 0x69 ) // SA0接地：0x68 SA0上拉：0x69 模块默认上拉 +#define IMU660RA_SPI_W ( 0x00 ) +#define IMU660RA_SPI_R ( 0x80 ) + +#define IMU660RA_CHIP_ID ( 0x00 ) +#define IMU660RA_PWR_CONF ( 0x7C ) +#define IMU660RA_PWR_CTRL ( 0x7D ) +#define IMU660RA_INIT_CTRL ( 0x59 ) +#define IMU660RA_INIT_DATA ( 0x5E ) +#define IMU660RA_INT_STA ( 0x21 ) +#define IMU660RA_ACC_ADDRESS ( 0x0C ) +#define IMU660RA_GYRO_ADDRESS ( 0x12 ) +#define IMU660RA_ACC_CONF ( 0x40 ) +#define IMU660RA_ACC_RANGE ( 0x41 ) +#define IMU660RA_GYR_CONF ( 0x42 ) +#define IMU660RA_GYR_RANGE ( 0x43 ) +//================================================定义 IMU660RA 内部地址================================================ + +extern int16 imu660ra_gyro_x, imu660ra_gyro_y, imu660ra_gyro_z; // 三轴陀螺仪数据 gyro (陀螺仪) +extern int16 imu660ra_acc_x, imu660ra_acc_y, imu660ra_acc_z; // 三轴加速度计数据 acc (accelerometer 加速度计) +extern float imu660ra_transition_factor[2]; + +void imu660ra_get_acc (void); // 获取 IMU660RA 加速度计数据 +void imu660ra_get_gyro (void); // 获取 IMU660RA 陀螺仪数据 + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 将 IMU660RA 加速度计数据转换为实际物理数据 +// 参数说明 acc_value 任意轴的加速度计数据 +// 返回参数 void +// 使用示例 float data = imu660ra_acc_transition(imu660ra_acc_x); // 单位为 g(m/s^2) +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +#define imu660ra_acc_transition(acc_value) ((float)(acc_value) / imu660ra_transition_factor[0]) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 将 IMU660RA 陀螺仪数据转换为实际物理数据 +// 参数说明 gyro_value 任意轴的陀螺仪数据 +// 返回参数 void +// 使用示例 float data = imu660ra_gyro_transition(imu660ra_gyro_x); // 单位为 °/s +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +#define imu660ra_gyro_transition(gyro_value) ((float)(gyro_value) / imu660ra_transition_factor[1]) + +uint8 imu660ra_init (void); // 初始化 IMU660RA + +#endif + diff --git a/libraries/zf_device/zf_device_imu963ra.c b/libraries/zf_device/zf_device_imu963ra.c new file mode 100644 index 0000000..ba22201 --- /dev/null +++ b/libraries/zf_device/zf_device_imu963ra.c @@ -0,0 +1,531 @@ +/*/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_imu963ra +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* // 硬件 SPI 引脚 +* SCL/SPC 查看 zf_device_imu963ra.h 中 IMU963RA_SPC_PIN 宏定义 +* SDA/DSI 查看 zf_device_imu963ra.h 中 IMU963RA_SDI_PIN 宏定义 +* SA0/SDO 查看 zf_device_imu963ra.h 中 IMU963RA_SDO_PIN 宏定义 +* CS 查看 zf_device_imu963ra.h 中 IMU963RA_CS_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* 其余引脚悬空 +* +* // 软件 IIC 引脚 +* SCL/SPC 查看 zf_device_imu963ra.h 中 IMU963RA_SCL_PIN 宏定义 +* SDA/DSI 查看 zf_device_imu963ra.h 中 IMU963RA_SDA_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* 其余引脚悬空 +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_driver_delay.h" +#include "zf_driver_spi.h" +#include "zf_driver_soft_iic.h" + +#include "zf_device_imu963ra.h" + +int16 imu963ra_gyro_x = 0, imu963ra_gyro_y = 0, imu963ra_gyro_z = 0; +int16 imu963ra_acc_x = 0, imu963ra_acc_y = 0, imu963ra_acc_z = 0; +int16 imu963ra_mag_x = 0, imu963ra_mag_y = 0, imu963ra_mag_z = 0; +float imu963ra_transition_factor[3] = {4098, 14.3, 3000}; + +#if IMU963RA_USE_SOFT_IIC +static soft_iic_info_struct imu963ra_iic_struct; + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU963RA 写寄存器 +// 参数说明 reg 寄存器地址 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 imu963ra_write_acc_gyro_register(IMU963RA_SLV0_CONFIG, 0x00); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define imu963ra_write_acc_gyro_register(reg,data) (soft_iic_write_8bit_register(&imu963ra_iic_struct,reg,data)) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU963RA 读寄存器 +// 参数说明 reg 寄存器地址 +// 返回参数 uint8 数据 +// 使用示例 imu963ra_read_acc_gyro_register(IMU963RA_STATUS_MASTER); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define imu963ra_read_acc_gyro_register(reg) (soft_iic_sccb_read_register(&imu963ra_iic_struct,reg)) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU963RA 读数据 内部调用 +// 参数说明 reg 寄存器地址 +// 参数说明 data 数据缓冲区 +// 参数说明 len 数据长度 +// 返回参数 void +// 使用示例 imu963ra_read_acc_gyro_registers(IMU963RA_OUTX_L_A, dat, 6); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define imu963ra_read_acc_gyro_registers(reg,data,len) (soft_iic_read_8bit_registers(&imu963ra_iic_struct,reg,data,len)) +#else +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU963RA 写寄存器 +// 参数说明 reg 寄存器地址 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 imu963ra_write_acc_gyro_register(IMU963RA_SLV0_CONFIG, 0x00); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static void imu963ra_write_acc_gyro_register(uint8 reg, uint8 data) +{ + IMU963RA_CS(0); + spi_write_8bit_register(IMU963RA_SPI, reg | IMU963RA_SPI_W, data); + + IMU963RA_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU963RA 读寄存器 +// 参数说明 reg 寄存器地址 +// 返回参数 uint8 数据 +// 使用示例 imu963ra_read_acc_gyro_register(IMU963RA_STATUS_MASTER); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static uint8 imu963ra_read_acc_gyro_register(uint8 reg) +{ + uint8 data = 0; + IMU963RA_CS(0); + data = spi_read_8bit_register(IMU963RA_SPI, reg | IMU963RA_SPI_R); + + IMU963RA_CS(1); + return data; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU963RA 读数据 内部调用 +// 参数说明 reg 寄存器地址 +// 参数说明 data 数据缓冲区 +// 参数说明 len 数据长度 +// 返回参数 void +// 使用示例 imu963ra_read_acc_gyro_registers(IMU963RA_OUTX_L_A, dat, 6); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static void imu963ra_read_acc_gyro_registers(uint8 reg, uint8 *data, uint32 len) +{ + IMU963RA_CS(0); + spi_read_8bit_registers(IMU963RA_SPI, reg | IMU963RA_SPI_R, data, len); + + IMU963RA_CS(1); +} +#endif + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU963RA 作为 IIC 主机向磁力计写数据 +// 参数说明 addr 目标地址 +// 参数说明 reg 目标寄存器 +// 参数说明 data 数据 +// 返回参数 uint8 1-失败 0-成功 +// 使用示例 imu963ra_write_mag_register(IMU963RA_MAG_ADDR, IMU963RA_MAG_CONTROL2, 0x80); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static uint8 imu963ra_write_mag_register (uint8 addr, uint8 reg, uint8 data) +{ + uint8 return_state = 0; + uint16 timeout_count = 0; + + addr = addr << 1; + imu963ra_write_acc_gyro_register(IMU963RA_SLV0_CONFIG, 0x00); // 从机0配置清除 + imu963ra_write_acc_gyro_register(IMU963RA_SLV0_ADD, addr | 0); // 设置地磁计地址（注意这里需要设置8位的I2C地址） 0x2C + imu963ra_write_acc_gyro_register(IMU963RA_SLV0_SUBADD, reg); // 需要写入的寄存器地址 + imu963ra_write_acc_gyro_register(IMU963RA_DATAWRITE_SLV0, data); // 需要写入的数据 + imu963ra_write_acc_gyro_register(IMU963RA_MASTER_CONFIG, 0x4C); // 仅在第一个周期启用通讯 开启上拉 I2C主机使能 + + // 等待通讯成功 + while(0 == (0x80 & imu963ra_read_acc_gyro_register(IMU963RA_STATUS_MASTER))) + { + if(IMU963RA_TIMEOUT_COUNT < timeout_count ++) + { + return_state = 1; + break; + } + system_delay_ms(2); + } + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU963RA 作为 IIC 主机向磁力计读数据 +// 参数说明 addr 目标地址 +// 参数说明 reg 目标寄存器 +// 返回参数 uint8 读取的数据 +// 使用示例 imu963ra_read_mag_register(IMU963RA_MAG_ADDR, IMU963RA_MAG_CHIP_ID); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static uint8 imu963ra_read_mag_register (uint8 addr, uint8 reg) +{ + uint16 timeout_count = 0; + + addr = addr << 1; + imu963ra_write_acc_gyro_register(IMU963RA_SLV0_ADD, addr | 1); // 设置地磁计地址（注意这里需要设置8位的I2C地址） 0x2C + imu963ra_write_acc_gyro_register(IMU963RA_SLV0_SUBADD, reg); // 需要读取的寄存器地址 + imu963ra_write_acc_gyro_register(IMU963RA_SLV0_CONFIG, 0x01); + imu963ra_write_acc_gyro_register(IMU963RA_MASTER_CONFIG, 0x4C); // 仅在第一个周期启用通讯 开启上拉 I2C主机使能 + + // 等待通讯成功 + while(0 == (0x01 & imu963ra_read_acc_gyro_register(IMU963RA_STATUS_MASTER))) + { + if(IMU963RA_TIMEOUT_COUNT < timeout_count ++) + { + break; + } + system_delay_ms(2); + } + + return (imu963ra_read_acc_gyro_register(IMU963RA_SENSOR_HUB_1)); // 返回读取到的数据 +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU963RA 作为 IIC 主机向磁力计自动写数据 +// 参数说明 addr 目标地址 +// 参数说明 reg 目标寄存器 +// 返回参数 void +// 使用示例 imu963ra_connect_mag(IMU963RA_MAG_ADDR, IMU963RA_MAG_OUTX_L); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static void imu963ra_connect_mag (uint8 addr, uint8 reg) +{ + addr = addr << 1; + + imu963ra_write_acc_gyro_register(IMU963RA_SLV0_ADD, addr | 1); // 设置地磁计地址（注意这里需要设置8位的I2C地址） 0x2C + imu963ra_write_acc_gyro_register(IMU963RA_SLV0_SUBADD, reg); // 需要读取的寄存器地址 + imu963ra_write_acc_gyro_register(IMU963RA_SLV0_CONFIG, 0x06); + imu963ra_write_acc_gyro_register(IMU963RA_MASTER_CONFIG, 0x6C); // 仅在第一个周期启用通讯 开启上拉 I2C主机使能 +} + + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU963RA 六轴自检 内部调用 +// 参数说明 void +// 返回参数 uint8 1-自检失败 0-自检成功 +// 使用示例 imu963ra_acc_gyro_self_check(); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static uint8 imu963ra_acc_gyro_self_check (void) +{ + uint8 return_state = 0; + uint8 dat = 0; + uint16 timeout_count = 0; + + while(0x6B != dat) // 判断 ID 是否正确 + { + if(IMU963RA_TIMEOUT_COUNT < timeout_count ++) + { + return_state = 1; + break; + } + dat = imu963ra_read_acc_gyro_register(IMU963RA_WHO_AM_I); + system_delay_ms(10); + } + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IMU963RA 磁力计自检 内部调用 +// 参数说明 void +// 返回参数 uint8 1-自检失败 0-自检成功 +// 使用示例 imu963ra_mag_self_check(); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static uint8 imu963ra_mag_self_check (void) +{ + uint8 return_state = 0; + uint8 dat = 0; + uint16 timeout_count = 0; + + while(0xff != dat) // 判断 ID 是否正确 + { + if(IMU963RA_TIMEOUT_COUNT < timeout_count ++) + { + return_state = 1; + break; + } + dat = imu963ra_read_mag_register(IMU963RA_MAG_ADDR, IMU963RA_MAG_CHIP_ID); + system_delay_ms(10); + } + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 获取 IMU963RA 加速度计数据 +// 参数说明 void +// 返回参数 void +// 使用示例 imu963ra_get_acc(); +// 备注信息 执行该函数后，直接查看对应的变量即可 +//------------------------------------------------------------------------------------------------------------------- +void imu963ra_get_acc (void) +{ + uint8 dat[6]; + + imu963ra_read_acc_gyro_registers(IMU963RA_OUTX_L_A, dat, 6); + imu963ra_acc_x = (int16)(((uint16)dat[1]<<8 | dat[0])); + imu963ra_acc_y = (int16)(((uint16)dat[3]<<8 | dat[2])); + imu963ra_acc_z = (int16)(((uint16)dat[5]<<8 | dat[4])); +} + + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 获取IMU963RA陀螺仪数据 +// 参数说明 void +// 返回参数 void +// 使用示例 imu963ra_get_gyro(); +// 备注信息 执行该函数后，直接查看对应的变量即可 +//------------------------------------------------------------------------------------------------------------------- +void imu963ra_get_gyro (void) +{ + uint8 dat[6]; + + imu963ra_read_acc_gyro_registers(IMU963RA_OUTX_L_G, dat, 6); + imu963ra_gyro_x = (int16)(((uint16)dat[1]<<8 | dat[0])); + imu963ra_gyro_y = (int16)(((uint16)dat[3]<<8 | dat[2])); + imu963ra_gyro_z = (int16)(((uint16)dat[5]<<8 | dat[4])); +} + + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 获取 IMU963RA 磁力计数据 +// 参数说明 void +// 返回参数 void +// 使用示例 imu963ra_get_mag(); +// 备注信息 执行该函数后，直接查看对应的变量即可 +//------------------------------------------------------------------------------------------------------------------- +void imu963ra_get_mag (void) +{ + uint8 temp_status; + uint8 dat[6]; + + imu963ra_write_acc_gyro_register(IMU963RA_FUNC_CFG_ACCESS, 0x40); + temp_status = imu963ra_read_acc_gyro_register(IMU963RA_STATUS_MASTER); + if(0x01 & temp_status) + { + imu963ra_read_acc_gyro_registers(IMU963RA_SENSOR_HUB_1, dat, 6); + imu963ra_mag_x = (int16)(((uint16)dat[1] << 8 | dat[0])); + imu963ra_mag_y = (int16)(((uint16)dat[3] << 8 | dat[2])); + imu963ra_mag_z = (int16)(((uint16)dat[5] << 8 | dat[4])); + } + imu963ra_write_acc_gyro_register(IMU963RA_FUNC_CFG_ACCESS, 0x00); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 初始化 IMU963RA +// 参数说明 void +// 返回参数 uint8 1-初始化失败 0-初始化成功 +// 使用示例 imu963ra_init(); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +uint8 imu963ra_init (void) +{ + uint8 return_state = 0; + system_delay_ms(10); // 上电延时 + +#if IMU963RA_USE_SOFT_IIC + soft_iic_init(&imu963ra_iic_struct, IMU963RA_DEV_ADDR, IMU963RA_SOFT_IIC_DELAY, IMU963RA_SCL_PIN, IMU963RA_SDA_PIN); +#else + spi_init(IMU963RA_SPI, SPI_MODE0, IMU963RA_SPI_SPEED, IMU963RA_SPC_PIN, IMU963RA_SDI_PIN, IMU963RA_SDO_PIN, SPI_CS_NULL); + gpio_init(IMU963RA_CS_PIN, GPO, GPIO_LOW, GPO_PUSH_PULL); +#endif + + do + { + imu963ra_write_acc_gyro_register(IMU963RA_FUNC_CFG_ACCESS, 0x00); // 关闭HUB寄存器访问 + imu963ra_write_acc_gyro_register(IMU963RA_CTRL3_C, 0x01); // 复位设备 + system_delay_ms(2); + imu963ra_write_acc_gyro_register(IMU963RA_FUNC_CFG_ACCESS, 0x00); // 关闭HUB寄存器访问 + if(imu963ra_acc_gyro_self_check()) + { + zf_log(0, "IMU963RA acc and gyro self check error."); + return_state = 1; + break; + } + + imu963ra_write_acc_gyro_register(IMU963RA_INT1_CTRL, 0x03); // 开启陀螺仪 加速度数据就绪中断 + + // IMU963RA_CTRL1_XL 寄存器 + // 设置为 0x30 加速度量程为 ±2 G 获取到的加速度计数据除以 16393 可以转化为带物理单位的数据 单位 g(m/s^2) + // 设置为 0x38 加速度量程为 ±4 G 获取到的加速度计数据除以 8197 可以转化为带物理单位的数据 单位 g(m/s^2) + // 设置为 0x3C 加速度量程为 ±8 G 获取到的加速度计数据除以 4098 可以转化为带物理单位的数据 单位 g(m/s^2) + // 设置为 0x34 加速度量程为 ±16 G 获取到的加速度计数据除以 2049 可以转化为带物理单位的数据 单位 g(m/s^2) + switch(IMU963RA_ACC_SAMPLE_DEFAULT) + { + default: + { + zf_log(0, "IMU963RA_ACC_SAMPLE_DEFAULT set error."); + return_state = 1; + }break; + case IMU963RA_ACC_SAMPLE_SGN_2G: + { + imu963ra_write_acc_gyro_register(IMU963RA_CTRL1_XL, 0x30); + imu963ra_transition_factor[0] = 16393; + }break; + case IMU963RA_ACC_SAMPLE_SGN_4G: + { + imu963ra_write_acc_gyro_register(IMU963RA_CTRL1_XL, 0x38); + imu963ra_transition_factor[0] = 8197; + }break; + case IMU963RA_ACC_SAMPLE_SGN_8G: + { + imu963ra_write_acc_gyro_register(IMU963RA_CTRL1_XL, 0x3C); + imu963ra_transition_factor[0] = 4098; + }break; + case IMU963RA_ACC_SAMPLE_SGN_16G: + { + imu963ra_write_acc_gyro_register(IMU963RA_CTRL1_XL, 0x34); + imu963ra_transition_factor[0] = 2049; + }break; + } + if(1 == return_state) + { + break; + } + + // IMU963RA_CTRL2_G 寄存器 + // 设置为 0x52 陀螺仪量程为 ±125 dps 获取到的陀螺仪数据除以 228.6 可以转化为带物理单位的数据 单位为 °/s + // 设置为 0x50 陀螺仪量程为 ±250 dps 获取到的陀螺仪数据除以 114.3 可以转化为带物理单位的数据 单位为 °/s + // 设置为 0x54 陀螺仪量程为 ±500 dps 获取到的陀螺仪数据除以 57.1 可以转化为带物理单位的数据 单位为 °/s + // 设置为 0x58 陀螺仪量程为 ±1000 dps 获取到的陀螺仪数据除以 28.6 可以转化为带物理单位的数据 单位为 °/s + // 设置为 0x5C 陀螺仪量程为 ±2000 dps 获取到的陀螺仪数据除以 14.3 可以转化为带物理单位的数据 单位为 °/s + // 设置为 0x51 陀螺仪量程为 ±4000 dps 获取到的陀螺仪数据除以 7.1 可以转化为带物理单位的数据 单位为 °/s + switch(IMU963RA_GYRO_SAMPLE_DEFAULT) + { + default: + { + zf_log(0, "IMU963RA_GYRO_SAMPLE_DEFAULT set error."); + return_state = 1; + }break; + case IMU963RA_GYRO_SAMPLE_SGN_125DPS: + { + imu963ra_write_acc_gyro_register(IMU963RA_CTRL2_G, 0x52); + imu963ra_transition_factor[1] = 228.6; + }break; + case IMU963RA_GYRO_SAMPLE_SGN_250DPS: + { + imu963ra_write_acc_gyro_register(IMU963RA_CTRL2_G, 0x50); + imu963ra_transition_factor[1] = 114.3; + }break; + case IMU963RA_GYRO_SAMPLE_SGN_500DPS: + { + imu963ra_write_acc_gyro_register(IMU963RA_CTRL2_G, 0x54); + imu963ra_transition_factor[1] = 57.1; + }break; + case IMU963RA_GYRO_SAMPLE_SGN_1000DPS: + { + imu963ra_write_acc_gyro_register(IMU963RA_CTRL2_G, 0x58); + imu963ra_transition_factor[1] = 28.6; + }break; + case IMU963RA_GYRO_SAMPLE_SGN_2000DPS: + { + imu963ra_write_acc_gyro_register(IMU963RA_CTRL2_G, 0x5C); + imu963ra_transition_factor[1] = 14.3; + }break; + case IMU963RA_GYRO_SAMPLE_SGN_4000DPS: + { + imu963ra_write_acc_gyro_register(IMU963RA_CTRL2_G, 0x51); + imu963ra_transition_factor[1] = 7.1; + }break; + } + if(1 == return_state) + { + break; + } + + imu963ra_write_acc_gyro_register(IMU963RA_CTRL3_C, 0x44); // 使能陀螺仪数字低通滤波器 + imu963ra_write_acc_gyro_register(IMU963RA_CTRL4_C, 0x02); // 使能数字低通滤波器 + imu963ra_write_acc_gyro_register(IMU963RA_CTRL5_C, 0x00); // 加速度计与陀螺仪四舍五入 + imu963ra_write_acc_gyro_register(IMU963RA_CTRL6_C, 0x00); // 开启加速度计高性能模式 陀螺仪低通滤波 133hz + imu963ra_write_acc_gyro_register(IMU963RA_CTRL7_G, 0x00); // 开启陀螺仪高性能模式 关闭高通滤波 + imu963ra_write_acc_gyro_register(IMU963RA_CTRL9_XL, 0x01); // 关闭I3C接口 + + imu963ra_write_acc_gyro_register(IMU963RA_FUNC_CFG_ACCESS, 0x40); // 开启HUB寄存器访问 用于配置地磁计 + imu963ra_write_acc_gyro_register(IMU963RA_MASTER_CONFIG, 0x80); // 复位I2C主机 + system_delay_ms(2); + imu963ra_write_acc_gyro_register(IMU963RA_MASTER_CONFIG, 0x00); // 清除复位标志 + system_delay_ms(2); + + imu963ra_write_mag_register(IMU963RA_MAG_ADDR, IMU963RA_MAG_CONTROL2, 0x80);// 复位连接的外设 + system_delay_ms(2); + imu963ra_write_mag_register(IMU963RA_MAG_ADDR, IMU963RA_MAG_CONTROL2, 0x00); + system_delay_ms(2); + + if(imu963ra_mag_self_check()) + { + zf_log(0, "IMU963RA mag self check error."); + return_state = 1; + break; + } + + // IMU963RA_MAG_ADDR 寄存器 + // 设置为 0x09 磁力计量程为 2G 获取到的磁力计数据除以 12000 可以转化为带物理单位的数据 单位 G(高斯) + // 设置为 0x19 磁力计量程为 8G 获取到的磁力计数据除以 3000 可以转化为带物理单位的数据 单位 G(高斯) + switch(IMU963RA_MAG_SAMPLE_DEFAULT) + { + default: + { + zf_log(0, "IMU963RA_MAG_SAMPLE_DEFAULT set error."); + return_state = 1; + }break; + case IMU963RA_MAG_SAMPLE_2G: + { + imu963ra_write_mag_register(IMU963RA_MAG_ADDR, IMU963RA_MAG_CONTROL1, 0x09); + imu963ra_transition_factor[2] = 12000; + }break; + case IMU963RA_MAG_SAMPLE_8G: + { + imu963ra_write_mag_register(IMU963RA_MAG_ADDR, IMU963RA_MAG_CONTROL1, 0x19); + imu963ra_transition_factor[2] = 3000; + }break; + } + if(1 == return_state) + { + break; + } + + imu963ra_write_mag_register(IMU963RA_MAG_ADDR, IMU963RA_MAG_FBR, 0x01); + imu963ra_connect_mag(IMU963RA_MAG_ADDR, IMU963RA_MAG_OUTX_L); + + imu963ra_write_acc_gyro_register(IMU963RA_FUNC_CFG_ACCESS, 0x00); // 关闭HUB寄存器访问 + + system_delay_ms(20); // 等待磁力计获取数据 + }while(0); + return return_state; +} diff --git a/libraries/zf_device/zf_device_imu963ra.h b/libraries/zf_device/zf_device_imu963ra.h new file mode 100644 index 0000000..2608b9f --- /dev/null +++ b/libraries/zf_device/zf_device_imu963ra.h @@ -0,0 +1,279 @@ +/*/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_imu963ra +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* // 硬件 SPI 引脚 +* SCL/SPC 查看 zf_device_imu963ra.h 中 IMU963RA_SPC_PIN 宏定义 +* SDA/DSI 查看 zf_device_imu963ra.h 中 IMU963RA_SDI_PIN 宏定义 +* SA0/SDO 查看 zf_device_imu963ra.h 中 IMU963RA_SDO_PIN 宏定义 +* CS 查看 zf_device_imu963ra.h 中 IMU963RA_CS_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* 其余引脚悬空 + +* // 软件 IIC 引脚 +* SCL/SPC 查看 zf_device_imu963ra.h 中 IMU963RA_SCL_PIN 宏定义 +* SDA/DSI 查看 zf_device_imu963ra.h 中 IMU963RA_SDA_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* 其余引脚悬空 +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_imu963ra_h +#define _zf_device_imu963ra_h + +#include "zf_common_typedef.h" + +#define IMU963RA_USE_SOFT_IIC (0) // 默认使用硬件 SPI 方式驱动 +#if IMU963RA_USE_SOFT_IIC // 这两段 颜色正常的才是正确的 颜色灰的就是没有用的 +//====================================================软件 IIC 驱动==================================================== +#define IMU963RA_SOFT_IIC_DELAY (10 ) // 软件 IIC 的时钟延时周期 数值越小 IIC 通信速率越快 +#define IMU963RA_SCL_PIN (B3) // 软件 IIC SCL 引脚 连接 IMU963RA 的 SCL 引脚 +#define IMU963RA_SDA_PIN (B5) // 软件 IIC SDA 引脚 连接 IMU963RA 的 SDA 引脚 +//====================================================软件 IIC 驱动==================================================== +#else +//====================================================硬件 SPI 驱动==================================================== +#define IMU963RA_SPI_SPEED (10*1000*1000 ) // 硬件 SPI 速率 +#define IMU963RA_SPI (SPI_3 ) // 硬件 SPI 号 +#define IMU963RA_SPC_PIN (SPI3_MAP0_SCK_B3 ) // 硬件 SPI SCK 引脚 +#define IMU963RA_SDI_PIN (SPI3_MAP0_MOSI_B5) // 硬件 SPI MOSI 引脚 +#define IMU963RA_SDO_PIN (SPI3_MAP0_MISO_B4) // 硬件 SPI MISO 引脚 +//====================================================硬件 SPI 驱动==================================================== +#endif +#define IMU963RA_CS_PIN (C10) // CS 片选引脚 +#define IMU963RA_CS(x) (x? (gpio_high(IMU963RA_CS_PIN)): (gpio_low(IMU963RA_CS_PIN))) + +typedef enum +{ + IMU963RA_ACC_SAMPLE_SGN_2G , // 加速度计量程 ±2G (ACC = Accelerometer 加速度计) (SGN = signum 带符号数 表示正负范围) (G = g 重力加速度 g≈9.80 m/s^2) + IMU963RA_ACC_SAMPLE_SGN_4G , // 加速度计量程 ±4G (ACC = Accelerometer 加速度计) (SGN = signum 带符号数 表示正负范围) (G = g 重力加速度 g≈9.80 m/s^2) + IMU963RA_ACC_SAMPLE_SGN_8G , // 加速度计量程 ±8G (ACC = Accelerometer 加速度计) (SGN = signum 带符号数 表示正负范围) (G = g 重力加速度 g≈9.80 m/s^2) + IMU963RA_ACC_SAMPLE_SGN_16G, // 加速度计量程 ±16G (ACC = Accelerometer 加速度计) (SGN = signum 带符号数 表示正负范围) (G = g 重力加速度 g≈9.80 m/s^2) +}imu963ra_acc_sample_config; + +typedef enum +{ + IMU963RA_GYRO_SAMPLE_SGN_125DPS , // 陀螺仪量程 ±125DPS (GYRO = Gyroscope 陀螺仪) (SGN = signum 带符号数 表示正负范围) (DPS = Degree Per Second 角速度单位 °/S) + IMU963RA_GYRO_SAMPLE_SGN_250DPS , // 陀螺仪量程 ±250DPS (GYRO = Gyroscope 陀螺仪) (SGN = signum 带符号数 表示正负范围) (DPS = Degree Per Second 角速度单位 °/S) + IMU963RA_GYRO_SAMPLE_SGN_500DPS , // 陀螺仪量程 ±500DPS (GYRO = Gyroscope 陀螺仪) (SGN = signum 带符号数 表示正负范围) (DPS = Degree Per Second 角速度单位 °/S) + IMU963RA_GYRO_SAMPLE_SGN_1000DPS, // 陀螺仪量程 ±1000DPS (GYRO = Gyroscope 陀螺仪) (SGN = signum 带符号数 表示正负范围) (DPS = Degree Per Second 角速度单位 °/S) + IMU963RA_GYRO_SAMPLE_SGN_2000DPS, // 陀螺仪量程 ±2000DPS (GYRO = Gyroscope 陀螺仪) (SGN = signum 带符号数 表示正负范围) (DPS = Degree Per Second 角速度单位 °/S) + IMU963RA_GYRO_SAMPLE_SGN_4000DPS, // 陀螺仪量程 ±4000DPS (GYRO = Gyroscope 陀螺仪) (SGN = signum 带符号数 表示正负范围) (DPS = Degree Per Second 角速度单位 °/S) +}imu963ra_gyro_sample_config; + +typedef enum +{ + IMU963RA_MAG_SAMPLE_2G, // 磁力计量程 2G (MAG = Magnetometer 陀螺仪) (G = Gs 高斯) + IMU963RA_MAG_SAMPLE_8G, // 磁力计量程 8G (MAG = Magnetometer 陀螺仪) (G = Gs 高斯) +}imu963ra_mag_sample_config; + +#define IMU963RA_ACC_SAMPLE_DEFAULT ( IMU963RA_ACC_SAMPLE_SGN_8G ) // 在这设置默认的 加速度计 初始化量程 +#define IMU963RA_GYRO_SAMPLE_DEFAULT ( IMU963RA_GYRO_SAMPLE_SGN_2000DPS ) // 在这设置默认的 陀螺仪 初始化量程 +#define IMU963RA_MAG_SAMPLE_DEFAULT ( IMU963RA_MAG_SAMPLE_8G ) // 在这设置默认的 磁力计 初始化量程 + +#define IMU963RA_TIMEOUT_COUNT ( 0x00FF ) // IMU963RA 超时计数 + +//================================================定义 IMU963RA 内部地址================================================ +#define IMU963RA_DEV_ADDR ( 0x6B ) // SA0接地：0x6A SA0上拉：0x6B 模块默认上拉 +#define IMU963RA_SPI_W ( 0x00 ) +#define IMU963RA_SPI_R ( 0x80 ) + +#define IMU963RA_FUNC_CFG_ACCESS ( 0x01 ) +#define IMU963RA_PIN_CTRL ( 0x02 ) +#define IMU963RA_S4S_TPH_L ( 0x04 ) +#define IMU963RA_S4S_TPH_H ( 0x05 ) +#define IMU963RA_S4S_RR ( 0x06 ) +#define IMU963RA_FIFO_CTRL1 ( 0x07 ) +#define IMU963RA_FIFO_CTRL2 ( 0x08 ) +#define IMU963RA_FIFO_CTRL3 ( 0x09 ) +#define IMU963RA_FIFO_CTRL4 ( 0x0A ) +#define IMU963RA_COUNTER_BDR_REG1 ( 0x0B ) +#define IMU963RA_COUNTER_BDR_REG2 ( 0x0C ) +#define IMU963RA_INT1_CTRL ( 0x0D ) +#define IMU963RA_INT2_CTRL ( 0x0E ) +#define IMU963RA_WHO_AM_I ( 0x0F ) +#define IMU963RA_CTRL1_XL ( 0x10 ) +#define IMU963RA_CTRL2_G ( 0x11 ) +#define IMU963RA_CTRL3_C ( 0x12 ) +#define IMU963RA_CTRL4_C ( 0x13 ) +#define IMU963RA_CTRL5_C ( 0x14 ) +#define IMU963RA_CTRL6_C ( 0x15 ) +#define IMU963RA_CTRL7_G ( 0x16 ) +#define IMU963RA_CTRL8_XL ( 0x17 ) +#define IMU963RA_CTRL9_XL ( 0x18 ) +#define IMU963RA_CTRL10_C ( 0x19 ) +#define IMU963RA_ALL_INT_SRC ( 0x1A ) +#define IMU963RA_WAKE_UP_SRC ( 0x1B ) +#define IMU963RA_TAP_SRC ( 0x1C ) +#define IMU963RA_D6D_SRC ( 0x1D ) +#define IMU963RA_STATUS_REG ( 0x1E ) +#define IMU963RA_OUT_TEMP_L ( 0x20 ) +#define IMU963RA_OUT_TEMP_H ( 0x21 ) +#define IMU963RA_OUTX_L_G ( 0x22 ) +#define IMU963RA_OUTX_H_G ( 0x23 ) +#define IMU963RA_OUTY_L_G ( 0x24 ) +#define IMU963RA_OUTY_H_G ( 0x25 ) +#define IMU963RA_OUTZ_L_G ( 0x26 ) +#define IMU963RA_OUTZ_H_G ( 0x27 ) +#define IMU963RA_OUTX_L_A ( 0x28 ) +#define IMU963RA_OUTX_H_A ( 0x29 ) +#define IMU963RA_OUTY_L_A ( 0x2A ) +#define IMU963RA_OUTY_H_A ( 0x2B ) +#define IMU963RA_OUTZ_L_A ( 0x2C ) +#define IMU963RA_OUTZ_H_A ( 0x2D ) +#define IMU963RA_EMB_FUNC_STATUS_MAINPAGE ( 0x35 ) +#define IMU963RA_FSM_STATUS_A_MAINPAGE ( 0x36 ) +#define IMU963RA_FSM_STATUS_B_MAINPAGE ( 0x37 ) +#define IMU963RA_STATUS_MASTER_MAINPAGE ( 0x39 ) +#define IMU963RA_FIFO_STATUS1 ( 0x3A ) +#define IMU963RA_FIFO_STATUS2 ( 0x3B ) +#define IMU963RA_TIMESTAMP0 ( 0x40 ) +#define IMU963RA_TIMESTAMP1 ( 0x41 ) +#define IMU963RA_TIMESTAMP2 ( 0x42 ) +#define IMU963RA_TIMESTAMP3 ( 0x43 ) +#define IMU963RA_TAP_CFG0 ( 0x56 ) +#define IMU963RA_TAP_CFG1 ( 0x57 ) +#define IMU963RA_TAP_CFG2 ( 0x58 ) +#define IMU963RA_TAP_THS_6D ( 0x59 ) +#define IMU963RA_INT_DUR2 ( 0x5A ) +#define IMU963RA_WAKE_UP_THS ( 0x5B ) +#define IMU963RA_WAKE_UP_DUR ( 0x5C ) +#define IMU963RA_FREE_FALL ( 0x5D ) +#define IMU963RA_MD1_CFG ( 0x5E ) +#define IMU963RA_MD2_CFG ( 0x5F ) +#define IMU963RA_S4S_ST_CMD_CODE ( 0x60 ) +#define IMU963RA_S4S_DT_REG ( 0x61 ) +#define IMU963RA_I3C_BUS_AVB ( 0x62 ) +#define IMU963RA_INTERNAL_FREQ_FINE ( 0x63 ) +#define IMU963RA_INT_OIS ( 0x6F ) +#define IMU963RA_CTRL1_OIS ( 0x70 ) +#define IMU963RA_CTRL2_OIS ( 0x71 ) +#define IMU963RA_CTRL3_OIS ( 0x72 ) +#define IMU963RA_X_OFS_USR ( 0x73 ) +#define IMU963RA_Y_OFS_USR ( 0x74 ) +#define IMU963RA_Z_OFS_USR ( 0x75 ) +#define IMU963RA_FIFO_DATA_OUT_TAG ( 0x78 ) +#define IMU963RA_FIFO_DATA_OUT_X_L ( 0x79 ) +#define IMU963RA_FIFO_DATA_OUT_X_H ( 0x7A ) +#define IMU963RA_FIFO_DATA_OUT_Y_L ( 0x7B ) +#define IMU963RA_FIFO_DATA_OUT_Y_H ( 0x7C ) +#define IMU963RA_FIFO_DATA_OUT_Z_L ( 0x7D ) +#define IMU963RA_FIFO_DATA_OUT_Z_H ( 0x7E ) + +// 集线器功能相关寄存器 需要将FUNC_CFG_ACCESS的SHUB_REG_ACCESS位设置为1才能正确访问 +#define IMU963RA_SENSOR_HUB_1 ( 0x02 ) +#define IMU963RA_SENSOR_HUB_2 ( 0x03 ) +#define IMU963RA_SENSOR_HUB_3 ( 0x04 ) +#define IMU963RA_SENSOR_HUB_4 ( 0x05 ) +#define IMU963RA_SENSOR_HUB_5 ( 0x06 ) +#define IMU963RA_SENSOR_HUB_6 ( 0x07 ) +#define IMU963RA_SENSOR_HUB_7 ( 0x08 ) +#define IMU963RA_SENSOR_HUB_8 ( 0x09 ) +#define IMU963RA_SENSOR_HUB_9 ( 0x0A ) +#define IMU963RA_SENSOR_HUB_10 ( 0x0B ) +#define IMU963RA_SENSOR_HUB_11 ( 0x0C ) +#define IMU963RA_SENSOR_HUB_12 ( 0x0D ) +#define IMU963RA_SENSOR_HUB_13 ( 0x0E ) +#define IMU963RA_SENSOR_HUB_14 ( 0x0F ) +#define IMU963RA_SENSOR_HUB_15 ( 0x10 ) +#define IMU963RA_SENSOR_HUB_16 ( 0x11 ) +#define IMU963RA_SENSOR_HUB_17 ( 0x12 ) +#define IMU963RA_SENSOR_HUB_18 ( 0x13 ) +#define IMU963RA_MASTER_CONFIG ( 0x14 ) +#define IMU963RA_SLV0_ADD ( 0x15 ) +#define IMU963RA_SLV0_SUBADD ( 0x16 ) +#define IMU963RA_SLV0_CONFIG ( 0x17 ) +#define IMU963RA_SLV1_ADD ( 0x18 ) +#define IMU963RA_SLV1_SUBADD ( 0x19 ) +#define IMU963RA_SLV1_CONFIG ( 0x1A ) +#define IMU963RA_SLV2_ADD ( 0x1B ) +#define IMU963RA_SLV2_SUBADD ( 0x1C ) +#define IMU963RA_SLV2_CONFIG ( 0x1D ) +#define IMU963RA_SLV3_ADD ( 0x1E ) +#define IMU963RA_SLV3_SUBADD ( 0x1F ) +#define IMU963RA_SLV3_CONFIG ( 0x20 ) +#define IMU963RA_DATAWRITE_SLV0 ( 0x21 ) +#define IMU963RA_STATUS_MASTER ( 0x22 ) + +#define IMU963RA_MAG_ADDR ( 0x0D ) // 7位IIC地址 +#define IMU963RA_MAG_OUTX_L ( 0x00 ) +#define IMU963RA_MAG_CONTROL1 ( 0x09 ) +#define IMU963RA_MAG_CONTROL2 ( 0x0A ) +#define IMU963RA_MAG_FBR ( 0x0B ) +#define IMU963RA_MAG_CHIP_ID ( 0x0D ) +//================================================定义 IMU963RA 内部地址================================================ + +extern int16 imu963ra_acc_x, imu963ra_acc_y, imu963ra_acc_z; +extern int16 imu963ra_gyro_x, imu963ra_gyro_y, imu963ra_gyro_z; +extern int16 imu963ra_mag_x, imu963ra_mag_y, imu963ra_mag_z; +extern float imu963ra_transition_factor[3]; + +void imu963ra_get_acc (void); +void imu963ra_get_gyro (void); +void imu963ra_get_mag (void); + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 将 IMU963RA 加速度计数据转换为实际物理数据 +// 参数说明 acc_value 任意轴的加速度计数据 +// 返回参数 void +// 使用示例 float data = imu963ra_acc_transition(imu963ra_acc_x); // 单位为 g(m/s^2) +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +#define imu963ra_acc_transition(acc_value) ((float)(acc_value) / imu963ra_transition_factor[0]) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 将 IMU963RA 陀螺仪数据转换为实际物理数据 +// 参数说明 gyro_value 任意轴的陀螺仪数据 +// 返回参数 void +// 使用示例 float data = imu963ra_gyro_transition(imu963ra_gyro_x); // 单位为 °/s +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +#define imu963ra_gyro_transition(gyro_value) ((float)(gyro_value) / imu963ra_transition_factor[1]) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 将 IMU963RA 磁力计数据转换为实际物理数据 +// 参数说明 mag_value 任意轴的磁力计数据 +// 返回参数 void +// 使用示例 float data = imu963ra_mag_transition(imu963ra_mag_x); // 单位为 G +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +#define imu963ra_mag_transition(mag_value) ((float)(mag_value) / imu963ra_transition_factor[2]) + +uint8 imu963ra_init (void); + +#endif diff --git a/libraries/zf_device/zf_device_ips114.c b/libraries/zf_device/zf_device_ips114.c new file mode 100644 index 0000000..3219601 --- /dev/null +++ b/libraries/zf_device/zf_device_ips114.c @@ -0,0 +1,1076 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_ips114 +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* SCL 查看 zf_device_ips114.h 中 IPS114_SCL_PIN 宏定义 +* SDA 查看 zf_device_ips114.h 中 IPS114_SDA_PIN 宏定义 +* RST 查看 zf_device_ips114.h 中 IPS114_RST_PIN 宏定义 +* DC 查看 zf_device_ips114.h 中 IPS114_DC_PIN 宏定义 +* CS 查看 zf_device_ips114.h 中 IPS114_CS_PIN 宏定义 +* BLK 查看 zf_device_ips114.h 中 IPS114_BLK_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* 最大分辨率 135 * 240 +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_common_font.h" +#include "zf_common_function.h" +#include "zf_driver_delay.h" +#include "zf_driver_soft_spi.h" +#include "zf_driver_spi.h" + +#include "zf_device_ips114.h" + +static uint16 ips114_pencolor = IPS114_DEFAULT_PENCOLOR; +static uint16 ips114_bgcolor = IPS114_DEFAULT_BGCOLOR; + +static ips114_dir_enum ips114_display_dir = IPS114_DEFAULT_DISPLAY_DIR; +static ips114_font_size_enum ips114_display_font = IPS114_DEFAULT_DISPLAY_FONT; + +static uint8 ips114_x_max = 240; +static uint8 ips114_y_max = 135; + +#if IPS114_USE_SOFT_SPI +static soft_spi_info_struct ips114_spi; +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 SPI 写 8bit 数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 ips114_write_8bit_data(dat); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips114_write_8bit_data(data) (soft_spi_write_8bit(&ips114_spi, (data))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 SPI 写 8bit 数据数组 +// 参数说明 *data 数据 +// 参数说明 len 数据长度 +// 返回参数 void +// 使用示例 ips114_write_8bit_data_array(data, len); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips114_write_8bit_data_array(data, len) (soft_spi_write_8bit(&ips114_spi, (data), (len))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 SPI 写 16bit 数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 ips114_write_16bit_data(x1 + 52); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips114_write_16bit_data(data) (soft_spi_write_16bit(&ips114_spi, (data))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 SPI 写 16bit 数据数组 +// 参数说明 *data 数据 +// 参数说明 len 数据长度 +// 返回参数 void +// 使用示例 ips114_write_16bit_data_array(data, len); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips114_write_16bit_data_array(data, len) (soft_spi_write_16bit_array(&ips114_spi, (data), (len))) +#else +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 SPI 写 8bit 数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 ips114_write_8bit_data(dat); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips114_write_8bit_data(data) (spi_write_8bit(IPS114_SPI, (data))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 SPI 写 8bit 数据数组 +// 参数说明 *data 数据 +// 参数说明 len 数据长度 +// 返回参数 void +// 使用示例 ips114_write_8bit_data_array(data, len); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips114_write_8bit_data_array(data, len) (spi_write_8bit_array(IPS114_SPI, (data), (len))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 SPI 写 16bit 数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 ips114_write_16bit_data(x1 + 52); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips114_write_16bit_data(data) (spi_write_16bit(IPS114_SPI, (data))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 SPI 写 16bit 数据数组 +// 参数说明 *data 数据 +// 参数说明 len 数据长度 +// 返回参数 void +// 使用示例 ips114_write_16bit_data_array(data, len); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips114_write_16bit_data_array(data, len) (spi_write_16bit_array(IPS114_SPI, (data), (len))) +#endif + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 写命令 +// 参数说明 dat 数据 +// 返回参数 void +// 使用示例 ips114_write_index(0x2a); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static void ips114_write_index (const uint8 dat) +{ + IPS114_DC(0); + ips114_write_8bit_data(dat); + IPS114_DC(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示区域 +// 参数说明 x1 起始x轴坐标 +// 参数说明 y1 起始y轴坐标 +// 参数说明 x2 结束x轴坐标 +// 参数说明 y2 结束y轴坐标 +// 返回参数 void +// 使用示例 ips114_set_region(0, 0, ips114_x_max - 1, ips114_y_max - 1); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static void ips114_set_region (const uint16 x1, const uint16 y1, const uint16 x2, const uint16 y2) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + // 检查一下你的显示调用的函数 自己计算一下哪里超过了屏幕显示范围 + zf_assert(x1 < ips114_x_max); + zf_assert(y1 < ips114_y_max); + zf_assert(x2 < ips114_x_max); + zf_assert(y2 < ips114_y_max); + + switch(ips114_display_dir) + { + case IPS114_PORTAIT: + { + ips114_write_index(0x2a); // 列地址设置 + ips114_write_16bit_data(x1 + 40); + ips114_write_16bit_data(x2 + 40); + ips114_write_index(0x2b); // 行地址设置 + ips114_write_16bit_data(y1 + 52); + ips114_write_16bit_data(y2 + 52); + ips114_write_index(0x2c); // 储存器写 + }break; + case IPS114_PORTAIT_180: + { + ips114_write_index(0x2a); // 列地址设置 + ips114_write_16bit_data(x1 + 40); + ips114_write_16bit_data(x2 + 40); + ips114_write_index(0x2b); // 行地址设置 + ips114_write_16bit_data(y1 + 53); + ips114_write_16bit_data(y2 + 53); + ips114_write_index(0x2c); // 储存器写 + }break; + case IPS114_CROSSWISE: + { + ips114_write_index(0x2a); // 列地址设置 + ips114_write_16bit_data(x1 + 52); + ips114_write_16bit_data(x2 + 52); + ips114_write_index(0x2b); // 行地址设置 + ips114_write_16bit_data(y1 + 40); + ips114_write_16bit_data(y2 + 40); + ips114_write_index(0x2c); // 储存器写 + }break; + case IPS114_CROSSWISE_180: + { + ips114_write_index(0x2a); // 列地址设置 + ips114_write_16bit_data(x1 + 53); + ips114_write_16bit_data(x2 + 53); + ips114_write_index(0x2b); // 行地址设置 + ips114_write_16bit_data(y1 + 40); + ips114_write_16bit_data(y2 + 40); + ips114_write_index(0x2c); // 储存器写 + }break; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 1.14寸 IPS 液晶显示DEBUG信息初始化 +// 参数说明 void +// 返回参数 void +// 使用示例 ips114_debug_init(); +// 备注信息 内部使用 +//------------------------------------------------------------------------------------------------------------------- +static void ips114_debug_init (void) +{ + debug_output_struct info; + debug_output_struct_init(&info); + + info.type_index = 1; + info.display_x_max = ips114_x_max; + info.display_y_max = ips114_y_max; + + switch(ips114_display_font) + { + case IPS114_6X8_FONT: + { + info.font_x_size = 6; + info.font_y_size = 8; + }break; + case IPS114_8X16_FONT: + { + info.font_x_size = 8; + info.font_y_size = 16; + }break; + case IPS114_16X16_FONT: + { + // 暂不支持 + }break; + } + info.output_screen = ips114_show_string; + info.output_screen_clear = ips114_clear; + + debug_output_init(&info); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 清屏函数 +// 参数说明 void +// 返回参数 void +// 使用示例 ips114_clear(); +// 备注信息 将屏幕清空成背景颜色 +//------------------------------------------------------------------------------------------------------------------- +void ips114_clear (void) +{ + uint16 color_buffer[ips114_x_max]; + uint32 i = 0, j = 0; + + IPS114_CS(0); + ips114_set_region(0, 0, ips114_x_max - 1, ips114_y_max - 1); + for(i = 0; i < ips114_x_max; i ++) + { + color_buffer[i] = ips114_bgcolor; + } + for (j = 0; j < ips114_y_max; j ++) + { + ips114_write_16bit_data_array(color_buffer, ips114_x_max); + } + IPS114_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 屏幕填充函数 +// 参数说明 color 颜色格式 RGB565 或者可以使用 zf_common_font.h 内 rgb565_color_enum 枚举值或者自行写入 +// 返回参数 void +// 使用示例 ips114_full(RGB565_BLACK); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips114_full (const uint16 color) +{ + uint16 color_buffer[ips114_x_max]; + uint32 i = 0, j = 0; + + IPS114_CS(0); + ips114_set_region(0, 0, ips114_x_max - 1, ips114_y_max - 1); + for(i = 0; i < ips114_x_max; i ++) + { + color_buffer[i] = color; + } + for (j = 0; j < ips114_y_max; j ++) + { + ips114_write_16bit_data_array(color_buffer, ips114_x_max); + } + IPS114_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示方向 +// 参数说明 dir 显示方向 参照 zf_device_ips114.h 内 ips114_dir_enum 枚举体定义 +// 返回参数 void +// 使用示例 ips114_set_dir(IPS114_CROSSWISE); +// 备注信息 这个函数只有在初始化屏幕之前调用才生效 +//------------------------------------------------------------------------------------------------------------------- +void ips114_set_dir (ips114_dir_enum dir) +{ + ips114_display_dir = dir; + switch(ips114_display_dir) + { + case IPS114_PORTAIT: + case IPS114_PORTAIT_180: + { + ips114_x_max = 240; + ips114_y_max = 135; + }break; + case IPS114_CROSSWISE: + case IPS114_CROSSWISE_180: + { + ips114_x_max = 135; + ips114_y_max = 240; + }break; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示字体 +// 参数说明 dir 显示方向 参照 zf_device_ips114.h 内 ips114_font_size_enum 枚举体定义 +// 返回参数 void +// 使用示例 ips114_set_font(IPS114_8x16_FONT); +// 备注信息 字体可以随时自由设置 设置后生效 后续显示就是新的字体大小 +//------------------------------------------------------------------------------------------------------------------- +void ips114_set_font (ips114_font_size_enum font) +{ + ips114_display_font = font; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示颜色 +// 参数说明 pen 颜色格式 RGB565 或者可以使用 zf_common_font.h 内 rgb565_color_enum 枚举值或者自行写入 +// 参数说明 bgcolor 颜色格式 RGB565 或者可以使用 zf_common_font.h 内 rgb565_color_enum 枚举值或者自行写入 +// 返回参数 void +// 使用示例 ips114_set_color(RGB565_WHITE, RGB565_BLACK); +// 备注信息 字体颜色和背景颜色也可以随时自由设置 设置后生效 +//------------------------------------------------------------------------------------------------------------------- +void ips114_set_color (const uint16 pen, const uint16 bgcolor) +{ + ips114_pencolor = pen; + ips114_bgcolor = bgcolor; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 画点 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips114_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips114_y_max-1] +// 参数说明 color 颜色格式 RGB565 或者可以使用 zf_common_font.h 内 rgb565_color_enum 枚举值或者自行写入 +// 返回参数 void +// 使用示例 ips114_draw_point(0, 0, RGB565_RED); // 坐标 0,0 画一个红色的点 +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips114_draw_point (uint16 x, uint16 y, const uint16 color) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips114_x_max); + zf_assert(y < ips114_y_max); + + IPS114_CS(0); + ips114_set_region(x, y, x, y); + ips114_write_16bit_data(color); + IPS114_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 画线 +// 参数说明 x_start 坐标x方向的起点 +// 参数说明 y_start 坐标y方向的起点 +// 参数说明 x_end 坐标x方向的终点 +// 参数说明 y_end 坐标y方向的终点 +// 参数说明 color 颜色格式 RGB565 或者可以使用 zf_common_font.h 内 rgb565_color_enum 枚举值或者自行写入 +// 返回参数 void +// 使用示例 ips114_draw_line(0, 0, 10, 10, RGB565_RED); // 坐标 0,0 到 10,10 画一条红色的线 +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips114_draw_line (uint16 x_start, uint16 y_start, uint16 x_end, uint16 y_end, const uint16 color) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x_start < ips114_x_max); + zf_assert(y_start < ips114_y_max); + zf_assert(x_end < ips114_x_max); + zf_assert(y_end < ips114_y_max); + + int16 x_dir = (x_start < x_end ? 1 : -1); + int16 y_dir = (y_start < y_end ? 1 : -1); + float temp_rate = 0; + float temp_b = 0; + + do + { + if(x_start != x_end) + { + temp_rate = (float)(y_start - y_end) / (float)(x_start - x_end); + temp_b = (float)y_start - (float)x_start * temp_rate; + } + else + { + while(y_start != y_end) + { + ips114_draw_point(x_start, y_start, color); + y_start += y_dir; + } + ips114_draw_point(x_start, y_start, color); + break; + } + if(func_abs(y_start - y_end) > func_abs(x_start - x_end)) + { + while(y_start != y_end) + { + ips114_draw_point(x_start, y_start, color); + y_start += y_dir; + x_start = (int16)(((float)y_start - temp_b) / temp_rate); + } + ips114_draw_point(x_start, y_start, color); + } + else + { + while(x_start != x_end) + { + ips114_draw_point(x_start, y_start, color); + x_start += x_dir; + y_start = (int16)((float)x_start * temp_rate + temp_b); + } + ips114_draw_point(x_start, y_start, color); + } + }while(0); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 显示字符 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips114_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips114_y_max-1] +// 参数说明 dat 需要显示的字符 +// 返回参数 void +// 使用示例 ips114_show_char(0, 0, 'x'); // 坐标 0,0 写一个字符 x +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips114_show_char (uint16 x, uint16 y, const char dat) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips114_x_max); + zf_assert(y < ips114_y_max); + + uint8 i = 0, j = 0; + + IPS114_CS(0); + switch(ips114_display_font) + { + case IPS114_6X8_FONT: + { + uint16 display_buffer[6*8]; + ips114_set_region(x, y, x + 5, y + 7); + for(i = 0; 6 > i; i ++) + { + // 减 32 因为是取模是从空格开始取得 空格在 ascii 中序号是 32 + uint8 temp_top = ascii_font_6x8[dat - 32][i]; + for(j = 0; 8 > j; j ++) + { + if(temp_top & 0x01) + { + display_buffer[i + j * 6] = (ips114_pencolor); + } + else + { + display_buffer[i + j * 6] = (ips114_bgcolor); + } + temp_top >>= 1; + } + } + ips114_write_16bit_data_array(display_buffer, 6*8); + }break; + case IPS114_8X16_FONT: + { + uint16 display_buffer[8*16]; + ips114_set_region(x, y, x + 7, y + 15); + for(i = 0; 8 > i; i ++) + { + uint8 temp_top = ascii_font_8x16[dat - 32][i]; + uint8 temp_bottom = ascii_font_8x16[dat - 32][i + 8]; + for(j = 0; 8 > j; j ++) + { + if(temp_top & 0x01) + { + display_buffer[i + j * 8] = (ips114_pencolor); + } + else + { + display_buffer[i + j * 8] = (ips114_bgcolor); + } + temp_top >>= 1; + } + for(j = 0; 8 > j; j ++) + { + if(temp_bottom & 0x01) + { + display_buffer[i + j * 8 + 4 * 16] = (ips114_pencolor); + } + else + { + display_buffer[i + j * 8 + 4 * 16] = (ips114_bgcolor); + } + temp_bottom >>= 1; + } + } + ips114_write_16bit_data_array(display_buffer, 8 * 16); + }break; + case IPS114_16X16_FONT: + { + // 暂不支持 + }break; + } + IPS114_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 显示字符串 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips114_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips114_y_max-1] +// 参数说明 dat 需要显示的字符串 +// 返回参数 void +// 使用示例 ips114_show_string(0, 0, "seekfree"); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips114_show_string (uint16 x, uint16 y, const char dat[]) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips114_x_max); + zf_assert(y < ips114_y_max); + + uint16 j = 0; + while('\0' != dat[j]) + { + switch(ips114_display_font) + { + case IPS114_6X8_FONT: ips114_show_char(x + 6 * j, y, dat[j]); break; + case IPS114_8X16_FONT: ips114_show_char(x + 8 * j, y, dat[j]); break; + case IPS114_16X16_FONT: break; // 暂不支持 + } + j ++; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 显示32位有符号 (去除整数部分无效的0) +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips114_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips114_y_max-1] +// 参数说明 dat 需要显示的变量 数据类型 int32 +// 参数说明 num 需要显示的位数 最高10位 不包含正负号 +// 返回参数 void +// 使用示例 ips114_show_int(0, 0, x, 3); // x 可以为 int32 int16 int8 类型 +// 备注信息 负数会显示一个 ‘-’号 +//------------------------------------------------------------------------------------------------------------------- +void ips114_show_int (uint16 x, uint16 y, const int32 dat, uint8 num) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips114_x_max); + zf_assert(y < ips114_y_max); + zf_assert(0 < num); + zf_assert(10 >= num); + + int32 dat_temp = dat; + int32 offset = 1; + char data_buffer[12]; + + memset(data_buffer, 0, 12); + memset(data_buffer, ' ', num + 1); + + // 用来计算余数显示 123 显示 2 位则应该显示 23 + if(10 > num) + { + for(; 0 < num; num --) + { + offset *= 10; + } + dat_temp %= offset; + } + func_int_to_str(data_buffer, dat_temp); + ips114_show_string(x, y, (const char *)&data_buffer); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 显示32位无符号 (去除整数部分无效的0) +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips114_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips114_y_max-1] +// 参数说明 dat 需要显示的变量 数据类型 uint32 +// 参数说明 num 需要显示的位数 最高10位 不包含正负号 +// 返回参数 void +// 使用示例 ips114_show_uint(0, 0, x, 3); // x 可以为 uint32 uint16 uint8 类型 +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips114_show_uint (uint16 x, uint16 y, const uint32 dat, uint8 num) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips114_x_max); + zf_assert(y < ips114_y_max); + zf_assert(0 < num); + zf_assert(10 >= num); + + uint32 dat_temp = dat; + int32 offset = 1; + char data_buffer[12]; + memset(data_buffer, 0, 12); + memset(data_buffer, ' ', num); + + // 用来计算余数显示 123 显示 2 位则应该显示 23 + if(10 > num) + { + for(; 0 < num; num --) + { + offset *= 10; + } + dat_temp %= offset; + } + func_uint_to_str(data_buffer, dat_temp); + ips114_show_string(x, y, (const char *)&data_buffer); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 显示浮点数 (去除整数部分无效的0) +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips114_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips114_y_max-1] +// 参数说明 dat 需要显示的变量 数据类型 double +// 参数说明 num 整数位显示长度 最高8位 +// 参数说明 pointnum 小数位显示长度 最高6位 +// 返回参数 void +// 使用示例 ips114_show_float(0, 0, x, 2, 3); // 显示浮点数 整数显示 2 位 小数显示 3 位 +// 备注信息 特别注意当发现小数部分显示的值与你写入的值不一样的时候， +// 可能是由于浮点数精度丢失问题导致的，这并不是显示函数的问题， +// 有关问题的详情，请自行百度学习 浮点数精度丢失问题。 +// 负数会显示一个 ‘-’号 +//------------------------------------------------------------------------------------------------------------------- +void ips114_show_float (uint16 x, uint16 y, const double dat, uint8 num, uint8 pointnum) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips114_x_max); + zf_assert(y < ips114_y_max); + zf_assert(0 < num); + zf_assert(8 >= num); + zf_assert(0 < pointnum); + zf_assert(6 >= pointnum); + + double dat_temp = dat; + double offset = 1.0; + char data_buffer[17]; + memset(data_buffer, 0, 17); + memset(data_buffer, ' ', num + pointnum + 2); + + // 用来计算余数显示 123 显示 2 位则应该显示 23 + for(; 0 < num; num --) + { + offset *= 10; + } + dat_temp = dat_temp - ((int)dat_temp / (int)offset) * offset; + func_double_to_str(data_buffer, dat_temp, pointnum); + ips114_show_string(x, y, data_buffer); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 显示二值图像 数据每八个点组成一个字节数据 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips114_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips114_y_max-1] +// 参数说明 *image 图像数组指针 +// 参数说明 width 图像实际宽度 +// 参数说明 height 图像实际高度 +// 参数说明 dis_width 图像显示宽度 参数范围 [0, ips114_x_max] +// 参数说明 dis_height 图像显示高度 参数范围 [0, ips114_y_max] +// 返回参数 void +// 使用示例 ips114_show_binary_image(0, 0, ov7725_image_binary[0], OV7725_W, OV7725_H, OV7725_W, OV7725_H); +// 备注信息 用于显示小钻风的未解压的压缩二值化图像 +// 这个函数不可以用来直接显示总钻风的未压缩的二值化图像 +// 这个函数不可以用来直接显示总钻风的未压缩的二值化图像 +// 这个函数不可以用来直接显示总钻风的未压缩的二值化图像 +//------------------------------------------------------------------------------------------------------------------- +void ips114_show_binary_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips114_x_max); + zf_assert(y < ips114_y_max); + zf_assert(NULL != image); + + uint32 i = 0, j = 0; + uint8 temp = 0; + uint32 width_index = 0; + uint16 data_buffer[dis_width]; + const uint8 *image_temp; + + IPS114_CS(0); + ips114_set_region(x, y, x + dis_width - 1, y + dis_height - 1); // 设置显示区域 + + for(j = 0; j < dis_height; j ++) + { + image_temp = image + j * height / dis_height * width / 8; // 直接对 image 操作会 Hardfault 暂时不知道为什么 + for(i = 0; i < dis_width; i ++) + { + width_index = i * width / dis_width; + temp = *(image_temp + width_index / 8); // 读取像素点 + if(0x80 & (temp << (width_index % 8))) + { + data_buffer[i] = (RGB565_WHITE); + } + else + { + data_buffer[i] = (RGB565_BLACK); + } + } + ips114_write_16bit_data_array(data_buffer, dis_width); + } + IPS114_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 显示 8bit 灰度图像 带二值化阈值 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips114_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips114_y_max-1] +// 参数说明 *image 图像数组指针 +// 参数说明 width 图像实际宽度 +// 参数说明 height 图像实际高度 +// 参数说明 dis_width 图像显示宽度 参数范围 [0, ips114_x_max] +// 参数说明 dis_height 图像显示高度 参数范围 [0, ips114_y_max] +// 参数说明 threshold 二值化显示阈值 0-不开启二值化 +// 返回参数 void +// 使用示例 ips114_show_gray_image(0, 0, mt9v03x_image[0], MT9V03X_W, MT9V03X_H, MT9V03X_W, MT9V03X_H, 0); +// 备注信息 用于显示总钻风的图像 +// 如果要显示二值化图像 直接修改最后一个参数为需要的二值化阈值即可 +// 如果要显示二值化图像 直接修改最后一个参数为需要的二值化阈值即可 +// 如果要显示二值化图像 直接修改最后一个参数为需要的二值化阈值即可 +//------------------------------------------------------------------------------------------------------------------- +void ips114_show_gray_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 threshold) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips114_x_max); + zf_assert(y < ips114_y_max); + zf_assert(NULL != image); + + uint32 i = 0, j = 0; + uint16 color = 0,temp = 0; + uint16 data_buffer[dis_width]; + const uint8 *image_temp; + + IPS114_CS(0); + ips114_set_region(x, y, x + dis_width - 1, y + dis_height - 1); // 设置显示区域 + + for(j = 0; j < dis_height; j ++) + { + image_temp = image + j * height / dis_height * width; // 直接对 image 操作会 Hardfault 暂时不知道为什么 + for(i = 0; i < dis_width; i ++) + { + temp = *(image_temp + i * width / dis_width); // 读取像素点 + if(threshold == 0) + { + color = (0x001f & ((temp) >> 3)) << 11; + color = color | (((0x003f) & ((temp) >> 2)) << 5); + color = color | (0x001f & ((temp) >> 3)); + data_buffer[i] = (color); + } + else if(temp < threshold) + { + data_buffer[i] = (RGB565_BLACK); + } + else + { + data_buffer[i] = (RGB565_WHITE); + } + } + ips114_write_16bit_data_array(data_buffer, dis_width); + } + IPS114_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 显示 RGB565 彩色图像 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips114_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips114_y_max-1] +// 参数说明 *image 图像数组指针 +// 参数说明 width 图像实际宽度 +// 参数说明 height 图像实际高度 +// 参数说明 dis_width 图像显示宽度 参数范围 [0, ips114_x_max] +// 参数说明 dis_height 图像显示高度 参数范围 [0, ips114_y_max] +// 参数说明 color_mode 色彩模式 0-低位在前 1-高位在前 +// 返回参数 void +// 使用示例 ips114_show_rgb565_image(0, 0, scc8660_image[0], SCC8660_W, SCC8660_H, SCC8660_W, SCC8660_H, 1); +// 备注信息 用于显示凌瞳的 RGB565 的图像 +// 如果要显示低位在前的其他 RGB565 图像 修改最后一个参数即可 +// 如果要显示低位在前的其他 RGB565 图像 修改最后一个参数即可 +// 如果要显示低位在前的其他 RGB565 图像 修改最后一个参数即可 +//------------------------------------------------------------------------------------------------------------------- +void ips114_show_rgb565_image (uint16 x, uint16 y, const uint16 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 color_mode) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips114_x_max); + zf_assert(y < ips114_y_max); + zf_assert(NULL != image); + + uint32 i = 0, j = 0; + uint16 data_buffer[dis_width]; + const uint16 *image_temp; + + IPS114_CS(0); + ips114_set_region(x, y, x + dis_width - 1, y + dis_height - 1); // 设置显示区域 + + for(j = 0; j < dis_height; j ++) + { + image_temp = image + j * height / dis_height * width; // 直接对 image 操作会 Hardfault 暂时不知道为什么 + for(i = 0; i < dis_width; i ++) + { + data_buffer[i] = *(image_temp + i * width / dis_width); // 读取像素点 + } + if(color_mode) + { + ips114_write_8bit_data_array((uint8 *)data_buffer, dis_width * 2); + } + else + { + ips114_write_16bit_data_array(data_buffer, dis_width); + } + } + IPS114_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 显示波形 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips114_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips114_y_max-1] +// 参数说明 *wave 波形数组指针 +// 参数说明 width 波形实际宽度 +// 参数说明 value_max 波形实际最大值 +// 参数说明 dis_width 波形显示宽度 参数范围 [0, ips114_x_max] +// 参数说明 dis_value_max 波形显示最大值 参数范围 [0, ips114_y_max] +// 返回参数 void +// 使用示例 ips114_show_wave(56,35,data,128,64,128,64); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips114_show_wave (uint16 x, uint16 y, const uint16 *wave, uint16 width, uint16 value_max, uint16 dis_width, uint16 dis_value_max) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips114_x_max); + zf_assert(y < ips114_y_max); + zf_assert(NULL != wave); + + uint32 i = 0, j = 0; + uint32 width_index = 0, value_max_index = 0; + uint16 data_buffer[dis_width]; + + + IPS114_CS(0); + ips114_set_region(x, y, x + dis_width - 1, y + dis_value_max - 1); // 设置显示区域 + for(j = 0; j < dis_value_max; j ++) + { + for(i = 0; i < dis_width; i ++) + { + data_buffer[i] = (ips114_bgcolor); + } + ips114_write_16bit_data_array(data_buffer, dis_width); + } + IPS114_CS(1); + + for(i = 0; i < dis_width; i ++) + { + width_index = i * width / dis_width; + value_max_index = *(wave + width_index) * (dis_value_max - 1) / value_max; + ips114_draw_point(i + x, (dis_value_max - 1) - value_max_index + y, ips114_pencolor); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 汉字显示 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips114_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips114_y_max-1] +// 参数说明 size 取模的时候设置的汉字字体大小 也就是一个汉字占用的点阵长宽为多少个点 取模的时候需要长宽是一样的 +// 参数说明 *chinese_buffer 需要显示的汉字数组 +// 参数说明 number 需要显示多少位 +// 参数说明 color 颜色格式 RGB565 或者可以使用 zf_common_font.h 内 rgb565_color_enum 枚举值或者自行写入 +// 返回参数 void +// 使用示例 ips114_show_chinese(0, 0, 16, chinese_test[0], 4, RGB565_RED);// 显示font文件里面的 示例 +// 备注信息 使用PCtoLCD2002软件取模 阴码、逐行式、顺向 16*16 +//------------------------------------------------------------------------------------------------------------------- +void ips114_show_chinese (uint16 x, uint16 y, uint8 size, const uint8 *chinese_buffer, uint8 number, const uint16 color) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips114_x_max); + zf_assert(y < ips114_y_max); + zf_assert(NULL != chinese_buffer); + + int i = 0, j = 0, k = 0; + uint8 temp = 0, temp1 = 0, temp2 = 0; + const uint8 *p_data = chinese_buffer; + + temp2 = size / 8; + + IPS114_CS(0); + ips114_set_region(x, y, number * size - 1 + x, y + size - 1); + + for(i = 0; i < size; i ++) + { + temp1 = number; + p_data = chinese_buffer + i * temp2; + while(temp1 --) + { + for(k = 0; k < temp2; k ++) + { + for(j = 8; 0 < j; j --) + { + temp = (*p_data >> (j - 1)) & 0x01; + if(temp) + { + ips114_write_16bit_data(color); + } + else + { + ips114_write_16bit_data(ips114_bgcolor); + } + } + p_data ++; + } + p_data = p_data - temp2 + temp2 * size; + } + } + IPS114_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 1.14寸 IPS液晶初始化 +// 参数说明 void +// 返回参数 void +// 使用示例 ips114_init(); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips114_init (void) +{ +#if IPS114_USE_SOFT_SPI + soft_spi_init(&ips114_spi, 0, IPS114_SOFT_SPI_DELAY, IPS114_SCL_PIN, IPS114_SDA_PIN, SOFT_SPI_PIN_NULL, SOFT_SPI_PIN_NULL); +#else + spi_init(IPS114_SPI, SPI_MODE0, IPS114_SPI_SPEED, IPS114_SCL_PIN, IPS114_SDA_PIN, SPI_MISO_NULL, SPI_CS_NULL); +#endif + + gpio_init(IPS114_DC_PIN, GPO, GPIO_LOW, GPO_PUSH_PULL); + gpio_init(IPS114_RST_PIN, GPO, GPIO_LOW, GPO_PUSH_PULL); + gpio_init(IPS114_CS_PIN, GPO, GPIO_HIGH, GPO_PUSH_PULL); + gpio_init(IPS114_BLK_PIN, GPO, GPIO_HIGH, GPO_PUSH_PULL); + + ips114_set_dir(ips114_display_dir); + ips114_set_color(ips114_pencolor, ips114_bgcolor); + + IPS114_RST(0); + system_delay_ms(200); + + IPS114_RST(1); + system_delay_ms(100); + + IPS114_CS(0); + ips114_write_index(0x36); + system_delay_ms(100); + switch(ips114_display_dir) + { + case IPS114_PORTAIT: ips114_write_8bit_data(0xA0); break; + case IPS114_PORTAIT_180: ips114_write_8bit_data(0x70); break; + case IPS114_CROSSWISE: ips114_write_8bit_data(0x00); break; + case IPS114_CROSSWISE_180: ips114_write_8bit_data(0xC0); break; + } + + ips114_write_index(0x3A); + ips114_write_8bit_data(0x05); + + ips114_write_index(0xB2); + ips114_write_8bit_data(0x0C); + ips114_write_8bit_data(0x0C); + ips114_write_8bit_data(0x00); + ips114_write_8bit_data(0x33); + ips114_write_8bit_data(0x33); + + ips114_write_index(0xB7); + ips114_write_8bit_data(0x35); + + ips114_write_index(0xBB); + ips114_write_8bit_data(0x37); + + ips114_write_index(0xC0); + ips114_write_8bit_data(0x2C); + + ips114_write_index(0xC2); + ips114_write_8bit_data(0x01); + + ips114_write_index(0xC3); + ips114_write_8bit_data(0x12); + + ips114_write_index(0xC4); + ips114_write_8bit_data(0x20); + + ips114_write_index(0xC6); + ips114_write_8bit_data(0x0F); + + ips114_write_index(0xD0); + ips114_write_8bit_data(0xA4); + ips114_write_8bit_data(0xA1); + + ips114_write_index(0xE0); + ips114_write_8bit_data(0xD0); + ips114_write_8bit_data(0x04); + ips114_write_8bit_data(0x0D); + ips114_write_8bit_data(0x11); + ips114_write_8bit_data(0x13); + ips114_write_8bit_data(0x2B); + ips114_write_8bit_data(0x3F); + ips114_write_8bit_data(0x54); + ips114_write_8bit_data(0x4C); + ips114_write_8bit_data(0x18); + ips114_write_8bit_data(0x0D); + ips114_write_8bit_data(0x0B); + ips114_write_8bit_data(0x1F); + ips114_write_8bit_data(0x23); + + ips114_write_index(0xE1); + ips114_write_8bit_data(0xD0); + ips114_write_8bit_data(0x04); + ips114_write_8bit_data(0x0C); + ips114_write_8bit_data(0x11); + ips114_write_8bit_data(0x13); + ips114_write_8bit_data(0x2C); + ips114_write_8bit_data(0x3F); + ips114_write_8bit_data(0x44); + ips114_write_8bit_data(0x51); + ips114_write_8bit_data(0x2F); + ips114_write_8bit_data(0x1F); + ips114_write_8bit_data(0x1F); + ips114_write_8bit_data(0x20); + ips114_write_8bit_data(0x23); + + ips114_write_index(0x21); + + ips114_write_index(0x11); + system_delay_ms(120); + + ips114_write_index(0x29); + IPS114_CS(1); + + ips114_clear(); + ips114_debug_init(); +} diff --git a/libraries/zf_device/zf_device_ips114.h b/libraries/zf_device/zf_device_ips114.h new file mode 100644 index 0000000..0bb1379 --- /dev/null +++ b/libraries/zf_device/zf_device_ips114.h @@ -0,0 +1,165 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_ips114 +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* SCL 查看 zf_device_ips114.h 中 IPS114_SCL_PIN 宏定义 +* SDA 查看 zf_device_ips114.h 中 IPS114_SDA_PIN 宏定义 +* RST 查看 zf_device_ips114.h 中 IPS114_RST_PIN 宏定义 +* DC 查看 zf_device_ips114.h 中 IPS114_DC_PIN 宏定义 +* CS 查看 zf_device_ips114.h 中 IPS114_CS_PIN 宏定义 +* BLK 查看 zf_device_ips114.h 中 IPS114_BLK_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* 最大分辨率 135 * 240 +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_ips114_h_ +#define _zf_device_ips114_h_ + +#include "zf_common_typedef.h" + +#define IPS114_USE_SOFT_SPI (0) // 默认使用硬件 SPI 方式驱动 建议使用硬件 SPI 方式驱动 +#if IPS114_USE_SOFT_SPI // 这两段 颜色正常的才是正确的 颜色灰的就是没有用的 +//====================================================软件 SPI 驱动==================================================== +#define IPS114_SOFT_SPI_DELAY (1 ) // 软件 SPI 的时钟延时周期 数值越小 SPI 通信速率越快 +#define IPS114_SCL_PIN (D4) // 软件 SPI SCK 引脚 +#define IPS114_SDA_PIN (D6) // 软件 SPI MOSI 引脚 +//====================================================软件 SPI 驱动==================================================== +#else +//====================================================硬件 SPI 驱动==================================================== +#define IPS114_SPI_SPEED (72 * 1000 * 1000) // 硬件 SPI 速率 这里设置为系统时钟二分频 +#define IPS114_SPI (SPI_2) // 硬件 SPI 号 +#define IPS114_SCL_PIN (SPI2_MAP0_SCK_B13) // 硬件 SPI SCK 引脚 +#define IPS114_SDA_PIN (SPI2_MAP0_MOSI_B15) // 硬件 SPI MOSI 引脚 +//====================================================硬件 SPI 驱动==================================================== +#endif + +//#define IPS114_RST_PIN (B7 ) // 液晶复位引脚定义 +//#define IPS114_DC_PIN (D7 ) // 液晶命令位引脚定义 +//#define IPS114_CS_PIN (D4 ) // CS 片选引脚 +//#define IPS114_BLK_PIN (D0 ) // 液晶背光引脚定义 + +#define IPS114_RST_PIN (D8 ) // 液晶复位引脚定义 +#define IPS114_DC_PIN (D9 ) // 液晶命令位引脚定义 +#define IPS114_CS_PIN (D10 ) // CS 片选引脚 +#define IPS114_BLK_PIN (D11 ) // 液晶背光引脚定义 + + +#define IPS114_DEFAULT_DISPLAY_DIR (IPS114_PORTAIT) // 默认的显示方向 +#define IPS114_DEFAULT_PENCOLOR (RGB565_RED) // 默认的画笔颜色 +#define IPS114_DEFAULT_BGCOLOR (RGB565_WHITE) // 默认的背景颜色 +#define IPS114_DEFAULT_DISPLAY_FONT (IPS114_8X16_FONT) // 默认的字体模式 + +#define IPS114_DC(x) ((x) ? (gpio_high(IPS114_DC_PIN)) : (gpio_low(IPS114_DC_PIN))) +#define IPS114_RST(x) ((x) ? (gpio_high(IPS114_RST_PIN)) : (gpio_low(IPS114_RST_PIN))) +#define IPS114_CS(x) ((x) ? (gpio_high(IPS114_CS_PIN)) : (gpio_low(IPS114_CS_PIN))) +#define IPS114_BLK(x) ((x) ? (gpio_high(IPS114_BLK_PIN)) : (gpio_low(IPS114_BLK_PIN))) + +typedef enum +{ + IPS114_PORTAIT = 0, // 竖屏模式 + IPS114_PORTAIT_180 = 1, // 竖屏模式 旋转180 + IPS114_CROSSWISE = 2, // 横屏模式 + IPS114_CROSSWISE_180 = 3, // 横屏模式 旋转180 +}ips114_dir_enum; + +typedef enum +{ + IPS114_6X8_FONT = 0, // 6x8 字体 + IPS114_8X16_FONT = 1, // 8x16 字体 + IPS114_16X16_FONT = 2, // 16x16 字体 目前不支持 +}ips114_font_size_enum; + +void ips114_clear (void); +void ips114_full (const uint16 color); +void ips114_set_dir (ips114_dir_enum dir); +void ips114_set_font (ips114_font_size_enum font); +void ips114_set_color (const uint16 pen, const uint16 bgcolor); +void ips114_draw_point (uint16 x, uint16 y, const uint16 color); +void ips114_draw_line (uint16 x_start, uint16 y_start, uint16 x_end, uint16 y_end, const uint16 color); + +void ips114_show_char (uint16 x, uint16 y, const char dat); +void ips114_show_string (uint16 x, uint16 y, const char dat[]); +void ips114_show_int (uint16 x,uint16 y, const int32 dat, uint8 num); +void ips114_show_uint (uint16 x,uint16 y, const uint32 dat, uint8 num); +void ips114_show_float (uint16 x,uint16 y, const double dat, uint8 num, uint8 pointnum); + +void ips114_show_binary_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height); +void ips114_show_gray_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 threshold); +void ips114_show_rgb565_image (uint16 x, uint16 y, const uint16 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 color_mode); + +void ips114_show_wave (uint16 x, uint16 y, const uint16 *wave, uint16 width, uint16 value_max, uint16 dis_width, uint16 dis_value_max); +void ips114_show_chinese (uint16 x, uint16 y, uint8 size, const uint8 *chinese_buffer, uint8 number, const uint16 color); + + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 显示小钻风图像 +// 参数说明 p 图像数组 +// 参数说明 width 显示宽度 +// 参数说明 height 显示高度 +// 返回参数 void +// 使用示例 ips114_displayimage7725(ov7725_image_binary[0], 80, 60); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +#define ips114_displayimage7725(p, width, height) (ips114_show_binary_image(0, 0, (p), OV7725_W, OV7725_H, (width), (height))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 显示总钻风图像 不带二值化 显示灰度图像 +// 参数说明 p 图像数组 +// 参数说明 width 显示宽度 +// 参数说明 height 显示高度 +// 返回参数 void +// 使用示例 ips114_displayimage03x(mt9v03x_image[0], 94, 60); +// 备注信息 如果要显示二值化图像就去调用 ips114_show_gray_image 函数 +//------------------------------------------------------------------------------------------------------------------- +#define ips114_displayimage03x(p, width, height) (ips114_show_gray_image(0, 0, (p), MT9V03X_W, MT9V03X_H, (width), (height), 0)) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 显示凌瞳图像 +// 参数说明 p 图像数组 +// 参数说明 width 显示宽度 +// 参数说明 height 显示高度 +// 返回参数 void +// 使用示例 ips114_displayimage8660(scc8660_image[0], 80, 60); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +#define ips114_displayimage8660(p, width, height) (ips114_show_rgb565_image(0, 0, (p), SCC8660_W, SCC8660_H, (width), (height), 1)) + +void ips114_init (void); + +#endif diff --git a/libraries/zf_device/zf_device_ips200.c b/libraries/zf_device/zf_device_ips200.c new file mode 100644 index 0000000..8f0a342 --- /dev/null +++ b/libraries/zf_device/zf_device_ips200.c @@ -0,0 +1,1296 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_ips200 +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* // 双排排针 并口两寸屏 硬件引脚 +* RD 查看 zf_device_ips200.h 中 IPS200_RD_PIN_PARALLEL8 宏定义 +* WR 查看 zf_device_ips200.h 中 IPS200_WR_PIN_PARALLEL8 宏定义 +* RS 查看 zf_device_ips200.h 中 IPS200_RS_PIN_PARALLEL8 宏定义 +* RST 查看 zf_device_ips200.h 中 IPS200_RST_PIN_PARALLEL8 宏定义 +* CS 查看 zf_device_ips200.h 中 IPS200_CS_PIN_PARALLEL8 宏定义 +* BL 查看 zf_device_ips200.h 中 IPS200_BL_PIN_PARALLEL8 宏定义 +* D0-D7 查看 zf_device_ips200.h 中 IPS200_Dx_PIN_PARALLEL8 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* +* // 单排排针 SPI 两寸屏 硬件引脚 +* SCL 查看 zf_device_ips200.h 中 IPS200_SCL_PIN_SPI 宏定义 +* SDA 查看 zf_device_ips200.h 中 IPS200_SDA_PIN_SPI 宏定义 +* RST 查看 zf_device_ips200.h 中 IPS200_RST_PIN_SPI 宏定义 +* DC 查看 zf_device_ips200.h 中 IPS200_DC_PIN_SPI 宏定义 +* CS 查看 zf_device_ips200.h 中 IPS200_CS_PIN_SPI 宏定义 +* BLk 查看 zf_device_ips200.h 中 IPS200_BLk_PIN_SPI 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* 最大分辨率 320 * 240 +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_common_font.h" +#include "zf_common_function.h" +#include "zf_driver_delay.h" +#include "zf_driver_gpio.h" +#include "zf_driver_spi.h" +#include "zf_driver_soft_spi.h" + +#include "zf_device_ips200.h" + +static uint16 ips200_pencolor = IPS200_DEFAULT_PENCOLOR; +static uint16 ips200_bgcolor = IPS200_DEFAULT_BGCOLOR; + +static ips200_type_enum ips200_display_type = IPS200_TYPE_SPI; +static ips200_dir_enum ips200_display_dir = IPS200_DEFAULT_DISPLAY_DIR; +static ips200_font_size_enum ips200_display_font = IPS200_DEFAULT_DISPLAY_FONT; + +static uint16 ips200_x_max = 240; +static uint16 ips200_y_max = 320; + +static gpio_pin_enum ips_rst_pin = IPS200_RST_PIN_SPI; +static gpio_pin_enum ips_bl_pin = IPS200_BLk_PIN_SPI; +static gpio_pin_enum ips_cs_pin = IPS200_CS_PIN_SPI; + +#if IPS200_USE_SOFT_SPI +static soft_spi_info_struct ips200_spi; +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 SPI 写 8bit 数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 ips200_write_8bit_data_spi(command); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips200_write_8bit_data_spi(data) (soft_spi_write_8bit(&ips200_spi, (data))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 SPI 写 8bit 数据数组 +// 参数说明 *data 数据 +// 参数说明 len 数据长度 +// 返回参数 void +// 使用示例 ips200_write_8bit_data_spi_array(data, len); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips200_write_8bit_data_spi_array(data, len) (soft_spi_write_8bit_array(&ips200_spi, (data), (len))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 SPI 写 16bit 数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 ips200_write_16bit_data_spi(dat); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips200_write_16bit_data_spi(data) (soft_spi_write_16bit(&ips200_spi, (data))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 SPI 写 16bit 数据数组 +// 参数说明 *data 数据 +// 参数说明 len 数据长度 +// 返回参数 void +// 使用示例 ips200_write_16bit_data_spi_array(data, len); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips200_write_16bit_data_spi_array(data, len) (soft_spi_write_16bit_array(&ips200_spi, (data), (len))) +#else +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 SPI 写 8bit 数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 ips200_write_8bit_data_spi(command); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips200_write_8bit_data_spi(data) (spi_write_8bit(IPS200_SPI, (data))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 SPI 写 8bit 数据数组 +// 参数说明 *data 数据 +// 参数说明 len 数据长度 +// 返回参数 void +// 使用示例 ips200_write_8bit_data_spi_array(data, len); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips200_write_8bit_data_spi_array(data, len) (spi_write_8bit_array(IPS200_SPI, (data), (len))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 SPI 写 16bit 数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 ips200_write_16bit_data_spi(dat); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips200_write_16bit_data_spi(data) (spi_write_16bit(IPS200_SPI, (data))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 SPI 写 16bit 数据数组 +// 参数说明 *data 数据 +// 参数说明 len 数据长度 +// 返回参数 void +// 使用示例 ips200_write_16bit_data_spi_array(data, len); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define ips200_write_16bit_data_spi_array(data, len) (spi_write_16bit_array(IPS200_SPI, (data), (len))) +#endif + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 SPI 写数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 ips200_write_16bit_data_spi(dat); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static void ips200_write_data (const uint8 dat) +{ + IPS200_DATAPORT->OUTDR = ((dat<< DATA_START_NUM) | (IPS200_DATAPORT->OUTDR & ~((uint32)(0xFF << DATA_START_NUM)))); + +} + +//#define ips200_write_data(x) (*(volatile uint16 *)IPS200_DATA_ADD = (((uint16)x & 0x00FF) << 8)) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 写命令 +// 参数说明 command 命令 +// 返回参数 void +// 使用示例 ips200_write_command(0x2a); +// 备注信息 内部调用 用户无需关心 +//------------------------------------------------------------------------------------------------------------------- +static void ips200_write_command (const uint8 command) +{ + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(1); + IPS200_CS(0); + IPS200_DC(0); + ips200_write_8bit_data_spi(command); + IPS200_DC(1); + IPS200_CS(1); + IPS200_CS(0); + } + else + { + IPS200_CS(0); + IPS200_RS(0); + IPS200_RD(1); + IPS200_WR(0); + ips200_write_data(command); + IPS200_WR(1); + IPS200_CS(1); + IPS200_RS(1); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 向液晶屏写 8bit 数据 +// 参数说明 dat 数据 +// 返回参数 void +// 使用示例 ips200_write_8bit_data(0x0C); +// 备注信息 内部调用 用户无需关心 +//------------------------------------------------------------------------------------------------------------------- +static void ips200_write_8bit_data (const uint8 dat) +{ + if(IPS200_TYPE_SPI == ips200_display_type) + { + ips200_write_8bit_data_spi(dat); + } + else + { + IPS200_CS(0); + IPS200_RD(1); + IPS200_WR(0); + ips200_write_data(dat); + IPS200_WR(1); + IPS200_CS(1); + } +} +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 向液晶屏写 8bit 数组 +// 参数说明 dat 数据 +// 返回参数 void +// 使用示例 ips200_write_8bit_data(dat,1); +// 备注信息 内部调用 用户无需关心 +//------------------------------------------------------------------------------------------------------------------- +static void ips200_write_8bit_data_array (const uint8 *dat, uint32 len) +{ + if(IPS200_TYPE_SPI == ips200_display_type) + { + ips200_write_8bit_data_spi_array(dat, len); + } + else + { + IPS200_CS(0); + IPS200_RD(1); + while(len --) + { + IPS200_WR(0); + ips200_write_data((uint8)*dat); + IPS200_WR(1); + dat ++; + } + IPS200_CS(1); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 向液晶屏写 16bit 数据 +// 参数说明 dat 数据 +// 返回参数 void +// 使用示例 ips200_write_16bit_data(x1); +// 备注信息 内部调用 用户无需关心 +//------------------------------------------------------------------------------------------------------------------- +static void ips200_write_16bit_data (const uint16 dat) +{ + if(IPS200_TYPE_SPI == ips200_display_type) + { + ips200_write_16bit_data_spi(dat); + } + else + { + IPS200_CS(0); + IPS200_RD(1); + IPS200_WR(0); + ips200_write_data((uint8)(dat >> 8)); + IPS200_WR(1); + IPS200_WR(0); + ips200_write_data((uint8)(dat & 0xFF)); + IPS200_WR(1); + IPS200_CS(1); + } +} +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 向液晶屏写 16bit 数据 +// 参数说明 dat 数据 +// 返回参数 void +// 使用示例 ips200_write_16bit_data(x1); +// 备注信息 内部调用 用户无需关心 +//------------------------------------------------------------------------------------------------------------------- +static void ips200_write_16bit_data_array (const uint16 *dat, uint32 len) +{ + if(IPS200_TYPE_SPI == ips200_display_type) + { + ips200_write_16bit_data_spi_array(dat, len); + } + else + { + IPS200_CS(0); + IPS200_RD(1); + while(len --) + { + IPS200_WR(0); + ips200_write_data((uint8)(*dat >> 8)); + IPS200_WR(1); + IPS200_WR(0); + ips200_write_data((uint8)(*dat & 0xFF)); + IPS200_WR(1); + dat ++; + } + IPS200_CS(1); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示区域 +// 参数说明 x1 起始x轴坐标 +// 参数说明 y1 起始y轴坐标 +// 参数说明 x2 结束x轴坐标 +// 参数说明 y2 结束y轴坐标 +// 返回参数 void +// 使用示例 ips200_set_region(0, 0, ips200_x_max - 1, ips200_y_max - 1); +// 备注信息 内部调用 用户无需关心 +//------------------------------------------------------------------------------------------------------------------- +static void ips200_set_region (uint16 x1, uint16 y1, uint16 x2, uint16 y2) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + // 检查一下你的显示调用的函数 自己计算一下哪里超过了屏幕显示范围 + zf_assert(x1 < ips200_x_max); + zf_assert(y1 < ips200_y_max); + zf_assert(x2 < ips200_x_max); + zf_assert(y2 < ips200_y_max); + + ips200_write_command(0x2a); + ips200_write_16bit_data(x1); + ips200_write_16bit_data(x2); + + ips200_write_command(0x2b); + ips200_write_16bit_data(y1); + ips200_write_16bit_data(y2); + + ips200_write_command(0x2c); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 显示DEBUG信息初始化 +// 参数说明 void +// 返回参数 void +// 使用示例 ips200_debug_init(); +// 备注信息 内部使用 用户无需关心 +//------------------------------------------------------------------------------------------------------------------- +static void ips200_debug_init (void) +{ + debug_output_struct info; + debug_output_struct_init(&info); + + info.type_index = 1; + info.display_x_max = ips200_x_max; + info.display_y_max = ips200_y_max; + + switch(ips200_display_font) + { + case IPS200_6X8_FONT: + { + info.font_x_size = 6; + info.font_y_size = 8; + }break; + case IPS200_8X16_FONT: + { + info.font_x_size = 8; + info.font_y_size = 16; + }break; + case IPS200_16X16_FONT: + { + // 暂不支持 + }break; + } + info.output_screen = ips200_show_string; + info.output_screen_clear = ips200_clear; + + debug_output_init(&info); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 清屏函数 +// 参数说明 void +// 返回参数 void +// 使用示例 ips200_clear(); +// 备注信息 将屏幕清空成背景颜色 +//------------------------------------------------------------------------------------------------------------------- +void ips200_clear (void) +{ + uint16 color_buffer[ips200_x_max]; + uint16 i = 0, j = 0; + + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(0); + } + ips200_set_region(0, 0, ips200_x_max - 1, ips200_y_max - 1); + for(i = 0; i < ips200_x_max; i ++) + { + color_buffer[i] = ips200_bgcolor; + } + for (j = 0; j < ips200_y_max; j ++) + { + ips200_write_16bit_data_array(color_buffer, ips200_x_max); + } + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(1); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 屏幕填充函数 +// 参数说明 color 颜色格式 RGB565 或者可以使用 zf_common_font.h 内 rgb565_color_enum 枚举值或者自行写入 +// 返回参数 void +// 使用示例 ips200_full(RGB565_BLACK); +// 备注信息 将屏幕填充成指定颜色 +//------------------------------------------------------------------------------------------------------------------- +void ips200_full (const uint16 color) +{ + uint16 color_buffer[ips200_x_max]; + uint16 i = 0, j = 0; + + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(0); + } + ips200_set_region(0, 0, ips200_x_max - 1, ips200_y_max - 1); + for(i = 0; i < ips200_x_max; i ++) + { + color_buffer[i] = color; + } + for (j = 0; j < ips200_y_max; j ++) + { + ips200_write_16bit_data_array(color_buffer, ips200_x_max); + } + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(1); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示方向 +// 参数说明 dir 显示方向 参照 zf_device_ips200.h 内 ips200_dir_enum 枚举体定义 +// 返回参数 void +// 使用示例 ips200_set_dir(IPS200_PORTAIT); +// 备注信息 这个函数只有在初始化屏幕之前调用才生效 +//------------------------------------------------------------------------------------------------------------------- +void ips200_set_dir (ips200_dir_enum dir) +{ + ips200_display_dir = dir; + switch(ips200_display_dir) + { + case IPS200_PORTAIT: + case IPS200_PORTAIT_180: + { + ips200_x_max = 240; + ips200_y_max = 320; + }break; + case IPS200_CROSSWISE: + case IPS200_CROSSWISE_180: + { + ips200_x_max = 320; + ips200_y_max = 240; + }break; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示字体 +// 参数说明 dir 显示方向 参照 zf_device_ips200.h 内 ips200_font_size_enum 枚举体定义 +// 返回参数 void +// 使用示例 ips200_set_font(IPS200_8x16_FONT); +// 备注信息 字体可以随时自由设置 设置后生效 后续显示就是新的字体大小 +//------------------------------------------------------------------------------------------------------------------- +void ips200_set_font (ips200_font_size_enum font) +{ + ips200_display_font = font; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示颜色 +// 参数说明 pen 颜色格式 RGB565 或者可以使用 zf_common_font.h 内 rgb565_color_enum 枚举值或者自行写入 +// 参数说明 bgcolor 颜色格式 RGB565 或者可以使用 zf_common_font.h 内 rgb565_color_enum 枚举值或者自行写入 +// 返回参数 void +// 使用示例 ips200_set_color(RGB565_RED, RGB565_GRAY); +// 备注信息 字体颜色和背景颜色也可以随时自由设置 设置后生效 +//------------------------------------------------------------------------------------------------------------------- +void ips200_set_color (const uint16 pen, const uint16 bgcolor) +{ + ips200_pencolor = pen; + ips200_bgcolor = bgcolor; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 画点 +// 参数说明 x 坐标x方向的起点 [0, ips200_x_max-1] +// 参数说明 y 坐标y方向的起点 [0, ips200_y_max-1] +// 参数说明 color 颜色格式 RGB565 或者可以使用 zf_common_font.h 内 rgb565_color_enum 枚举值或者自行写入 +// 返回参数 void +// 使用示例 ips200_draw_point(0, 0, RGB565_RED); //坐标0,0画一个红色的点 +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips200_draw_point (uint16 x, uint16 y, const uint16 color) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips200_x_max); + zf_assert(y < ips200_y_max); + + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(0); + } + ips200_set_region(x, y, x, y); + ips200_write_16bit_data(color); + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(1); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 画线 +// 参数说明 x_start 坐标x方向的起点 [0, ips200_x_max-1] +// 参数说明 y_start 坐标y方向的起点 [0, ips200_y_max-1] +// 参数说明 x_end 坐标x方向的终点 [0, ips200_x_max-1] +// 参数说明 y_end 坐标y方向的终点 [0, ips200_y_max-1] +// 参数说明 color 颜色格式 RGB565 或者可以使用 zf_common_font.h 内 rgb565_color_enum 枚举值或者自行写入 +// 返回参数 void +// 使用示例 ips200_draw_line(0, 0, 10, 10, RGB565_RED); // 坐标 0,0 到 10,10 画一条红色的线 +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips200_draw_line (uint16 x_start, uint16 y_start, uint16 x_end, uint16 y_end, const uint16 color) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x_start < ips200_x_max); + zf_assert(y_start < ips200_y_max); + zf_assert(x_end < ips200_x_max); + zf_assert(y_end < ips200_y_max); + + int16 x_dir = (x_start < x_end ? 1 : -1); + int16 y_dir = (y_start < y_end ? 1 : -1); + float temp_rate = 0; + float temp_b = 0; + + do + { + if(x_start != x_end) + { + temp_rate = (float)(y_start - y_end) / (float)(x_start - x_end); + temp_b = (float)y_start - (float)x_start * temp_rate; + } + else + { + while(y_start != y_end) + { + ips200_draw_point(x_start, y_start, color); + y_start += y_dir; + } + ips200_draw_point(x_start, y_start, color); + break; + } + if(func_abs(y_start - y_end) > func_abs(x_start - x_end)) + { + while(y_start != y_end) + { + ips200_draw_point(x_start, y_start, color); + y_start += y_dir; + x_start = (int16)(((float)y_start - temp_b) / temp_rate); + } + ips200_draw_point(x_start, y_start, color); + } + else + { + while(x_start != x_end) + { + ips200_draw_point(x_start, y_start, color); + x_start += x_dir; + y_start = (int16)((float)x_start * temp_rate + temp_b); + } + ips200_draw_point(x_start, y_start, color); + } + }while(0); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 显示字符 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips200_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips200_y_max-1] +// 参数说明 dat 需要显示的字符 +// 返回参数 void +// 使用示例 ips200_show_char(0, 0, 'x'); // 坐标0,0写一个字符x +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips200_show_char (uint16 x, uint16 y, const char dat) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips200_x_max); + zf_assert(y < ips200_y_max); + + uint8 i = 0, j = 0; + + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(0); + } + switch(ips200_display_font) + { + case IPS200_6X8_FONT: + { + uint16 display_buffer[6*8]; + ips200_set_region(x, y, x + 5, y + 7); + for(i = 0; 6 > i; i ++) + { + // 减 32 因为是取模是从空格开始取得 空格在 ascii 中序号是 32 + uint8 temp_top = ascii_font_6x8[dat - 32][i]; + for(j = 0; 8 > j; j ++) + { + if(temp_top & 0x01) + { + display_buffer[i + j * 6] = (ips200_pencolor); + } + else + { + display_buffer[i + j * 6] = (ips200_bgcolor); + } + temp_top >>= 1; + } + } + ips200_write_16bit_data_array(display_buffer, 6*8); + }break; + case IPS200_8X16_FONT: + { + uint16 display_buffer[8*16]; + ips200_set_region(x, y, x + 7, y + 15); + for(i = 0; 8 > i; i ++) + { + uint8 temp_top = ascii_font_8x16[dat - 32][i]; + uint8 temp_bottom = ascii_font_8x16[dat - 32][i + 8]; + for(j = 0; 8 > j; j ++) + { + if(temp_top & 0x01) + { + display_buffer[i + j * 8] = (ips200_pencolor); + } + else + { + display_buffer[i + j * 8] = (ips200_bgcolor); + } + temp_top >>= 1; + } + for(j = 0; 8 > j; j ++) + { + if(temp_bottom & 0x01) + { + display_buffer[i + j * 8 + 4 * 16] = (ips200_pencolor); + } + else + { + display_buffer[i + j * 8 + 4 * 16] = (ips200_bgcolor); + } + temp_bottom >>= 1; + } + } + ips200_write_16bit_data_array(display_buffer, 8 * 16); + }break; + case IPS200_16X16_FONT: + { + // 暂不支持 + }break; + } + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(1); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 显示字符串 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips200_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips200_y_max-1] +// 参数说明 dat 需要显示的字符串 +// 返回参数 void +// 使用示例 ips200_show_string(0, 0, "seekfree"); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips200_show_string (uint16 x, uint16 y, const char dat[]) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips200_x_max); + zf_assert(y < ips200_y_max); + + uint16 j = 0; + while('\0' != dat[j]) + { + switch(ips200_display_font) + { + case IPS200_6X8_FONT: ips200_show_char(x + 6 * j, y, dat[j]); break; + case IPS200_8X16_FONT: ips200_show_char(x + 8 * j, y, dat[j]); break; + case IPS200_16X16_FONT: break; // 暂不支持 + } + j ++; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 显示32位有符号 (去除整数部分无效的0) +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips200_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips200_y_max-1] +// 参数说明 dat 需要显示的变量 数据类型 int32 +// 参数说明 num 需要显示的位数 最高10位 不包含正负号 +// 返回参数 void +// 使用示例 ips200_show_int(0, 0, x, 3); // x 可以为 int32 int16 int8 类型 +// 备注信息 负数会显示一个 ‘-’号 +//------------------------------------------------------------------------------------------------------------------- +void ips200_show_int (uint16 x, uint16 y, const int32 dat, uint8 num) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips200_x_max); + zf_assert(y < ips200_y_max); + zf_assert(0 < num); + zf_assert(10 >= num); + + int32 dat_temp = dat; + int32 offset = 1; + char data_buffer[12]; + + memset(data_buffer, 0, 12); + memset(data_buffer, ' ', num+1); + + // 用来计算余数显示 123 显示 2 位则应该显示 23 + if(10 > num) + { + for(; 0 < num; num --) + { + offset *= 10; + } + dat_temp %= offset; + } + func_int_to_str(data_buffer, dat_temp); + ips200_show_string(x, y, (const char *)&data_buffer); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 显示32位无符号 (去除整数部分无效的0) +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips114_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips114_y_max-1] +// 参数说明 dat 需要显示的变量 数据类型 uint32 +// 参数说明 num 需要显示的位数 最高10位 不包含正负号 +// 返回参数 void +// 使用示例 ips200_show_uint(0, 0, x, 3); // x 可以为 uint32 uint16 uint8 类型 +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips200_show_uint (uint16 x, uint16 y, const uint32 dat, uint8 num) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips200_x_max); + zf_assert(y < ips200_y_max); + zf_assert(0 < num); + zf_assert(10 >= num); + + uint32 dat_temp = dat; + int32 offset = 1; + char data_buffer[12]; + memset(data_buffer, 0, 12); + memset(data_buffer, ' ', num); + + // 用来计算余数显示 123 显示 2 位则应该显示 23 + if(10 > num) + { + for(; 0 < num; num --) + { + offset *= 10; + } + dat_temp %= offset; + } + func_uint_to_str(data_buffer, dat_temp); + ips200_show_string(x, y, (const char *)&data_buffer); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 显示浮点数(去除整数部分无效的0) +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips200_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips200_y_max-1] +// 参数说明 dat 需要显示的变量 数据类型 double +// 参数说明 num 整数位显示长度 最高8位 +// 参数说明 pointnum 小数位显示长度 最高6位 +// 返回参数 void +// 使用示例 ips200_show_float(0, 0, x, 2, 3); // 显示浮点数 整数显示2位 小数显示三位 +// 备注信息 特别注意当发现小数部分显示的值与你写入的值不一样的时候， +// 可能是由于浮点数精度丢失问题导致的，这并不是显示函数的问题， +// 有关问题的详情，请自行百度学习 浮点数精度丢失问题。 +// 负数会显示一个 ‘-’号 +//------------------------------------------------------------------------------------------------------------------- +void ips200_show_float (uint16 x, uint16 y, const double dat, uint8 num, uint8 pointnum) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips200_x_max); + zf_assert(y < ips200_y_max); + zf_assert(0 < num); + zf_assert(8 >= num); + zf_assert(0 < pointnum); + zf_assert(6 >= pointnum); + + double dat_temp = dat; + double offset = 1.0; + char data_buffer[17]; + memset(data_buffer, 0, 17); + memset(data_buffer, ' ', num+pointnum+2); + + // 用来计算余数显示 123 显示 2 位则应该显示 23 + for(; 0 < num; num --) + { + offset *= 10; + } + dat_temp = dat_temp - ((int)dat_temp / (int)offset) * offset; + func_double_to_str(data_buffer, dat_temp, pointnum); + ips200_show_string(x, y, data_buffer); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 显示二值图像 数据每八个点组成一个字节数据 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips200_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips200_y_max-1] +// 参数说明 *image 图像数组指针 +// 参数说明 width 图像实际宽度 +// 参数说明 height 图像实际高度 +// 参数说明 dis_width 图像显示宽度 参数范围 [0, ips200_x_max] +// 参数说明 dis_height 图像显示高度 参数范围 [0, ips200_y_max] +// 返回参数 void +// 使用示例 ips200_show_binary_image(0, 0, ov7725_image_binary[0], OV7725_W, OV7725_H, OV7725_W, OV7725_H); +// 备注信息 用于显示小钻风的未解压的压缩二值化图像 +// 这个函数不可以用来直接显示总钻风的未压缩的二值化图像 +// 这个函数不可以用来直接显示总钻风的未压缩的二值化图像 +// 这个函数不可以用来直接显示总钻风的未压缩的二值化图像 +//------------------------------------------------------------------------------------------------------------------- +void ips200_show_binary_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips200_x_max); + zf_assert(y < ips200_y_max); + zf_assert(NULL != image); + + uint32 i = 0, j = 0; + uint8 temp = 0; + uint32 width_index = 0; + uint16 data_buffer[dis_width]; + const uint8 *image_temp; + + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(0); + } + ips200_set_region(x, y, x + dis_width - 1, y + dis_height - 1); // 设置显示区域 + + for(j = 0; j < dis_height; j ++) + { + image_temp = image + j * height / dis_height * width / 8; // 直接对 image 操作会 Hardfault 暂时不知道为什么 + for(i = 0; i < dis_width; i ++) + { + width_index = i * width / dis_width; + temp = *(image_temp + width_index / 8); // 读取像素点 + if(0x80 & (temp << (width_index % 8))) + { + data_buffer[i] = (RGB565_WHITE); + } + else + { + data_buffer[i] = (RGB565_BLACK); + } + } + ips200_write_16bit_data_array(data_buffer, dis_width); + } + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(1); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 显示 8bit 灰度图像 带二值化阈值 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips200_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips200_y_max-1] +// 参数说明 *image 图像数组指针 +// 参数说明 width 图像实际宽度 +// 参数说明 height 图像实际高度 +// 参数说明 dis_width 图像显示宽度 参数范围 [0, ips200_x_max] +// 参数说明 dis_height 图像显示高度 参数范围 [0, ips200_y_max] +// 参数说明 threshold 二值化显示阈值 0-不开启二值化 +// 返回参数 void +// 使用示例 ips200_show_gray_image(0, 0, mt9v03x_image[0], MT9V03X_W, MT9V03X_H, MT9V03X_W, MT9V03X_H, 0); +// 备注信息 用于显示总钻风的图像 +// 如果要显示二值化图像 直接修改最后一个参数为需要的二值化阈值即可 +// 如果要显示二值化图像 直接修改最后一个参数为需要的二值化阈值即可 +// 如果要显示二值化图像 直接修改最后一个参数为需要的二值化阈值即可 +//------------------------------------------------------------------------------------------------------------------- +void ips200_show_gray_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 threshold) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips200_x_max); + zf_assert(y < ips200_y_max); + zf_assert(NULL != image); + + uint32 i = 0, j = 0; + uint16 color = 0,temp = 0; + uint16 data_buffer[dis_width]; + const uint8 *image_temp; + + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(0); + } + ips200_set_region(x, y, x + dis_width - 1, y + dis_height - 1); // 设置显示区域 + + for(j = 0; j < dis_height; j ++) + { + image_temp = image + j * height / dis_height * width; // 直接对 image 操作会 Hardfault 暂时不知道为什么 + for(i = 0; i < dis_width; i ++) + { + temp = *(image_temp + i * width / dis_width); // 读取像素点 + if(threshold == 0) + { + color = (0x001f & ((temp) >> 3)) << 11; + color = color | (((0x003f) & ((temp) >> 2)) << 5); + color = color | (0x001f & ((temp) >> 3)); + data_buffer[i] = (color); + } + else if(temp < threshold) + { + data_buffer[i] = (RGB565_BLACK); + } + else + { + data_buffer[i] = (RGB565_WHITE); + } + } + ips200_write_16bit_data_array(data_buffer, dis_width); + } + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(1); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 显示 RGB565 彩色图像 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips200_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips200_y_max-1] +// 参数说明 *image 图像数组指针 +// 参数说明 width 图像实际宽度 +// 参数说明 height 图像实际高度 +// 参数说明 dis_width 图像显示宽度 参数范围 [0, ips200_x_max] +// 参数说明 dis_height 图像显示高度 参数范围 [0, ips200_y_max] +// 参数说明 color_mode 色彩模式 0-低位在前 1-高位在前 +// 返回参数 void +// 使用示例 ips200_show_rgb565_image(0, 0, scc8660_image[0], SCC8660_W, SCC8660_H, SCC8660_W, SCC8660_H, 1); +// 备注信息 用于显示凌瞳的 RGB565 的图像 +// 如果要显示低位在前的其他 RGB565 图像 修改最后一个参数即可 +// 如果要显示低位在前的其他 RGB565 图像 修改最后一个参数即可 +// 如果要显示低位在前的其他 RGB565 图像 修改最后一个参数即可 +//------------------------------------------------------------------------------------------------------------------- +void ips200_show_rgb565_image (uint16 x, uint16 y, const uint16 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 color_mode) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips200_x_max); + zf_assert(y < ips200_y_max); + zf_assert(NULL != image); + + uint32 i = 0, j = 0; + uint16 data_buffer[dis_width]; + const uint16 *image_temp; + + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(0); + } + ips200_set_region(x, y, x + dis_width - 1, y + dis_height - 1); // 设置显示区域 + + for(j = 0; j < dis_height; j ++) + { + image_temp = image + j * height / dis_height * width; // 直接对 image 操作会 Hardfault 暂时不知道为什么 + for(i = 0; i < dis_width; i ++) + { + data_buffer[i] = *(image_temp + i * width / dis_width); // 读取像素点 + } + if(color_mode) + { + ips200_write_8bit_data_array((uint8 *)data_buffer, dis_width * 2); + } + else + { + ips200_write_16bit_data_array(data_buffer, dis_width); + } + } + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(1); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 显示波形 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips200_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips200_y_max-1] +// 参数说明 *wave 波形数组指针 +// 参数说明 width 波形实际宽度 +// 参数说明 value_max 波形实际最大值 +// 参数说明 dis_width 波形显示宽度 参数范围 [0, ips200_x_max] +// 参数说明 dis_value_max 波形显示最大值 参数范围 [0, ips200_y_max] +// 返回参数 void +// 使用示例 ips200_show_wave(0, 0, data, 128, 64, 64, 32); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips200_show_wave (uint16 x, uint16 y, const uint16 *wave, uint16 width, uint16 value_max, uint16 dis_width, uint16 dis_value_max) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips200_x_max); + zf_assert(y < ips200_y_max); + zf_assert(NULL != wave); + + uint32 i = 0, j = 0; + uint32 width_index = 0, value_max_index = 0; + uint16 data_buffer[dis_width]; + + + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(0); + } + ips200_set_region(x, y, x + dis_width - 1, y + dis_value_max - 1); // 设置显示区域 + for(j = 0; j < dis_value_max; j ++) + { + for(i = 0; i < dis_width; i ++) + { + data_buffer[i] = (ips200_bgcolor); + } + ips200_write_16bit_data_array(data_buffer, dis_width); + } + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(1); + } + + for(i = 0; i < dis_width; i ++) + { + width_index = i * width / dis_width; + value_max_index = *(wave + width_index) * (dis_value_max - 1) / value_max; + ips200_draw_point(i + x, (dis_value_max - 1) - value_max_index + y, ips200_pencolor); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 汉字显示 +// 参数说明 x 坐标x方向的起点 参数范围 [0, ips200_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, ips200_y_max-1] +// 参数说明 size 取模的时候设置的汉字字体大小 也就是一个汉字占用的点阵长宽为多少个点 取模的时候需要长宽是一样的 +// 参数说明 *chinese_buffer 需要显示的汉字数组 +// 参数说明 number 需要显示多少位 +// 参数说明 color 颜色格式 RGB565 或者可以使用 zf_common_font.h 内 rgb565_color_enum 枚举值或者自行写入 +// 返回参数 void +// 使用示例 ips200_show_chinese(0, 0, 16, chinese_test[0], 4, RGB565_RED);//显示font文件里面的 示例 +// 备注信息 使用PCtoLCD2002软件取模 阴码、逐行式、顺向 16*16 +//------------------------------------------------------------------------------------------------------------------- +void ips200_show_chinese (uint16 x, uint16 y, uint8 size, const uint8 *chinese_buffer, uint8 number, const uint16 color) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < ips200_x_max); + zf_assert(y < ips200_y_max); + zf_assert(NULL != chinese_buffer); + + int i = 0, j = 0, k = 0; + uint8 temp = 0, temp1 = 0, temp2 = 0; + const uint8 *p_data = chinese_buffer; + + temp2 = size / 8; + + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(0); + } + ips200_set_region(x, y, number * size - 1 + x, y + size - 1); + + for(i = 0; i < size; i ++) + { + temp1 = number; + p_data = chinese_buffer + i * temp2; + while(temp1 --) + { + for(k = 0; k < temp2; k ++) + { + for(j = 8; 0 < j; j --) + { + temp = (*p_data >> (j - 1)) & 0x01; + if(temp) + { + ips200_write_16bit_data(color); + } + else + { + ips200_write_16bit_data(ips200_bgcolor); + } + } + p_data ++; + } + p_data = p_data - temp2 + temp2 * size; + } + } + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(1); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 2寸 IPS液晶初始化 +// 参数说明 type_select 两寸屏接口类型 IPS200_TYPE_SPI 为 SPI 接口串口两寸屏 IPS200_TYPE_PARALLEL8 为 8080 协议八位并口两寸屏 +// 返回参数 void +// 使用示例 ips200_init(IPS200_TYPE_PARALLEL8); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void ips200_init (ips200_type_enum type_select) +{ + if(IPS200_TYPE_SPI == type_select) + { + ips200_display_type = IPS200_TYPE_SPI; + ips_rst_pin = IPS200_RST_PIN_SPI; + ips_bl_pin = IPS200_BLk_PIN_SPI; + ips_cs_pin = IPS200_CS_PIN_SPI; +#if IPS200_USE_SOFT_SPI + soft_spi_init(&ips200_spi, 0, IPS200_SOFT_SPI_DELAY, IPS200_SCL_PIN, IPS200_SDA_PIN, SOFT_SPI_PIN_NULL, SOFT_SPI_PIN_NULL); +#else + spi_init(IPS200_SPI, SPI_MODE0, IPS200_SPI_SPEED, IPS200_SCL_PIN_SPI, IPS200_SDA_PIN_SPI, SPI_MISO_NULL, SPI_CS_NULL); +#endif + + gpio_init(IPS200_DC_PIN_SPI, GPO, GPIO_LOW, GPO_PUSH_PULL); + gpio_init(ips_rst_pin, GPO, GPIO_LOW, GPO_PUSH_PULL); + gpio_init(IPS200_CS_PIN_SPI, GPO, GPIO_LOW, GPO_PUSH_PULL); + gpio_init(ips_bl_pin, GPO, GPIO_HIGH, GPO_PUSH_PULL); + } + else + { + ips200_display_type = IPS200_TYPE_PARALLEL8; + ips_rst_pin = IPS200_RST_PIN_PARALLEL8; + ips_bl_pin = IPS200_BL_PIN_PARALLEL8; + ips_cs_pin = IPS200_CS_PIN_PARALLEL8; + + gpio_init(IPS200_RD_PIN_PARALLEL8, GPO, 1, GPO_PUSH_PULL); + gpio_init(IPS200_WR_PIN_PARALLEL8, GPO, 1, GPO_PUSH_PULL); + gpio_init(IPS200_RS_PIN_PARALLEL8, GPO, 1, GPO_PUSH_PULL); + gpio_init(IPS200_RST_PIN_PARALLEL8, GPO, 1, GPO_PUSH_PULL); + gpio_init(IPS200_CS_PIN_PARALLEL8, GPO, 1, GPO_PUSH_PULL); + gpio_init(IPS200_BL_PIN_PARALLEL8, GPO, 1, GPO_PUSH_PULL); + //#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) + //#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) + //#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) + //#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) + //#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) + //#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) + //#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) + + uint8 i = 0; + uint8 pin_value = (((uint32)IPS200_DATAPORT - GPIOA_BASE)/0x400) * 0x20 + DATA_START_NUM; // 获取端口的枚举体值 + + for(i = 0;i < 8;i++) + { + gpio_init((gpio_pin_enum)(pin_value + i), GPO, 0, GPO_PUSH_PULL); + } + } + + ips200_set_dir(ips200_display_dir); + ips200_set_color(ips200_pencolor, ips200_bgcolor); + + IPS200_BL(1); + IPS200_RST(0); + system_delay_ms(5); + IPS200_RST(1); + system_delay_ms(120); + + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(0); + } + ips200_write_command(0x11); + system_delay_ms(120); + + ips200_write_command(0x36); + switch(ips200_display_dir) + { + case IPS200_PORTAIT: ips200_write_8bit_data(0x00); break; + case IPS200_PORTAIT_180: ips200_write_8bit_data(0xC0); break; + case IPS200_CROSSWISE: ips200_write_8bit_data(0x70); break; + case IPS200_CROSSWISE_180: ips200_write_8bit_data(0xA0); break; + } + + ips200_write_command(0x3A); + ips200_write_8bit_data(0x05); + + ips200_write_command(0xB2); + ips200_write_8bit_data(0x0C); + ips200_write_8bit_data(0x0C); + ips200_write_8bit_data(0x00); + ips200_write_8bit_data(0x33); + ips200_write_8bit_data(0x33); + + ips200_write_command(0xB7); + ips200_write_8bit_data(0x35); + + ips200_write_command(0xBB); + ips200_write_8bit_data(0x29); // 32 Vcom=1.35V + + ips200_write_command(0xC2); + ips200_write_8bit_data(0x01); + + ips200_write_command(0xC3); + ips200_write_8bit_data(0x19); // GVDD=4.8V + + ips200_write_command(0xC4); + ips200_write_8bit_data(0x20); // VDV, 0x20:0v + + ips200_write_command(0xC5); + ips200_write_8bit_data(0x1A); // VCOM Offset Set + + ips200_write_command(0xC6); + ips200_write_8bit_data(0x01F); // 0x0F:60Hz + + ips200_write_command(0xD0); + ips200_write_8bit_data(0xA4); + ips200_write_8bit_data(0xA1); + + ips200_write_command(0xE0); + ips200_write_8bit_data(0xD0); + ips200_write_8bit_data(0x08); + ips200_write_8bit_data(0x0E); + ips200_write_8bit_data(0x09); + ips200_write_8bit_data(0x09); + ips200_write_8bit_data(0x05); + ips200_write_8bit_data(0x31); + ips200_write_8bit_data(0x33); + ips200_write_8bit_data(0x48); + ips200_write_8bit_data(0x17); + ips200_write_8bit_data(0x14); + ips200_write_8bit_data(0x15); + ips200_write_8bit_data(0x31); + ips200_write_8bit_data(0x34); + + ips200_write_command(0xE1); + ips200_write_8bit_data(0xD0); + ips200_write_8bit_data(0x08); + ips200_write_8bit_data(0x0E); + ips200_write_8bit_data(0x09); + ips200_write_8bit_data(0x09); + ips200_write_8bit_data(0x15); + ips200_write_8bit_data(0x31); + ips200_write_8bit_data(0x33); + ips200_write_8bit_data(0x48); + ips200_write_8bit_data(0x17); + ips200_write_8bit_data(0x14); + ips200_write_8bit_data(0x15); + ips200_write_8bit_data(0x31); + ips200_write_8bit_data(0x34); + + ips200_write_command(0x21); + + ips200_write_command(0x29); + if(IPS200_TYPE_SPI == ips200_display_type) + { + IPS200_CS(1); + } + + ips200_clear(); // 初始化为白屏 + ips200_debug_init(); +} diff --git a/libraries/zf_device/zf_device_ips200.h b/libraries/zf_device/zf_device_ips200.h new file mode 100644 index 0000000..8a4c04d --- /dev/null +++ b/libraries/zf_device/zf_device_ips200.h @@ -0,0 +1,210 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_ips200 +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* // 双排排针 并口两寸屏 硬件引脚 +* RD 查看 zf_device_ips200.h 中 IPS200_RD_PIN_PARALLEL8 宏定义 +* WR 查看 zf_device_ips200.h 中 IPS200_WR_PIN_PARALLEL8 宏定义 +* RS 查看 zf_device_ips200.h 中 IPS200_RS_PIN_PARALLEL8 宏定义 +* RST 查看 zf_device_ips200.h 中 IPS200_RST_PIN_PARALLEL8 宏定义 +* CS 查看 zf_device_ips200.h 中 IPS200_CS_PIN_PARALLEL8 宏定义 +* BL 查看 zf_device_ips200.h 中 IPS200_BL_PIN_PARALLEL8 宏定义 +* D0-D7 查看 zf_device_ips200.h 中 IPS200_Dx_PIN_PARALLEL8 宏定义 +* // 单排排针 SPI 两寸屏 硬件引脚 +* SCL 查看 zf_device_ips200.h 中 IPS200_SCL_PIN_SPI 宏定义 +* SDA 查看 zf_device_ips200.h 中 IPS200_SDA_PIN_SPI 宏定义 +* RST 查看 zf_device_ips200.h 中 IPS200_RST_PIN_SPI 宏定义 +* DC 查看 zf_device_ips200.h 中 IPS200_DC_PIN_SPI 宏定义 +* CS 查看 zf_device_ips200.h 中 IPS200_CS_PIN_SPI 宏定义 +* BLk 查看 zf_device_ips200.h 中 IPS200_BLk_PIN_SPI 宏定义 +* 电源引脚 +* VCC 3.3V电源 +* GND 电源地 +* 最大分辨率 320 * 240 +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_ips200_h_ +#define _zf_device_ips200_h_ + +#include "zf_common_typedef.h" + + +// --------------------单排两寸屏幕SPI接口引脚定义--------------------// + +#define IPS200_USE_SOFT_SPI (0 ) // 默认使用硬件 SPI 方式驱动 建议使用硬件 SPI 方式驱动 +#if IPS200_USE_SOFT_SPI // 这两段 颜色正常的才是正确的 颜色灰的就是没有用的 +//====================================================软件 SPI 驱动==================================================== +// 如果使用的是单排排针的两寸屏幕 SPI 驱动控制引脚 可以修改 +#define IPS200_SOFT_SPI_DELAY (1 ) // 软件 SPI 的时钟延时周期 数值越小 SPI 通信速率越快 +#define IPS200_SCL_PIN (B13) // 软件 SPI SCK 引脚 +#define IPS200_SDA_PIN (B15) // 软件 SPI MOSI 引脚 +//====================================================软件 SPI 驱动==================================================== +#else +//====================================================硬件 SPI 驱动==================================================== +// 如果使用的是单排排针的两寸屏幕 SPI 驱动控制引脚 可以修改 +#define IPS200_SPI_SPEED (72 * 1000 * 1000 ) // 硬件 SPI 速率 这里设置为系统时钟二分频 +#define IPS200_SPI (SPI_2 ) // 硬件 SPI 号 +#define IPS200_SCL_PIN_SPI (SPI2_MAP0_SCK_B13 ) // 硬件 SPI SCK 引脚 +#define IPS200_SDA_PIN_SPI (SPI2_MAP0_MOSI_B15) // 硬件 SPI MOSI 引脚 +//====================================================硬件 SPI 驱动==================================================== +#endif + +// 如果使用的是单排排针的两寸屏幕 SPI 驱动控制引脚 可以修改 +#define IPS200_RST_PIN_SPI (B7 ) // 液晶复位引脚定义 +#define IPS200_DC_PIN_SPI (D7 ) // 液晶命令位引脚定义 +#define IPS200_CS_PIN_SPI (D4 ) +#define IPS200_BLk_PIN_SPI (D0 ) + + +// --------------------单排两寸屏幕SPI接口引脚定义--------------------// + + + +// --------------------双排两寸屏幕并口引脚定义--------------------// +#define IPS200_RD_PIN_PARALLEL8 (B13) +#define IPS200_WR_PIN_PARALLEL8 (B15) +#define IPS200_RS_PIN_PARALLEL8 (B7 ) +#define IPS200_RST_PIN_PARALLEL8 (D7 ) +#define IPS200_CS_PIN_PARALLEL8 (D4 ) +#define IPS200_BL_PIN_PARALLEL8 (D0 ) + +//8个数据引脚必须连续 例如B0-B7,B6-B13等等。 +//--------------数据端口寄存器-------------- +#define IPS200_DATAPORT GPIOE + +//--------------数据端口起始地址偏移-------------- +#define DATA_START_NUM 0 + +//例：D1-D8 IPS200_DATAPORT设置为GPIOD DATA_START_NUM设置为1 +//例：C5-C12 IPS200_DATAPORT设置为GPIOC DATA_START_NUM设置为5 +// --------------------双排SPI接口两寸屏幕引脚定义--------------------// + +#define IPS200_DEFAULT_DISPLAY_DIR (IPS200_PORTAIT) // 默认的显示方向 +#define IPS200_DEFAULT_PENCOLOR (RGB565_RED ) // 默认的画笔颜色 +#define IPS200_DEFAULT_BGCOLOR (RGB565_WHITE ) // 默认的背景颜色 +#define IPS200_DEFAULT_DISPLAY_FONT (IPS200_8X16_FONT) // 默认的字体模式 + +// 控制语句 +#define IPS200_RD(x) ((x) ? (gpio_high(IPS200_RD_PIN_PARALLEL8)) : (gpio_low(IPS200_RD_PIN_PARALLEL8))) +#define IPS200_WR(x) ((x) ? (gpio_high(IPS200_WR_PIN_PARALLEL8)) : (gpio_low(IPS200_WR_PIN_PARALLEL8))) +#define IPS200_RST(x) ((x) ? (gpio_high(ips_rst_pin)) : (gpio_low(ips_rst_pin))) +#define IPS200_BL(x) ((x) ? (gpio_high(ips_bl_pin)) : (gpio_low(ips_bl_pin))) +#define IPS200_RS(x) ((x) ? (gpio_high(IPS200_RS_PIN_PARALLEL8)) : (gpio_low(IPS200_RS_PIN_PARALLEL8))) + +#define IPS200_DC(x) ((x) ? (gpio_high(IPS200_DC_PIN_SPI)) : (gpio_low(IPS200_DC_PIN_SPI))) +#define IPS200_CS(x) ((x) ? (gpio_high(ips_cs_pin)) : (gpio_low(ips_cs_pin))) + + +typedef enum +{ + IPS200_TYPE_SPI, // SPI 驱动 + IPS200_TYPE_PARALLEL8, // 并口驱动 +}ips200_type_enum; + +typedef enum +{ + IPS200_PORTAIT = 0, // 竖屏模式 + IPS200_PORTAIT_180 = 1, // 竖屏模式 旋转180 + IPS200_CROSSWISE = 2, // 横屏模式 + IPS200_CROSSWISE_180 = 3, // 横屏模式 旋转180 +}ips200_dir_enum; + +typedef enum +{ + IPS200_6X8_FONT = 0, // 6x8 字体 + IPS200_8X16_FONT = 1, // 8x16 字体 + IPS200_16X16_FONT = 2, // 16x16 字体 目前不支持 +}ips200_font_size_enum; + +void ips200_clear (void); +void ips200_full (const uint16 color); +void ips200_set_dir (ips200_dir_enum dir); +void ips200_set_font (ips200_font_size_enum font); +void ips200_set_color (const uint16 pen, const uint16 bgcolor); +void ips200_draw_point (uint16 x, uint16 y, const uint16 color); +void ips200_draw_line (uint16 x_start, uint16 y_start, uint16 x_end, uint16 y_end, const uint16 color); + +void ips200_show_char (uint16 x, uint16 y, const char dat); +void ips200_show_string (uint16 x, uint16 y, const char dat[]); +void ips200_show_int (uint16 x, uint16 y, const int32 dat, uint8 num); +void ips200_show_uint (uint16 x, uint16 y, const uint32 dat, uint8 num); +void ips200_show_float (uint16 x, uint16 y, const double dat, uint8 num, uint8 pointnum); + +void ips200_show_binary_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height); +void ips200_show_gray_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 threshold); +void ips200_show_rgb565_image (uint16 x, uint16 y, const uint16 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 color_mode); + +void ips200_show_wave (uint16 x, uint16 y, const uint16 *wave, uint16 width, uint16 value_max, uint16 dis_width, uint16 dis_value_max); +void ips200_show_chinese (uint16 x, uint16 y, uint8 size, const uint8 *chinese_buffer, uint8 number, const uint16 color); + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 显示小钻风图像 +// 参数说明 p 图像数组 +// 参数说明 width 显示宽度 +// 参数说明 height 显示高度 +// 返回参数 void +// 使用示例 ips200_displayimage7725(ov7725_image_binary[0], 80, 60); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +#define ips200_displayimage7725(p, width, height) (ips200_show_binary_image(0, 0, (p), OV7725_W, OV7725_H, (width), (height))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 显示总钻风图像 不带二值化 显示灰度图像 +// 参数说明 p 图像数组 +// 参数说明 width 显示宽度 +// 参数说明 height 显示高度 +// 返回参数 void +// 使用示例 ips200_displayimage03x(mt9v03x_image[0], 94, 60); +// 备注信息 如果要显示二值化图像就去调用 ips200_show_gray_image 函数 +//------------------------------------------------------------------------------------------------------------------- +#define ips200_displayimage03x(p, width, height) (ips200_show_gray_image(0, 0, (p), MT9V03X_W, MT9V03X_H, (width), (height), 0)) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS200 显示凌瞳图像 +// 参数说明 p 图像数组 +// 参数说明 width 显示宽度 +// 参数说明 height 显示高度 +// 返回参数 void +// 使用示例 ips200_displayimage8660(scc8660_image[0], 80, 60); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +#define ips200_displayimage8660(p, width, height) (ips200_show_rgb565_image(0, 0, (p), SCC8660_W, SCC8660_H, (width), (height), 1)) + +void ips200_init (ips200_type_enum type_select); + +#endif diff --git a/libraries/zf_device/zf_device_k24c02.c b/libraries/zf_device/zf_device_k24c02.c new file mode 100644 index 0000000..78c3498 --- /dev/null +++ b/libraries/zf_device/zf_device_k24c02.c @@ -0,0 +1,148 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_k24c02 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* IIC ͨŶӦϵ +* SCL 鿴 zf_device_k24c02.h K24C02_SCL_PIN 궨 +* SDA 鿴 zf_device_k24c02.h K24C02_SDA_PIN 궨 +* Ӳ IIC ͨŶӦϵ +* SCL 鿴 zf_device_k24c02.h K24C02_SCL_PIN 궨 +* SDA 鿴 zf_device_k24c02.h K24C02_SDA_PIN 궨 +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_driver_delay.h" +#include "zf_driver_iic.h" +#include "zf_driver_soft_iic.h" + +#include "zf_device_k24c02.h" + +#if K24C02_USE_SOFT_IIC +static soft_iic_info_struct k24c02_iic_struct; + +//------------------------------------------------------------------------------------------------------------------- +// K24C02 IIC дĴ +// ˵ reg Ĵ +// ˵ *data ݻ +// ˵ len ݳ +// ز void +// ʹʾ k24c02_write_registers(page_num*8, (uint8 *)&k24c02_union_buffer[0], K24C02_PAGE_SIZE); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +#define k24c02_write_registers(reg, data, len) (soft_iic_write_8bit_registers(&k24c02_iic_struct, (reg), (data), (len))) + +//------------------------------------------------------------------------------------------------------------------- +// K24C02 IIC Ĵ +// ˵ reg Ĵ +// ˵ *data ݻ +// ˵ len ݳ +// ز void +// ʹʾ k24c02_read_registers(page_num*8, (uint8 *)&k24c02_union_buffer[0], K24C02_PAGE_SIZE); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +#define k24c02_read_registers(reg, data, len) (soft_iic_read_8bit_registers(&k24c02_iic_struct, (reg), (data), (len))) +#else +//------------------------------------------------------------------------------------------------------------------- +// K24C02 IIC дĴ +// ˵ reg Ĵ +// ˵ *data ݻ +// ˵ len ݳ +// ز void +// ʹʾ k24c02_write_registers(page_num*8, (uint8 *)&k24c02_union_buffer[0], K24C02_PAGE_SIZE); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +#define k24c02_write_registers(reg, data, len) (iic_write_8bit_registers(K24C02_IIC, K24C02_DEV_ADDR, (reg), (data), (len))) + +//------------------------------------------------------------------------------------------------------------------- +// K24C02 IIC Ĵ +// ˵ reg Ĵ +// ˵ *data ݻ +// ˵ len ݳ +// ز void +// ʹʾ k24c02_read_registers(page_num*8, (uint8 *)&k24c02_union_buffer[0], K24C02_PAGE_SIZE); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +#define k24c02_read_registers(reg, data, len) (iic_read_8bit_registers(K24C02_IIC, K24C02_DEV_ADDR, (reg), (data), (len))) +#endif + +k24c02_data_union k24c02_union_buffer[K24C02_DATA_BUFFER_SIZE]; + +//------------------------------------------------------------------------------------------------------------------- +// K24C02 ָҳݵ +// ˵ page_num ָҳ +// ز void +// ʹʾ k24c02_read_page_to_buffer(K24C02_PAGE_0); +// עϢ ݸµ ñֱӶȡ +//------------------------------------------------------------------------------------------------------------------- +void k24c02_read_page_to_buffer (k24c02_page_enum page_num) +{ + k24c02_read_registers(page_num*8, (uint8 *)&k24c02_union_buffer[0], K24C02_PAGE_SIZE); +} + +//------------------------------------------------------------------------------------------------------------------- +// K24C02 дָҳ +// ˵ page_num ָҳ +// ز void +// ʹʾ k24c02_write_page_from_buffer(K24C02_PAGE_0); +// עϢ ݻд K24C02 ָҳ +//------------------------------------------------------------------------------------------------------------------- +uint8 k24c02_write_page_from_buffer (k24c02_page_enum page_num) +{ + uint8 return_state = 0; + k24c02_write_registers(page_num*8, (uint8 *)&k24c02_union_buffer[0], K24C02_PAGE_SIZE); + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// brief ʼ K24C02 +// param void +// return uint8 1-ʼʧ 0-ʼɹ +// ʹʾ k24c02_init(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 k24c02_init (void) +{ + uint8 return_state = 0; +#if K24C02_USE_SOFT_IIC + soft_iic_init(&k24c02_iic_struct, K24C02_DEV_ADDR, K24C02_SOFT_IIC_DELAY, K24C02_SCL_PIN, K24C02_SDA_PIN); +#else + iic_init(K24C02_IIC, K24C02_DEV_ADDR, K24C02_IIC_SPEED, K24C02_SCL_PIN, K24C02_SDA_PIN); +#endif + return return_state; +} diff --git a/libraries/zf_device/zf_device_k24c02.h b/libraries/zf_device/zf_device_k24c02.h new file mode 100644 index 0000000..bd87fe4 --- /dev/null +++ b/libraries/zf_device/zf_device_k24c02.h @@ -0,0 +1,112 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_k24c02 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* IIC ͨŶӦϵ +* SCL 鿴 zf_device_k24c02.h K24C02_SCL_PIN 궨 +* SDA 鿴 zf_device_k24c02.h K24C02_SDA_PIN 궨 +* Ӳ IIC ͨŶӦϵ +* SCL 鿴 zf_device_k24c02.h K24C02_SCL_PIN 궨 +* SDA 鿴 zf_device_k24c02.h K24C02_SDA_PIN 궨 +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_k24c02_h_ +#define _zf_device_k24c02_h_ + +#include "zf_common_typedef.h" + +#define K24C02_USE_SOFT_IIC (1) // Ĭʹ IIC ʽ ʹ IIC ʽ +#if K24C02_USE_SOFT_IIC // ɫIJȷ ɫҵľûõ +//==================================================== IIC ==================================================== +#define K24C02_SOFT_IIC_DELAY (500) // IIC ʱʱ ֵԽС IIC ͨԽ +#define K24C02_SCL_PIN (B10 ) // IIC SCL K24C02 SCL +#define K24C02_SDA_PIN (B11 ) // IIC SDA K24C02 SDA +//==================================================== IIC ==================================================== +#else +//====================================================Ӳ IIC ==================================================== +#define K24C02_IIC_SPEED (400000 ) // Ӳ IIC ͨ 400KHz 40KHz +#define K24C02_IIC (IIC_1 ) // Ӳ IIC +#define K24C02_SCL_PIN (IIC1_SCL_C6) // Ӳ IIC SCL K24C02 SCL +#define K24C02_SDA_PIN (IIC1_SDA_C7) // Ӳ IIC SDA K24C02 SDA +//====================================================Ӳ IIC ==================================================== +#endif + +#define K24C02_TIMEOUT_COUNT (0x00FF) // K24C02 ʱ + +//================================================ K24C02 ڲַ================================================ +#define K24C02_DEV_ADDR (0xA0 >> 1) // IICдʱĵַֽ +1Ϊȡ +//================================================ K24C02 ڲַ================================================ + +#define K24C02_SIZE (256) // 256 byte +#define K24C02_PAGE_SIZE (8) // 8 byte +#define K24C02_DATA_BUFFER_SIZE (K24C02_PAGE_SIZE / sizeof(k24c02_data_union))// Զÿҳܹ¶ٸ + +typedef enum // ö K24C02 ҳ öٶ岻û޸ +{ + K24C02_PAGE_0 , K24C02_PAGE_1 , K24C02_PAGE_2 , K24C02_PAGE_3 , + K24C02_PAGE_4 , K24C02_PAGE_5 , K24C02_PAGE_6 , K24C02_PAGE_7 , + K24C02_PAGE_8 , K24C02_PAGE_9 , K24C02_PAGE_10, K24C02_PAGE_11, + K24C02_PAGE_12, K24C02_PAGE_13, K24C02_PAGE_14, K24C02_PAGE_15, + K24C02_PAGE_16, K24C02_PAGE_17, K24C02_PAGE_18, K24C02_PAGE_19, + K24C02_PAGE_20, K24C02_PAGE_21, K24C02_PAGE_22, K24C02_PAGE_23, + K24C02_PAGE_24, K24C02_PAGE_25, K24C02_PAGE_26, K24C02_PAGE_27, + K24C02_PAGE_28, K24C02_PAGE_29, K24C02_PAGE_30, K24C02_PAGE_31, +}k24c02_page_enum; + +typedef union // ̶ݻ嵥Ԫʽ +{ + float float_type; // float + uint32 uint32_type; // uint32 + int32 int32_type; // int32 + uint16 uint16_type; // uint16 + int16 int16_type; // int16 + uint8 uint8_type; // uint8 + int8 int8_type; // int8 +}k24c02_data_union; // ݹͬһ 32bit ַ + +extern k24c02_data_union k24c02_union_buffer[K24C02_DATA_BUFFER_SIZE]; + +void k24c02_read_page (k24c02_page_enum page_num, uint8 *buf, uint8 len); +uint8 k24c02_write_page (k24c02_page_enum page_num, const uint8 *buf, uint8 len); + +void k24c02_read_page_to_buffer (k24c02_page_enum page_num); +uint8 k24c02_write_page_from_buffer (k24c02_page_enum page_num); + +uint8 k24c02_init (void); + +#endif diff --git a/libraries/zf_device/zf_device_key.c b/libraries/zf_device/zf_device_key.c new file mode 100644 index 0000000..f71ae93 --- /dev/null +++ b/libraries/zf_device/zf_device_key.c @@ -0,0 +1,148 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_key +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* // 一般是主板按键对应的引脚 +* KEY1/S1 查看 zf_device_key.h 中 KEY_LIST[0] +* KEY2/S2 查看 zf_device_key.h 中 KEY_LIST[1] +* KEY3/S3 查看 zf_device_key.h 中 KEY_LIST[2] +* KEY4/S4 查看 zf_device_key.h 中 KEY_LIST[3] +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_debug.h" + +#include "zf_device_key.h" + +static uint32 scanner_period = 0; // 按键的扫描周期 +static uint32 key_press_time[KEY_NUMBER]; // 按键信号持续时长 +static key_state_enum key_state[KEY_NUMBER]; // 按键状态 + +static const gpio_pin_enum key_index[KEY_NUMBER] = KEY_LIST; + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 按键状态扫描 +// 参数说明 void +// 返回参数 void +// 使用示例 key_scanner(); +// 备注信息 这个函数放在主循环或者 PIT 中断中 +//------------------------------------------------------------------------------------------------------------------- +void key_scanner (void) +{ + uint8 i = 0; + for(i = 0; KEY_NUMBER > i; i ++) + { + if(KEY_RELEASE_LEVEL != gpio_get_level(key_index[i])) // 按键按下 + { + key_press_time[i] ++; + if(KEY_LONG_PRESS_PERIOD / scanner_period <= key_press_time[i]) + { + key_state[i] = KEY_LONG_PRESS; + } + } + else // 按键释放 + { + if((KEY_LONG_PRESS != key_state[i]) && (KEY_MAX_SHOCK_PERIOD / scanner_period <= key_press_time[i])) + { + key_state[i] = KEY_SHORT_PRESS; + } + else + { + key_state[i] = KEY_RELEASE; + } + key_press_time[i] = 0; + } + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 获取按键状态 +// 参数说明 key_n 按键索引 +// 返回参数 key_state_enum 按键状态 +// 使用示例 key_get_state(KEY_1); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +key_state_enum key_get_state (key_index_enum key_n) +{ + return key_state[key_n]; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 清除对应按键状态 +// 参数说明 key_n 按键索引 +// 返回参数 void 无 +// 使用示例 key_clear_state(KEY_1); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void key_clear_state (key_index_enum key_n) +{ + key_state[key_n] = KEY_RELEASE; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 清除所有按键状态 +// 参数说明 void 无 +// 返回参数 void 无 +// 使用示例 key_clear_all_state(); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void key_clear_all_state (void) +{ + key_state[0] = KEY_RELEASE; + key_state[1] = KEY_RELEASE; + key_state[2] = KEY_RELEASE; + key_state[3] = KEY_RELEASE; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 按键初始化 +// 参数说明 period 按键扫描周期 以毫秒为单位 +// 返回参数 void +// 使用示例 key_init(10); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void key_init (uint32 period) +{ + zf_assert(0 < period); + uint8 loop_temp = 0; + for(loop_temp = 0; KEY_NUMBER > loop_temp; loop_temp ++) + { + gpio_init(key_index[loop_temp], GPI, GPIO_HIGH, GPI_PULL_UP); + key_state[loop_temp] = KEY_RELEASE; + } + scanner_period = period; +} diff --git a/libraries/zf_device/zf_device_key.h b/libraries/zf_device/zf_device_key.h new file mode 100644 index 0000000..f6a56d6 --- /dev/null +++ b/libraries/zf_device/zf_device_key.h @@ -0,0 +1,85 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_key +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* // 一般是主板按键对应的引脚 +* KEY1/S1 查看 zf_device_key.h 中 KEY_LIST[0] +* KEY2/S2 查看 zf_device_key.h 中 KEY_LIST[1] +* KEY3/S3 查看 zf_device_key.h 中 KEY_LIST[2] +* KEY4/S4 查看 zf_device_key.h 中 KEY_LIST[3] +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_key_h_ +#define _zf_device_key_h_ + +#include "zf_common_debug.h" + +#include "zf_driver_gpio.h" + +// 定义按键引脚 用户可以新增可以修改 默认定义四个按键 +// 定义按键顺序对应下方 key_index_enum 枚举体中定义的顺序 +// 如果用户可以新增按键 那么需要同步在下方 key_index_enum 枚举体中新增按键 +#define KEY_LIST {A8 , D8 , B12 , B0 } + +#define KEY_RELEASE_LEVEL (GPIO_HIGH) // 按键的默认状态 也就是按键释放状态的电平 +#define KEY_MAX_SHOCK_PERIOD (10 ) // 按键消抖检测时长 单位毫秒 低于这个时长的信号会被认为是杂波抖动 +#define KEY_LONG_PRESS_PERIOD (1000 ) // 最小长按时长 单位毫秒 + +typedef enum +{ + KEY_1, + KEY_2, + KEY_3, + KEY_4, + KEY_NUMBER, +}key_index_enum; // 按键索引 对应上方定义的按键引脚个数 默认定义四个按键 + +typedef enum +{ + KEY_RELEASE, // 按键释放状态 + KEY_SHORT_PRESS, // 按键短按状态 + KEY_LONG_PRESS, // 按键长按状态 +}key_state_enum; + +void key_scanner (void); +key_state_enum key_get_state (key_index_enum key_n); +void key_clear_state (key_index_enum key_n); +void key_clear_all_state (void); +void key_init (uint32 period); + +#endif diff --git a/libraries/zf_device/zf_device_mpu6050.c b/libraries/zf_device/zf_device_mpu6050.c new file mode 100644 index 0000000..11fe409 --- /dev/null +++ b/libraries/zf_device/zf_device_mpu6050.c @@ -0,0 +1,219 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_mpu6050 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* IIC ͨŶӦϵ +* SCL 鿴 zf_device_mpu6050.h MPU6050_SOFT_IIC_SCL 궨 +* SDA 鿴 zf_device_mpu6050.h MPU6050_SOFT_IIC_SDA 궨 +* Ӳ IIC ͨŶӦϵ +* SCL 鿴 zf_device_mpu6050.h MPU6050_IIC_SCL 궨 +* SDA 鿴 zf_device_mpu6050.h MPU6050_IIC_SDA 궨 +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_device_mpu6050.h" + +int16 mpu6050_gyro_x = 0, mpu6050_gyro_y = 0, mpu6050_gyro_z = 0; // gyro () +int16 mpu6050_acc_x = 0, mpu6050_acc_y = 0, mpu6050_acc_z = 0; // ٶȼ acc (accelerometer ٶȼ) + +#if MPU6050_USE_SOFT_IIC +static soft_iic_info_struct mpu6050_iic_struct; + +#define mpu6050_write_register(reg, data) (soft_iic_write_8bit_register(&mpu6050_iic_struct, (reg), (data))) +#define mpu6050_read_register(reg) (soft_iic_read_8bit_register(&mpu6050_iic_struct, (reg))) +#define mpu6050_read_registers(reg, data, len) (soft_iic_read_8bit_registers(&mpu6050_iic_struct, (reg), (data), (len))) +#else +#define mpu6050_write_register(reg, data) (iic_write_8bit_register(MPU6050_IIC, MPU6050_DEV_ADDR, (reg), (data))) +#define mpu6050_read_register(reg) (iic_read_8bit_register(MPU6050_IIC, MPU6050_DEV_ADDR, (reg))) +#define mpu6050_read_registers(reg, data, len) (iic_read_8bit_registers(MPU6050_IIC, MPU6050_DEV_ADDR, (reg), (data), (len))) +#endif + + +//------------------------------------------------------------------------------------------------------------------- +// MPU6050 Լ +// ˵ void +// ز uint8 1-Լʧ 0-Լɹ +// ʹʾ if(mpu6050_self1_check()) +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static uint8 mpu6050_self1_check (void) +{ + uint8 dat = 0, return_state = 0; + uint16 timeout_count = 0; + + mpu6050_write_register(MPU6050_PWR_MGMT_1, 0x00); // ״̬ + mpu6050_write_register(MPU6050_SMPLRT_DIV, 0x07); // 125HZ + while(0x07 != dat) + { + if(timeout_count ++ > MPU6050_TIMEOUT_COUNT) + { + return_state = 1; + break; + } + dat = mpu6050_read_register(MPU6050_SMPLRT_DIV); + system_delay_ms(10); + } + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// ȡ MPU6050 ٶȼ +// ˵ void +// ز void +// ʹʾ mpu6050_get_acc(); // ִиúֱӲ鿴Ӧı +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void mpu6050_get_acc (void) +{ + uint8 dat[6]; + + mpu6050_read_registers(MPU6050_ACCEL_XOUT_H, dat, 6); + mpu6050_acc_x = (int16)(((uint16)dat[0] << 8 | dat[1])); + mpu6050_acc_y = (int16)(((uint16)dat[2] << 8 | dat[3])); + mpu6050_acc_z = (int16)(((uint16)dat[4] << 8 | dat[5])); +} + +//------------------------------------------------------------------------------------------------------------------- +// ȡ MPU6050 +// ˵ void +// ز void +// ʹʾ mpu6050_get_gyro(); // ִиúֱӲ鿴Ӧı +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void mpu6050_get_gyro (void) +{ + uint8 dat[6]; + + mpu6050_read_registers(MPU6050_GYRO_XOUT_H, dat, 6); + mpu6050_gyro_x = (int16)(((uint16)dat[0] << 8 | dat[1])); + mpu6050_gyro_y = (int16)(((uint16)dat[2] << 8 | dat[3])); + mpu6050_gyro_z = (int16)(((uint16)dat[4] << 8 | dat[5])); +} + +//------------------------------------------------------------------------------------------------------------------- +// MPU6050 ٶȼתΪʵ +// ˵ gyro_value ļٶȼ +// ز void +// ʹʾ float data = mpu6050_acc_transition(mpu6050_acc_x); // λΪ g(m/s^2) +// עϢ +//------------------------------------------------------------------------------------------------------------------- +float mpu6050_acc_transition (int16 acc_value) +{ + float acc_data = 0; + switch(MPU6050_ACC_SAMPLE) + { + case 0x00: acc_data = (float)acc_value / 16384; break; // 0x00 ٶȼΪ:2g ȡļٶȼ 16384 תΪλݣλg(m/s^2) + case 0x08: acc_data = (float)acc_value / 8192; break; // 0x08 ٶȼΪ:4g ȡļٶȼ 8192 תΪλݣλg(m/s^2) + case 0x10: acc_data = (float)acc_value / 4096; break; // 0x10 ٶȼΪ:8g ȡļٶȼ 4096 תΪλݣλg(m/s^2) + case 0x18: acc_data = (float)acc_value / 2048; break; // 0x18 ٶȼΪ:16g ȡļٶȼ 2048 תΪλݣλg(m/s^2) + default: break; + } + return acc_data; +} + +//------------------------------------------------------------------------------------------------------------------- +// MPU6050 תΪʵ +// ˵ gyro_value +// ز void +// ʹʾ float data = mpu6050_gyro_transition(mpu6050_gyro_x); // λΪ/s +// עϢ +//------------------------------------------------------------------------------------------------------------------- +float mpu6050_gyro_transition (int16 gyro_value) +{ + float gyro_data = 0; + switch(MPU6050_GYR_SAMPLE) + { + case 0x00: gyro_data = (float)gyro_value / 131.0f; break; // 0x00 Ϊ:250 dps ȡݳ 131 תΪλݣλΪ/s + case 0x08: gyro_data = (float)gyro_value / 65.5f; break; // 0x08 Ϊ:500 dps ȡݳ 65.5 תΪλݣλΪ/s + case 0x10: gyro_data = (float)gyro_value / 32.8f; break; // 0x10 Ϊ:1000dps ȡݳ 32.8 תΪλݣλΪ/s + case 0x18: gyro_data = (float)gyro_value / 16.4f; break; // 0x18 Ϊ:2000dps ȡݳ 16.4 תΪλݣλΪ/s + default: break; + } + return gyro_data; +} + +//------------------------------------------------------------------------------------------------------------------- +// ʼ MPU6050 +// ˵ void +// ز uint8 1-ʼʧ 0-ʼɹ +// ʹʾ mpu6050_init(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 mpu6050_init (void) +{ + uint8 return_state = 0; +#if MPU6050_USE_SOFT_IIC + soft_iic_init(&mpu6050_iic_struct, MPU6050_DEV_ADDR, MPU6050_SOFT_IIC_DELAY, MPU6050_SCL_PIN, MPU6050_SDA_PIN); +#else + iic_init(MPU6050_IIC, MPU6050_DEV_ADDR, MPU6050_IIC_SPEED, MPU6050_SCL_PIN, MPU6050_SDA_PIN); +#endif + system_delay_ms(100); // ϵʱ + + do + { + if(mpu6050_self1_check()) + { + // ˶Ϣ ʾλ + // ô MPU6050 Լʱ˳ + // һ½û ûܾǻ + zf_log(0, "MPU6050 self check error."); + return_state = 1; + break; + } + mpu6050_write_register(MPU6050_PWR_MGMT_1, 0x00); // ״̬ + mpu6050_write_register(MPU6050_SMPLRT_DIV, 0x07); // 125HZ + mpu6050_write_register(MPU6050_CONFIG, 0x04); + + mpu6050_write_register(MPU6050_GYRO_CONFIG, MPU6050_GYR_SAMPLE); // 2000 + // GYRO_CONFIGĴ + // Ϊ:0x00 Ϊ:250 dps ȡݳ131.2 תΪλݣλΪ/s + // Ϊ:0x08 Ϊ:500 dps ȡݳ65.6 תΪλݣλΪ/s + // Ϊ:0x10 Ϊ:1000dps ȡݳ32.8 תΪλݣλΪ/s + // Ϊ:0x18 Ϊ:2000dps ȡݳ16.4 תΪλݣλΪ/s + + mpu6050_write_register(MPU6050_ACCEL_CONFIG, MPU6050_ACC_SAMPLE); // 8g + // ACCEL_CONFIGĴ + // Ϊ:0x00 ٶȼΪ:2g ȡļٶȼ 16384 תΪλݣλg(m/s^2) + // Ϊ:0x08 ٶȼΪ:4g ȡļٶȼ 8192 תΪλݣλg(m/s^2) + // Ϊ:0x10 ٶȼΪ:8g ȡļٶȼ 4096 תΪλݣλg(m/s^2) + // Ϊ:0x18 ٶȼΪ:16g ȡļٶȼ 2048 תΪλݣλg(m/s^2) + + mpu6050_write_register(MPU6050_USER_CONTROL, 0x00); + mpu6050_write_register(MPU6050_INT_PIN_CFG, 0x02); + }while(0); + return return_state; +} diff --git a/libraries/zf_device/zf_device_mpu6050.h b/libraries/zf_device/zf_device_mpu6050.h new file mode 100644 index 0000000..e2d60d6 --- /dev/null +++ b/libraries/zf_device/zf_device_mpu6050.h @@ -0,0 +1,123 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_mpu6050 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* IIC ͨŶӦϵ +* SCL 鿴 zf_device_mpu6050.h MPU6050_SOFT_IIC_SCL 궨 +* SDA 鿴 zf_device_mpu6050.h MPU6050_SOFT_IIC_SDA 궨 +* Ӳ IIC ͨŶӦϵ +* SCL 鿴 zf_device_mpu6050.h MPU6050_IIC_SCL 궨 +* SDA 鿴 zf_device_mpu6050.h MPU6050_IIC_SDA 궨 +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_mpu6050_h_ +#define _zf_device_mpu6050_h_ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" + +#include "zf_driver_delay.h" + +#include "zf_driver_soft_iic.h" + +#define MPU6050_USE_SOFT_IIC (1) // Ĭʹ IIC ʽ ʹ IIC ʽ +#if MPU6050_USE_SOFT_IIC // ɫIJȷ ɫҵľûõ +//==================================================== IIC ==================================================== +#define MPU6050_SOFT_IIC_DELAY (10 ) // IIC ʱʱ ֵԽС IIC ͨԽ +#define MPU6050_SCL_PIN (B3 ) // IIC SCL MPU6050 SCL +#define MPU6050_SDA_PIN (B5 ) // IIC SDA MPU6050 SDA +//==================================================== IIC ==================================================== +#else +//====================================================Ӳ IIC ==================================================== +#define MPU6050_IIC_SPEED (400000 ) // Ӳ IIC ͨ 400KHz 40KHz +#define MPU6050_IIC (ݲ֧ ) // Ӳ IIC SCL MPU6050 SCL +#define MPU6050_SCL_PIN (ݲ֧ ) // Ӳ IIC SCL MPU6050 SCL +#define MPU6050_SDA_PIN (ݲ֧ ) // Ӳ IIC SDA MPU6050 SDA +//====================================================Ӳ IIC ==================================================== +#endif + +#define MPU6050_TIMEOUT_COUNT (0x00FF) // MPU6050 ʱ + +//================================================ MPU6050 ڲַ================================================ +#define MPU6050_DEV_ADDR (0xD0>>1) // IICдʱĵַֽݣ+1Ϊȡ + +#define MPU6050_SMPLRT_DIV (0x19) // Dzʣֵ0x07(125Hz) +#define MPU6050_CONFIG (0x1A) // ͨ˲Ƶʣֵ0x06(5Hz) +#define MPU6050_GYRO_CONFIG (0x1B) // Լ켰Χֵ0x18(Լ죬2000deg/s) +#define MPU6050_ACCEL_CONFIG (0x1C) // ټԼ졢Χͨ˲Ƶʣֵ0x01(Լ죬2G5Hz) +#define MPU6050_INT_PIN_CFG (0x37) // 6050I2CΪֱͨģʽĴ +#define MPU6050_ACCEL_XOUT_H (0x3B) +#define MPU6050_ACCEL_XOUT_L (0x3C) +#define MPU6050_ACCEL_YOUT_H (0x3D) +#define MPU6050_ACCEL_YOUT_L (0x3E) +#define MPU6050_ACCEL_ZOUT_H (0x3F) +#define MPU6050_ACCEL_ZOUT_L (0x40) +#define MPU6050_GYRO_XOUT_H (0x43) +#define MPU6050_GYRO_XOUT_L (0x44) +#define MPU6050_GYRO_YOUT_H (0x45) +#define MPU6050_GYRO_YOUT_L (0x46) +#define MPU6050_GYRO_ZOUT_H (0x47) +#define MPU6050_GYRO_ZOUT_L (0x48) +#define MPU6050_USER_CONTROL (0x6A) // ر6050ԸI2C豸Ŀ +#define MPU6050_PWR_MGMT_1 (0x6B) // Դֵ0x00() +#define MPU6050_WHO_AM_I (0x75) // IICַĴ(Ĭֵ0x68ֻ) + +#define MPU6050_ACC_SAMPLE (0x10) // ٶȼ +// Ϊ:0x00 Ϊ:250 dps ȡݳ131.2 תΪλݣλΪ/s +// Ϊ:0x08 Ϊ:500 dps ȡݳ65.6 תΪλݣλΪ/s +// Ϊ:0x10 Ϊ:1000dps ȡݳ32.8 תΪλݣλΪ/s +// Ϊ:0x18 Ϊ:2000dps ȡݳ16.4 תΪλݣλΪ/s + +#define MPU6050_GYR_SAMPLE (0x18) // +// Ϊ:0x00 Ϊ:250 dps ȡݳ131.2 תΪλݣλΪ/s +// Ϊ:0x08 Ϊ:500 dps ȡݳ65.6 תΪλݣλΪ/s +// Ϊ:0x10 Ϊ:1000dps ȡݳ32.8 תΪλݣλΪ/s +// Ϊ:0x18 Ϊ:2000dps ȡݳ16.4 תΪλݣλΪ/s + +//================================================ MPU6050 ڲַ================================================ + +extern int16 mpu6050_gyro_x, mpu6050_gyro_y, mpu6050_gyro_z; // gyro () +extern int16 mpu6050_acc_x, mpu6050_acc_y, mpu6050_acc_z; // ٶȼ acc (accelerometer ٶȼ) + +void mpu6050_get_acc (void); +void mpu6050_get_gyro (void); +float mpu6050_acc_transition (int16 acc_value); // MPU6050 ٶȼתΪʵ +float mpu6050_gyro_transition (int16 gyro_value); // MPU6050 תΪʵ +uint8 mpu6050_init (void); + +#endif diff --git a/libraries/zf_device/zf_device_mt9v03x_dvp.c b/libraries/zf_device/zf_device_mt9v03x_dvp.c new file mode 100644 index 0000000..4f2f959 --- /dev/null +++ b/libraries/zf_device/zf_device_mt9v03x_dvp.c @@ -0,0 +1,660 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_mt9v03x +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2021-12-23 W ͷɼɱ־λvolatile +* 2022-03-26 W ޸IJֲҪע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* TXD 鿴 zf_device_mt9v03x_dvp.h MT9V03X_COF_UART_TX 궨 +* RXD 鿴 zf_device_mt9v03x_dvp.h MT9V03X_COF_UART_RX 궨 +* D0 鿴 zf_device_mt9v03x_dvp.h MT9V03X_D0_PIN 궨 +* D1 鿴 zf_device_mt9v03x_dvp.h MT9V03X_D1_PIN 궨 +* D2 鿴 zf_device_mt9v03x_dvp.h MT9V03X_D2_PIN 궨 +* D3 鿴 zf_device_mt9v03x_dvp.h MT9V03X_D3_PIN 궨 +* D4 鿴 zf_device_mt9v03x_dvp.h MT9V03X_D4_PIN 궨 +* D5 鿴 zf_device_mt9v03x_dvp.h MT9V03X_D5_PIN 궨 +* D6 鿴 zf_device_mt9v03x_dvp.h MT9V03X_D6_PIN 궨 +* D7 鿴 zf_device_mt9v03x_dvp.h MT9V03X_D7_PIN 궨 +* PCLK 鿴 zf_device_mt9v03x_dvp.h MT9V03X_PCLK_PIN 궨 +* VSYNC 鿴 zf_device_mt9v03x_dvp.h MT9V03X_VSY_PIN 궨 +* HSYNC 鿴 zf_device_mt9v03x_dvp.h MT9V03X_HERF_PIN 궨 +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_driver_delay.h" +#include "zf_driver_dvp.h" +#include "zf_driver_soft_iic.h" + + +#include "zf_device_camera.h" +#include "zf_device_type.h" +#include "zf_device_mt9v03x_dvp.h" +#include "zf_device_config.h" + +vuint8 mt9v03x_finish_flag = 0; // һͼɼɱ־λ +__attribute__((aligned(4))) uint8 mt9v03x_image[MT9V03X_H][MT9V03X_W]; + +static fifo_struct *camera_receiver_fifo; +static mt9v03x_type_enum mt9v03x_type = MT9V03X_SCCB; +static uint16 mt9v03x_version = 0x00; + +//------------------------------------------------------------------------------------------------------------------- +// ͷڲϢ +// ˵ buff Ϣĵַscc8660_sccb_set_config +// ز uint8 1-ʧ 0-ɹ +// ʹʾ mt9v03x_set_config(mt9v03x_set_confing_buffer); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static uint8 mt9v03x_set_config (const int16 buff[MT9V03X_CONFIG_FINISH][2]) +{ + uint8 uart_buffer[4]; + uint8 return_state = 1; + uint16 temp_value = 0; + uint16 timeout_count = 0; + uint32 loop_count = 0; + uint32 uart_buffer_index = 0; + + switch(mt9v03x_version) + { + case 0x0230: loop_count = MT9V03X_PCLK_MODE; break; + default: loop_count = MT9V03X_GAIN; break; + } + // ò οֲ + // ʼͷ³ʼ + for(; loop_count < MT9V03X_SET_DATA; loop_count --) + { + uart_buffer[0] = 0xA5; + uart_buffer[1] = buff[loop_count][0]; + temp_value = buff[loop_count][1]; + uart_buffer[2] = temp_value >> 8; + uart_buffer[3] = (uint8)temp_value; + uart_write_buffer(MT9V03X_COF_UART, uart_buffer, 4); + + system_delay_ms(2); + } + + do + { + if(3 <= fifo_used(camera_receiver_fifo)) + { + uart_buffer_index = 3; + fifo_read_buffer(camera_receiver_fifo, uart_buffer, &uart_buffer_index, FIFO_READ_AND_CLEAN); + if((0xff == uart_buffer[1]) || (0xff == uart_buffer[2])) + { + return_state = 0; + break; + } + } + system_delay_ms(1); + }while(MT9V03X_INIT_TIMEOUT > timeout_count ++); + // ϲֶͷõȫᱣͷ51Ƭeeprom + // set_exposure_timeõعݲ洢eeprom + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// ȡͷڲϢ +// ˵ buff Ϣĵַ +// ز uint8 1-ʧ 0-ɹ +// ʹʾ mt9v03x_get_config(mt9v03x_get_confing_buffer); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static uint8 mt9v03x_get_config (int16 buff[MT9V03X_CONFIG_FINISH - 1][2]) +{ + int8 loop_count = 0; + uint8 uart_buffer[4]; + uint8 return_state = 0; + uint16 temp_value = 0; + uint16 timeout_count = 0; + uint32 uart_buffer_index = 0; + + switch(mt9v03x_version) + { + case 0x0230: loop_count = MT9V03X_PCLK_MODE; break; + default: loop_count = MT9V03X_GAIN; break; + } + + for(loop_count = loop_count - 1; 0 <= loop_count; loop_count --) + { + if((0x0230 > mt9v03x_version) && (MT9V03X_PCLK_MODE == buff[loop_count][0])) + { + continue; + } + uart_buffer[0] = 0xA5; + uart_buffer[1] = MT9V03X_GET_STATUS; + temp_value = buff[loop_count][0]; + uart_buffer[2] = temp_value >> 8; + uart_buffer[3] = (uint8)temp_value; + uart_write_buffer(MT9V03X_COF_UART, uart_buffer, 4); + + timeout_count = 0; + do + { + if(3 <= fifo_used(camera_receiver_fifo)) + { + uart_buffer_index = 3; + fifo_read_buffer(camera_receiver_fifo, uart_buffer, &uart_buffer_index, FIFO_READ_AND_CLEAN); + buff[loop_count][1] = uart_buffer[1] << 8 | uart_buffer[2]; + break; + } + system_delay_ms(1); + }while(MT9V03X_INIT_TIMEOUT > timeout_count ++); + if(MT9V03X_INIT_TIMEOUT < timeout_count) // ʱ + { + return_state = 1; + break; + } + } + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// MT9V03X UART ȡͷ ID +// ˵ void +// ز uint8 0-ɹ x-ʧ +// ʹʾ mt9v03x_check_id(); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static uint8 mt9v03x_uart_check_id (void) +{ + uint8 uart_buffer[4] = {0}; + uint8 return_state = 1; + uint16 timeout_count = 0; + uint32 uart_buffer_index = 0; + + + if(fifo_used(camera_receiver_fifo)) + { + fifo_clear(camera_receiver_fifo); + } + + uart_write_byte(MT9V03X_COF_UART, 0xFF); + uart_buffer[0] = 0xA5; + uart_buffer[1] = MT9V03X_COLOR_GET_WHO_AM_I; + uart_buffer[2] = 0; + uart_buffer[3] = 0; + uart_write_buffer(MT9V03X_COF_UART, uart_buffer, 4); + + timeout_count = 0; + do + { + if(3 <= fifo_used(camera_receiver_fifo)) + { + uart_buffer_index = 3; + fifo_read_buffer(camera_receiver_fifo, uart_buffer, &uart_buffer_index, FIFO_READ_AND_CLEAN); + return_state = !(0x01 == uart_buffer[2] || 0x02 == uart_buffer[2]); + break; + } + system_delay_ms(1); + }while(MT9V03X_INIT_TIMEOUT > timeout_count ++); + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// MT9V03X ͨŴڻص +// ˵ void +// ز void +// ʹʾ mt9v03x_uart_handler(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +static void mt9v03x_uart_handler (void) +{ + uint8 data = 0; + uart_query_byte(MT9V03X_COF_UART, &data); + if(NULL != camera_receiver_fifo) + { + if(0xA5 == data) + { + fifo_clear(camera_receiver_fifo); + } + + fifo_write_element(camera_receiver_fifo, data); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// MT9V03Xͷж +// ˵ NULL +// ز void +// @since v1.0 +// ʹʾ isr.cȴӦжϺȻøú(֮жϱ־λ) +//------------------------------------------------------------------------------------------------------------------- +void mt9v03x_dvp_handler(void) +{ + //Ѿ޸ΪѭɼģʽҪõַͿDVP + //DVP->DMA_BUF0 = (uint32)camera_buffer_addr; // ָDMAַ + mt9v03x_finish_flag = 1; // ͷɼɱ־λ1 + //Ѿ޸ΪѭɼģʽҪõַͿDVP + //DVP->CR0 |= RB_ENABLE; // ´DVPɼһͼ +} + + + + +//------------------------------------------------------------------------------------------------------------------- +// ȡͷ̼汾 +// ˵ void +// ز uint16 0-ȡ N-汾 +// ʹʾ mt9v03x_get_version(); // øúǰȳʼ +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +uint16 mt9v03x_get_version (void) +{ + uint8 uart_buffer[4]; + uint16 timeout_count = 0; + uint16 return_value = 0; + uint32 uart_buffer_index = 0; + + do + { + uart_buffer[0] = 0xA5; + uart_buffer[1] = MT9V03X_GET_STATUS; + uart_buffer[2] = (uint8)((MT9V03X_GET_VERSION >> 8) & 0xFF); + uart_buffer[3] = (uint8)(MT9V03X_GET_VERSION & 0xFF); + uart_write_buffer(MT9V03X_COF_UART, uart_buffer, 4); + + do + { + if(3 <= fifo_used(camera_receiver_fifo)) + { + uart_buffer_index = 3; + fifo_read_buffer(camera_receiver_fifo, uart_buffer, &uart_buffer_index, FIFO_READ_AND_CLEAN); + return_value = uart_buffer[1] << 8 | uart_buffer[2]; + break; + } + system_delay_ms(1); + }while(MT9V03X_INIT_TIMEOUT > timeout_count ++); + }while(0); + return return_value; +} + +//------------------------------------------------------------------------------------------------------------------- +// ͷعʱ +// ˵ light 趨عʱ +// ز uint8 1-ʧ 0-ɹ +// ʹʾ mt9v03x_set_exposure_time(100); // øúǰȳʼ +// עϢ عʱԽͼԽ +// ͷյݷֱʼFPSعʱõݹ +// ôͷֵ +//------------------------------------------------------------------------------------------------------------------- +uint8 mt9v03x_set_exposure_time (uint16 light) +{ + uint8 uart_buffer[4]; + uint8 *receiver_buffer = NULL; + uint8 return_state = 0; + uint16 temp_value = 0; + uint16 timeout_count = 0; + uint32 uart_buffer_index = 0; + + if(MT9V03X_UART == mt9v03x_type) + { + do + { + receiver_buffer = (uint8 *)malloc(MT9V03X_COF_BUFFER_SIZE); + if(NULL == receiver_buffer) + { + zf_log(0, "FIFO buffer malloc error."); + return_state = 1; + break; + } + camera_receiver_fifo = (fifo_struct *)malloc(sizeof(fifo_struct)); + if(NULL == camera_receiver_fifo) + { + zf_log(0, "FIFO malloc error."); + return_state = 1; + break; + } + fifo_init(camera_receiver_fifo, FIFO_DATA_8BIT, receiver_buffer, MT9V03X_COF_BUFFER_SIZE); + + uart_buffer[0] = 0xA5; + uart_buffer[1] = MT9V03X_SET_EXP_TIME; + temp_value = light; + uart_buffer[2] = temp_value >> 8; + uart_buffer[3] = (uint8)temp_value; + uart_write_buffer(MT9V03X_COF_UART, uart_buffer, 4); + + do + { + if(3 <= fifo_used(camera_receiver_fifo)) + { + uart_buffer_index = 3; + fifo_read_buffer(camera_receiver_fifo, uart_buffer, &uart_buffer_index, FIFO_READ_AND_CLEAN); + temp_value = uart_buffer[1] << 8 | uart_buffer[2]; + break; + } + system_delay_ms(1); + }while(MT9V03X_INIT_TIMEOUT > timeout_count ++); + if((temp_value != light) || (MT9V03X_INIT_TIMEOUT <= timeout_count)) + { + return_state = 1; + } + }while(0); + } + else + { + return_state = mt9v03x_sccb_set_exposure_time(light); + } + + free(receiver_buffer); + free(camera_receiver_fifo); + camera_receiver_fifo = NULL; + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// ͷڲĴд +// ˵ addr ͷڲĴַ +// ˵ data Ҫд +// ز uint8 1-ʧ 0-ɹ +// ʹʾ mt9v03x_set_reg(addr, data); // øúǰȳʼ +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 mt9v03x_set_reg (uint8 addr, uint16 data) +{ + uint8 uart_buffer[4]; + uint8 *receiver_buffer = NULL; + uint8 return_state = 0; + uint16 temp_value = 0; + uint16 timeout_count = 0; + uint32 uart_buffer_index = 0; + + if(MT9V03X_UART == mt9v03x_type) + { + do + { + receiver_buffer = (uint8 *)malloc(MT9V03X_COF_BUFFER_SIZE); + if(NULL == receiver_buffer) + { + zf_log(0, "FIFO buffer malloc error."); + return_state = 1; + break; + } + camera_receiver_fifo = (fifo_struct *)malloc(sizeof(fifo_struct)); + if(NULL == camera_receiver_fifo) + { + zf_log(0, "FIFO malloc error."); + return_state = 1; + break; + } + fifo_init(camera_receiver_fifo, FIFO_DATA_8BIT, receiver_buffer, MT9V03X_COF_BUFFER_SIZE); + + uart_buffer[0] = 0xA5; + uart_buffer[1] = MT9V03X_SET_ADDR; + temp_value = addr; + uart_buffer[2] = temp_value >> 8; + uart_buffer[3] = (uint8)temp_value; + uart_write_buffer(MT9V03X_COF_UART, uart_buffer, 4); + + system_delay_ms(10); + uart_buffer[0] = 0xA5; + uart_buffer[1] = MT9V03X_SET_DATA; + temp_value = data; + uart_buffer[2] = temp_value >> 8; + uart_buffer[3] = (uint8)temp_value; + uart_write_buffer(MT9V03X_COF_UART, uart_buffer, 4); + + do + { + if(3 <= fifo_used(camera_receiver_fifo)) + { + uart_buffer_index = 3; + fifo_read_buffer(camera_receiver_fifo, uart_buffer, &uart_buffer_index, FIFO_READ_AND_CLEAN); + temp_value = uart_buffer[1] << 8 | uart_buffer[2]; + break; + } + system_delay_ms(1); + }while(MT9V03X_INIT_TIMEOUT > timeout_count ++); + if((temp_value != data) || (MT9V03X_INIT_TIMEOUT <= timeout_count)) + { + return_state = 1; + } + }while(0); + } + else + { + return_state = mt9v03x_sccb_set_reg(addr, data); + } + + free(receiver_buffer); + free(camera_receiver_fifo); + camera_receiver_fifo = NULL; + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// MT9V03X SCCB ʼ +// ˵ void +// ز uint8 0-ɹ x-ʧ +// ʹʾ mt9v03x_sccb_init(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 mt9v03x_sccb_init (void) +{ + uint8 return_state = 1; + + mt9v03x_type = MT9V03X_SCCB; + soft_iic_info_struct mt9v03x_iic_struct; + soft_iic_init( + &mt9v03x_iic_struct, 0, + MT9V03X_COF_IIC_DELAY, + MT9V03X_COF_IIC_SCL, + MT9V03X_COF_IIC_SDA); + + if(!mt9v03x_sccb_check_id(&mt9v03x_iic_struct)) + { + // Ҫõͷ ޸IJ + const int16 mt9v03x_set_confing_buffer[MT9V03X_CONFIG_FINISH][2]= + { + {MT9V03X_INIT, 0}, // ͷʼʼ + + {MT9V03X_AUTO_EXP, MT9V03X_AUTO_EXP_DEF}, // Զع + {MT9V03X_EXP_TIME, MT9V03X_EXP_TIME_DEF}, // عʱ + {MT9V03X_FPS, MT9V03X_FPS_DEF}, // ͼ֡ + {MT9V03X_SET_COL, MT9V03X_W}, // ͼ + {MT9V03X_SET_ROW, MT9V03X_H}, // ͼ + {MT9V03X_LR_OFFSET, MT9V03X_LR_OFFSET_DEF}, // ͼƫ + {MT9V03X_UD_OFFSET, MT9V03X_UD_OFFSET_DEF}, // ͼƫ + {MT9V03X_GAIN, MT9V03X_GAIN_DEF}, // ͼ + {MT9V03X_PCLK_MODE, MT9V03X_PCLK_MODE_DEF}, // ʱģʽ + }; + return_state = mt9v03x_sccb_set_config(mt9v03x_set_confing_buffer); + } + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// MT9V03X UART ʼ +// ˵ void +// ز uint8 0-ɹ x-ʧ +// ʹʾ mt9v03x_uart_init(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 mt9v03x_uart_init (void) +{ + uint8 return_state = 1; + uint8 loop_count = 0; + uint8 *receiver_buffer = NULL; + + mt9v03x_type = MT9V03X_UART; + do + { + receiver_buffer = (uint8 *)malloc(MT9V03X_COF_BUFFER_SIZE); // 뻺 + if(NULL == receiver_buffer) // ѿռ䲻 + { + zf_log(0, "FIFO buffer malloc error."); // ޷ȡݻʾ + return_state = 2; // 쳣 + break; + } + camera_receiver_fifo = (fifo_struct *)malloc(sizeof(fifo_struct)); // FIFO + if(NULL == camera_receiver_fifo) // ѿռ䲻 + { + zf_log(0, "FIFO malloc error."); // ޷ȡ FIFO ʾ + free(receiver_buffer); + return_state = 2; // 쳣 + break; + } + fifo_init(camera_receiver_fifo, FIFO_DATA_8BIT, receiver_buffer, MT9V03X_COF_BUFFER_SIZE); + + + + // ʼ ͷ + uart_init(MT9V03X_COF_UART, MT9V03X_COF_BAUR, MT9V03X_COF_UART_RX, MT9V03X_COF_UART_TX); + uart_rx_interrupt(MT9V03X_COF_UART, 1); + + mt9v03x_version = mt9v03x_get_version(); + + if(mt9v03x_version != 0) + { + if(mt9v03x_uart_check_id()) + { + uart_rx_interrupt(MT9V03X_COF_UART, 0); + return_state = 3; + break; + } + } + + + // Ҫõͷ ޸IJ + const int16 mt9v03x_set_confing_buffer[MT9V03X_CONFIG_FINISH][2]= + { + {MT9V03X_INIT, 0}, // ͷʼʼ + + {MT9V03X_AUTO_EXP, MT9V03X_AUTO_EXP_DEF}, // Զع + {MT9V03X_EXP_TIME, MT9V03X_EXP_TIME_DEF}, // عʱ + {MT9V03X_FPS, MT9V03X_FPS_DEF}, // ͼ֡ + {MT9V03X_SET_COL, MT9V03X_W}, // ͼ + {MT9V03X_SET_ROW, MT9V03X_H}, // ͼ + {MT9V03X_LR_OFFSET, MT9V03X_LR_OFFSET_DEF}, // ͼƫ + {MT9V03X_UD_OFFSET, MT9V03X_UD_OFFSET_DEF}, // ͼƫ + {MT9V03X_GAIN, MT9V03X_GAIN_DEF}, // ͼ + {MT9V03X_PCLK_MODE, MT9V03X_PCLK_MODE_DEF}, // ʱģʽ + }; + + // ͷڲȡ ޸IJ + int16 mt9v03x_get_confing_buffer[MT9V03X_CONFIG_FINISH - 1][2]= + { + {MT9V03X_AUTO_EXP, 0}, // Զع + {MT9V03X_EXP_TIME, 0}, // عʱ + {MT9V03X_FPS, 0}, // ͼ֡ + {MT9V03X_SET_COL, 0}, // ͼ + {MT9V03X_SET_ROW, 0}, // ͼ + {MT9V03X_LR_OFFSET, 0}, // ͼƫ + {MT9V03X_UD_OFFSET, 0}, // ͼƫ + {MT9V03X_GAIN, 0}, // ͼ + {MT9V03X_PCLK_MODE, 0}, // ʱģʽ PCLKģʽ < MT9V034 V1.5 Լϰ汾ָ֧ > + }; + + if(mt9v03x_set_config(mt9v03x_set_confing_buffer)) // + { + // ˶Ϣ ʾλ + // ôǴͨųʱ˳ + // һ½û ûܾǻ + zf_log(0, "MT9V03X set config error."); + uart_rx_interrupt(MT9V03X_COF_UART, 0); + return_state = 1; + break; + } + + // ȡñڲ鿴Ƿȷ + if(mt9v03x_get_config(mt9v03x_get_confing_buffer)) + { + // ˶Ϣ ʾλ + // ôǴͨųʱ˳ + // һ½û ûܾǻ + zf_log(0, "MT9V03X get config error."); + uart_rx_interrupt(MT9V03X_COF_UART, 0); + return_state = 1; + break; + } + + for(loop_count = 0; MT9V03X_CONFIG_FINISH - 1 > loop_count; loop_count ++) + { + if( mt9v03x_set_confing_buffer[loop_count + 1][0] != mt9v03x_get_confing_buffer[loop_count][0] || + mt9v03x_set_confing_buffer[loop_count + 1][1] != mt9v03x_get_confing_buffer[loop_count][1]) + { + break; + } + } + return_state = (MT9V03X_CONFIG_FINISH - 2 <= loop_count) ? 0 : 1; + }while(0); + + free(receiver_buffer); + free(camera_receiver_fifo); + camera_receiver_fifo = NULL; + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// MT9V03X ͷʼ +// ˵ void +// ز uint8 0-ɹ x-ʧ +// ʹʾ mt9v03x_init(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 mt9v03x_init (void) +{ + + uint8 return_state = 0; + + do + { + set_camera_type(CAMERA_GRAYSCALE, NULL, mt9v03x_dvp_handler); + if(mt9v03x_sccb_init()) + { + set_camera_type(CAMERA_GRAYSCALE, mt9v03x_uart_handler, mt9v03x_dvp_handler); + return_state = mt9v03x_uart_init(); + } + + if(!return_state) + { + // DVPųʼ + dvp_gpio_init( + MT9V03X_D0_PIN, MT9V03X_D1_PIN, MT9V03X_D2_PIN, MT9V03X_D3_PIN, + MT9V03X_D4_PIN, MT9V03X_D5_PIN, MT9V03X_D6_PIN, MT9V03X_D7_PIN, + MT9V03X_PCLK_PIN, MT9V03X_VSY_PIN, MT9V03X_HERF_PIN); + + // DVPӿڳʼ + dvp_camera_init((uint32 *)&mt9v03x_image[0], (uint32 *)&mt9v03x_image[0], MT9V03X_W*MT9V03X_H, MT9V03X_H); + break; + } + set_camera_type(NO_CAMERE, NULL, NULL); + }while(0); + + return return_state; +} diff --git a/libraries/zf_device/zf_device_mt9v03x_dvp.h b/libraries/zf_device/zf_device_mt9v03x_dvp.h new file mode 100644 index 0000000..2fbe060 --- /dev/null +++ b/libraries/zf_device/zf_device_mt9v03x_dvp.h @@ -0,0 +1,154 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_mt9v03x +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2021-12-23 W ͷɼɱ־λvolatile +* 2022-03-26 W ޸IJֲҪע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* TXD 鿴 zf_device_mt9v03x.h MT9V03X_COF_UART_TX 궨 +* RXD 鿴 zf_device_mt9v03x.h MT9V03X_COF_UART_RX 궨 +* D0 鿴 zf_device_mt9v03x.h MT9V03X_D0_PIN 궨 +* D1 鿴 zf_device_mt9v03x.h MT9V03X_D1_PIN 궨 +* D2 鿴 zf_device_mt9v03x.h MT9V03X_D2_PIN 궨 +* D3 鿴 zf_device_mt9v03x.h MT9V03X_D3_PIN 궨 +* D4 鿴 zf_device_mt9v03x.h MT9V03X_D4_PIN 궨 +* D5 鿴 zf_device_mt9v03x.h MT9V03X_D5_PIN 궨 +* D6 鿴 zf_device_mt9v03x.h MT9V03X_D6_PIN 궨 +* D7 鿴 zf_device_mt9v03x.h MT9V03X_D7_PIN 궨 +* PCLK 鿴 zf_device_mt9v03x.h MT9V03X_PCLK_PIN 궨 +* VSYNC 鿴 zf_device_mt9v03x.h MT9V03X_VSY_PIN 궨 +* HSYNC 鿴 zf_device_mt9v03x.h MT9V03X_HERF_PIN 궨 +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_mt9v03x_h_ +#define _zf_device_mt9v03x_h_ + + +#include "zf_common_typedef.h" + + +//-------------------------------------------------------------------------------------------------- +// +//-------------------------------------------------------------------------------------------------- +#define MT9V03X_COF_UART (UART_5 ) // ͷʹõĴ +#define MT9V03X_COF_BAUR (9600 ) // ôڲ +#define MT9V03X_COF_UART_TX (UART5_MAP0_RX_D2) // UART-TX ҪڵƬ RX +#define MT9V03X_COF_UART_RX (UART5_MAP0_TX_C12) // UART-RX ҪڵƬ TX + +#define MT9V03X_COF_IIC_DELAY (500) // IIC ʱ +#define MT9V03X_COF_IIC_SCL (D2 ) // IIC-SCL +#define MT9V03X_COF_IIC_SDA (C12) // IIC-SDA + +#define MT9V03X_D0_PIN (A9 ) +#define MT9V03X_D1_PIN (A10) +#define MT9V03X_D2_PIN (C8 ) +#define MT9V03X_D3_PIN (C9 ) +#define MT9V03X_D4_PIN (C11) +#define MT9V03X_D5_PIN (B6 ) +#define MT9V03X_D6_PIN (B8 ) +#define MT9V03X_D7_PIN (B9 ) + +#define MT9V03X_PCLK_PIN (A6 ) +#define MT9V03X_VSY_PIN (A5 ) +#define MT9V03X_HERF_PIN (A4 ) +#define MT9V03X_INIT_TIMEOUT (200) // Ĭϵͷʼʱʱ Ϊλ + +//-------------------------------------------------------------------------------------------------- +// ͷĬϲ ڴ޸ͷ +//-------------------------------------------------------------------------------------------------- +#define MT9V03X_W (188) // ͼ Χ [1-752] +#define MT9V03X_H (120) // ͼ߶ Χ [1-480] +#define MT9V03X_IMAGE_SIZE ( MT9V03X_W * MT9V03X_H ) // ͼСܳ 65535 +#define MT9V03X_COF_BUFFER_SIZE ( 64 ) // ôڻС 64 + +#define MT9V03X_AUTO_EXP_DEF (0 ) // Զع ĬϲԶع Χ [0-63] 0Ϊر + // Զع⿪ EXP_TIMEԶعʱ + // һDzҪԶع ߷dzȵԳԶع⣬ͼȶ +#define MT9V03X_EXP_TIME_DEF (512) // عʱ ͷյԶعʱ䣬ùΪعֵ +#define MT9V03X_FPS_DEF (50 ) // ͼ֡ ͷյԶFPSΪFPS +#define MT9V03X_LR_OFFSET_DEF (0 ) // ͼƫ ֵ ƫ ֵ ƫ Ϊ188 376 752ʱ޷ƫ + // ͷƫݺԶƫƣüƫ +#define MT9V03X_UD_OFFSET_DEF (0 ) // ͼƫ ֵ ƫ ֵ ƫ Ϊ120 240 480ʱ޷ƫ + // ͷƫݺԶƫƣüƫ +#define MT9V03X_GAIN_DEF (32 ) // ͼ Χ [16-64] عʱ̶¸ıͼ̶ +#define MT9V03X_PCLK_MODE_DEF (1 ) // ʱģʽ Χ [0-1] Ĭϣ0 ѡΪ[0ź,1ź] + // ͨΪ0ʹCH32V307DVPӿڻSTM32DCMIӿڲɼҪΪ1 + // MT9V034 V1.5 Լϰ汾ָ֧ + +// ͷö +typedef enum +{ + MT9V03X_INIT = 0, // ͷʼ + MT9V03X_AUTO_EXP, // Զع + MT9V03X_EXP_TIME, // عʱ + MT9V03X_FPS, // ͷ֡ + MT9V03X_SET_COL, // ͼ + MT9V03X_SET_ROW, // ͼ + MT9V03X_LR_OFFSET, // ͼƫ + MT9V03X_UD_OFFSET, // ͼƫ + MT9V03X_GAIN, // ͼƫ + MT9V03X_PCLK_MODE, // ʱģʽ(MT9V034 V1.5Լϰ汾ָ֧) + MT9V03X_CONFIG_FINISH, // λҪռλ + + MT9V03X_COLOR_GET_WHO_AM_I = 0xEF, + MT9V03X_SET_EXP_TIME = 0XF0, // عʱ + MT9V03X_GET_STATUS, // ȡͷ + MT9V03X_GET_VERSION, // ̼汾 + + MT9V03X_SET_ADDR = 0XFE, // Ĵַ + MT9V03X_SET_DATA // Ĵ +}m9v03x_cmd_enum; + + +// ͷӿö +typedef enum +{ + MT9V03X_UART, + MT9V03X_SCCB, +}mt9v03x_type_enum; + +extern volatile vuint8 mt9v03x_finish_flag;//һͼɼɱ־λ +extern uint8 mt9v03x_image[MT9V03X_H][MT9V03X_W]; + +void mt9v03x_uart_callback (void); +void mt9v03x_handler (void); +uint16 mt9v03x_get_version (void); +uint8 mt9v03x_set_exposure_time (uint16 light); +uint8 mt9v03x_set_reg (uint8 addr, uint16 data); +uint8 mt9v03x_init (void); + +#endif diff --git a/libraries/zf_device/zf_device_oled.c b/libraries/zf_device/zf_device_oled.c new file mode 100644 index 0000000..3d92a9b --- /dev/null +++ b/libraries/zf_device/zf_device_oled.c @@ -0,0 +1,765 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_oled +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* D0 查看 zf_device_oled.h 中 OLED_D0_PIN 宏定义 +* D1 查看 zf_device_oled.h 中 OLED_D1_PIN 宏定义 +* RES 查看 zf_device_oled.h 中 OLED_RES_PIN 宏定义 +* DC 查看 zf_device_oled.h 中 OLED_DC_PIN 宏定义 +* CS 查看 zf_device_oled.h 中 OLED_CS_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_common_font.h" +#include "zf_common_function.h" +#include "zf_driver_delay.h" +#include "zf_driver_soft_spi.h" +#include "zf_driver_spi.h" + +#include "zf_device_oled.h" + +#if OLED_USE_SOFT_SPI +static soft_spi_info_struct oled_spi; +#define oled_spi_write_8bit(data) (soft_spi_write_8bit(&oled_spi, (data))) +#else +#define oled_spi_write_8bit(data) (spi_write_8bit(OLED_SPI, (data))) +#endif + +static oled_dir_enum oled_display_dir = OLED_DEFAULT_DISPLAY_DIR; +static oled_font_size_enum oled_display_font = OLED_DEFAULT_DISPLAY_FONT; + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 写8位数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 oled_write_data(color); +// 备注信息 内部调用 用户无需关心 +//------------------------------------------------------------------------------------------------------------------- +static void oled_write_data (const uint8 data) +{ + OLED_DC(1); + oled_spi_write_8bit(data); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 写命令 +// 参数说明 cmd 命令 +// 返回参数 void +// 使用示例 oled_write_command(0xb0 + y); +// 备注信息 内部调用 用户无需关心 +//------------------------------------------------------------------------------------------------------------------- +static void oled_write_command (const uint8 command) +{ + OLED_DC(0); + oled_spi_write_8bit(command); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED显示坐标设置 +// 参数说明 x x轴坐标设置0-127 +// 参数说明 y y轴坐标设置0-7 +// 返回参数 void +// 使用示例 oled_set_coordinate(x, y); +// 备注信息 内部使用用户无需关心 +//------------------------------------------------------------------------------------------------------------------- +static void oled_set_coordinate (uint8 x, uint8 y) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + // 检查一下你的显示调用的函数 自己计算一下哪里超过了屏幕显示范围 + zf_assert(128 > x); + zf_assert(8 > y); + + oled_write_command(0xb0 + y); + oled_write_command(((x & 0xf0) >> 4) | 0x10); + oled_write_command((x & 0x0f) | 0x00); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED显示DEBUG信息初始化 +// 参数说明 void +// 返回参数 void +// 使用示例 oled_debug_init(); +// 备注信息 内部使用用户无需关心 +//------------------------------------------------------------------------------------------------------------------- +static void oled_debug_init (void) +{ + debug_output_struct info; + debug_output_struct_init(&info); + + info.type_index = 1; + + info.display_x_max = OLED_X_MAX; + info.display_y_max = OLED_Y_MAX; + switch(oled_display_font) + { + case OLED_6X8_FONT: + { + info.font_x_size = 6; + info.font_y_size = 1; + }break; + case OLED_8X16_FONT: + { + info.font_x_size = 8; + info.font_y_size = 2; + }break; + case OLED_16X16_FONT: + { + // 暂不支持 + }break; + } + info.output_screen = oled_show_string; + info.output_screen_clear = oled_clear; + + debug_output_init(&info); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED 清屏函数 +// 参数说明 void +// 返回参数 void +// 使用示例 oled_clear(); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void oled_clear (void) +{ + uint8 y = 0, x = 0; + + OLED_CS(0); + for(y = 0; 8 > y; y ++) + { + oled_write_command(0xb0 + y); + oled_write_command(0x01); + oled_write_command(0x10); + for(x = 0; OLED_X_MAX > x; x ++) + { + oled_write_data(0x00); + } + } + OLED_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED 屏幕填充函数 +// 参数说明 color 填充颜色选着(0x00 or 0xff) +// 返回参数 void +// 使用示例 oled_full(0x00); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void oled_full (const uint8 color) +{ + uint8 y = 0, x = 0; + + OLED_CS(0); + for(y = 0; 8 > y; y ++) + { + oled_write_command(0xb0 + y); + oled_write_command(0x01); + oled_write_command(0x10); + for(x = 0; OLED_X_MAX > x; x ++) + { + oled_write_data(color); + } + } + OLED_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示方向 +// 参数说明 dir 显示方向 参照 zf_device_oled.h 内 oled_dir_enum 枚举体定义 +// 返回参数 void +// 使用示例 oled_set_dir(OLED_CROSSWISE); +// 备注信息 这个函数只有在初始化屏幕之前调用才生效 +//------------------------------------------------------------------------------------------------------------------- +void oled_set_dir (oled_dir_enum dir) +{ + oled_display_dir = dir; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示字体 +// 参数说明 dir 显示方向 参照 zf_device_oled.h 内 oled_font_size_enum 枚举体定义 +// 返回参数 void +// 使用示例 oled_set_font(OLED_8x16_FONT); +// 备注信息 字体可以随时自由设置 设置后生效 后续显示就是新的字体大小 +//------------------------------------------------------------------------------------------------------------------- +void oled_set_font (oled_font_size_enum font) +{ + oled_display_font = font; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 画点函数 +// 参数说明 x x 轴坐标设置 0-127 +// 参数说明 y y 轴坐标设置 0-7 +// 参数说明 color 8 个点数据 +// 返回参数 void +// 使用示例 oled_draw_point(0, 0, 1); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void oled_draw_point (uint16 x, uint16 y, const uint8 color) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + // 检查一下你的显示调用的函数 自己计算一下哪里超过了屏幕显示范围 + zf_assert(128 > x); + zf_assert(8 > y); + + OLED_CS(0); + oled_set_coordinate(x, y); + oled_write_command(0xb0 + y); + oled_write_command(((x & 0xf0) >> 4) | 0x10); + oled_write_command((x & 0x0f) | 0x00); + oled_write_data(color); + OLED_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED 显示字符串 +// 参数说明 x x 轴坐标设置 0-127 +// 参数说明 y y 轴坐标设置 0-7 +// 参数说明 ch[] 字符串 +// 返回参数 void +// 使用示例 oled_show_string(0, 0, "SEEKFREE"); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void oled_show_string (uint16 x, uint16 y, const char ch[]) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + // 检查一下你的显示调用的函数 自己计算一下哪里超过了屏幕显示范围 + zf_assert(128 > x); + zf_assert(8 > y); + + OLED_CS(0); + uint8 c = 0, i = 0, j = 0; + while ('\0' != ch[j]) + { + switch(oled_display_font) + { + case OLED_6X8_FONT: + { + c = ch[j] - 32; + if(x > 126) + { + x = 0; + y ++; + } + oled_set_coordinate(x, y); + for(i = 0; 6 > i; i ++) + { + oled_write_data(ascii_font_6x8[c][i]); + } + x += 6; + j ++; + }break; + case OLED_8X16_FONT: + { + c = ch[j] - 32; + if(x > 120) + { + x = 0; + y ++; + } + oled_set_coordinate(x, y); + for(i = 0; i < 8; i ++) + { + oled_write_data(ascii_font_8x16[c][i]); + } + + oled_set_coordinate(x, y + 1); + for(i = 0; i < 8; i ++) + { + oled_write_data(ascii_font_8x16[c][i + 8]); + } + x += 8; + j ++; + }break; + case OLED_16X16_FONT: + { + // 暂不支持 + }break; + } + } + OLED_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED 显示32位有符号 (去除整数部分无效的0) +// 参数说明 x x轴坐标设置 0-127 +// 参数说明 y y轴坐标设置 0-7 +// 参数说明 dat 需要显示的变量 数据类型 int32 +// 参数说明 num 需要显示的位数 最高10位 不包含正负号 +// 返回参数 void +// 使用示例 oled_show_int(0, 0, x, 3); // x 可以为 int32 int16 int8 类型 +// 备注信息 负数会显示一个 ‘-’号 +//------------------------------------------------------------------------------------------------------------------- +void oled_show_int (uint16 x, uint16 y, const int32 dat, uint8 num) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + // 检查一下你的显示调用的函数 自己计算一下哪里超过了屏幕显示范围 + zf_assert(128 > x); + zf_assert(8 > y); + + zf_assert(0 < num); + zf_assert(10 >= num); + + int32 dat_temp = dat; + int32 offset = 1; + char data_buffer[12]; + + memset(data_buffer, 0, 12); + memset(data_buffer, ' ', num + 1); + + // 用来计算余数显示 123 显示 2 位则应该显示 23 + if(10 > num) + { + for(; 0 < num; num --) + { + offset *= 10; + } + dat_temp %= offset; + } + func_int_to_str(data_buffer, dat_temp); + oled_show_string(x, y, (const char *)&data_buffer); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED 显示32位无符号 (去除整数部分无效的0) +// 参数说明 x x 轴坐标设置 0-127 +// 参数说明 y y 轴坐标设置 0-7 +// 参数说明 dat 需要显示的变量 数据类型 uint32 +// 参数说明 num 需要显示的位数 最高10位 不包含正负号 +// 返回参数 void +// 使用示例 oled_show_uint(0, 0, x, 3); // x 可以为 uint32 uint16 uint8 类型 +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void oled_show_uint (uint16 x,uint16 y,const uint32 dat,uint8 num) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + // 检查一下你的显示调用的函数 自己计算一下哪里超过了屏幕显示范围 + zf_assert(128 > x); + zf_assert(8 > y); + + zf_assert(0 < num); + zf_assert(10 >= num); + + uint32 dat_temp = dat; + int32 offset = 1; + char data_buffer[12]; + memset(data_buffer, 0, 12); + memset(data_buffer, ' ', num); + + // 用来计算余数显示 123 显示 2 位则应该显示 23 + if(10 > num) + { + for(; 0 < num; num --) + { + offset *= 10; + } + dat_temp %= offset; + } + func_uint_to_str(data_buffer, dat_temp); + oled_show_string(x, y, (const char *)&data_buffer); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED 显示浮点数 (去除整数部分无效的0) +// 参数说明 x x 轴坐标设置 0-127 +// 参数说明 y y 轴坐标设置 0-7 +// 参数说明 dat 需要显示的变量 数据类型 float +// 参数说明 num 整数位显示长度 最高8位 +// 参数说明 pointnum 小数位显示长度 最高6位 +// 返回参数 void +// 使用示例 oled_show_float(0, 0, x, 2, 3); // 显示浮点数 整数显示2位 小数显示三位 +// 备注信息 特别注意当发现小数部分显示的值与你写入的值不一样的时候， +// 可能是由于浮点数精度丢失问题导致的，这并不是显示函数的问题， +// 有关问题的详情，请自行百度学习 浮点数精度丢失问题。 +// 负数会显示一个 ‘-’号 +//------------------------------------------------------------------------------------------------------------------- +void oled_show_float (uint16 x,uint16 y,const double dat,uint8 num,uint8 pointnum) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + // 检查一下你的显示调用的函数 自己计算一下哪里超过了屏幕显示范围 + zf_assert(128 > x); + zf_assert(8 > y); + + zf_assert(0 < num); + zf_assert(8 >= num); + zf_assert(0 < pointnum); + zf_assert(6 >= pointnum); + + double dat_temp = dat; + double offset = 1.0; + char data_buffer[17]; + memset(data_buffer, 0, 17); + memset(data_buffer, ' ', num + pointnum + 2); + + // 用来计算余数显示 123 显示 2 位则应该显示 23 + for(; 0 < num; num --) + { + offset *= 10; + } + dat_temp = dat_temp - ((int)dat_temp / (int)offset) * offset; + func_double_to_str(data_buffer, dat_temp, pointnum); + oled_show_string(x, y, data_buffer); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED 显示二值图像 数据每八个点组成一个字节数据 +// 参数说明 x x 轴坐标设置 0-127 +// 参数说明 y y 轴坐标设置 0-7 +// 参数说明 *image 图像数组指针 +// 参数说明 width 图像实际宽度 +// 参数说明 height 图像实际高度 +// 参数说明 dis_width 图像显示宽度 参数范围 [0, 128] +// 参数说明 dis_height 图像显示高度 参数范围 [0, 64] +// 返回参数 void +// 使用示例 oled_show_binary_image(0, 0, ov7725_image_binary[0], OV7725_W, OV7725_H, OV7725_W, OV7725_H); +// 备注信息 用于显示小钻风的未解压的压缩二值化图像 +// 这个函数不可以用来直接显示总钻风的未压缩的二值化图像 +// 这个函数不可以用来直接显示总钻风的未压缩的二值化图像 +// 这个函数不可以用来直接显示总钻风的未压缩的二值化图像 +//------------------------------------------------------------------------------------------------------------------- +void oled_show_binary_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + // 检查一下你的显示调用的函数 自己计算一下哪里超过了屏幕显示范围 + zf_assert(128 > x); + zf_assert(8 > y); + zf_assert(NULL != image); + + uint32 i = 0, j = 0, z = 0; + uint8 dat = 0; + uint32 width_index = 0, height_index = 0; + + OLED_CS(0); + dis_height = dis_height - dis_height % 8; + dis_width = dis_width - dis_width % 8; + for(j = 0; j < dis_height; j += 8) + { + oled_set_coordinate(x + 0, y + j / 8); + height_index = j * height / dis_height; + for(i = 0; i < dis_width; i += 8) + { + width_index = i * width / dis_width / 8; + for(z = 0; 8 > z; z ++) + { + dat = 0; + if(*(image + height_index * width / 8 + width_index + width / 8 * 0) & (0x80 >> z)) + { + dat |= 0x01; + } + if(*(image + height_index * width / 8 + width_index + width / 8 * 1) & (0x80 >> z)) + { + dat |= 0x02; + } + if(*(image + height_index * width / 8 + width_index + width / 8 * 2) & (0x80 >> z)) + { + dat |= 0x04; + } + if(*(image + height_index * width / 8 + width_index + width / 8 * 3) & (0x80 >> z)) + { + dat |= 0x08; + } + if(*(image + height_index * width / 8 + width_index + width / 8 * 4) & (0x80 >> z)) + { + dat |= 0x10; + } + if(*(image + height_index * width / 8 + width_index + width / 8 * 5) & (0x80 >> z)) + { + dat |= 0x20; + } + if(*(image + height_index * width / 8 + width_index + width / 8 * 6) & (0x80 >> z)) + { + dat |= 0x40; + } + if(*(image + height_index * width / 8 + width_index + width / 8 * 7) & (0x80 >> z)) + { + dat |= 0x80; + } + oled_write_data(dat); + } + } + } + OLED_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED 显示 8bit 灰度图像 带二值化阈值 +// 参数说明 x x 轴坐标设置 0-127 +// 参数说明 y y 轴坐标设置 0-7 +// 参数说明 *image 图像数组指针 +// 参数说明 width 图像实际宽度 +// 参数说明 height 图像实际高度 +// 参数说明 dis_width 图像显示宽度 参数范围 [0, 128] +// 参数说明 dis_height 图像显示高度 参数范围 [0, 64] +// 参数说明 threshold 二值化显示阈值 0-不开启二值化 +// 返回参数 void +// 使用示例 oled_show_gray_image(0, 0, mt9v03x_image[0], width, height, 128, 64, x); +// 备注信息 用于显示总钻风的图像 +// 如果要显示二值化图像 直接修改最后一个参数为需要的二值化阈值即可 +// 如果要显示二值化图像 直接修改最后一个参数为需要的二值化阈值即可 +// 如果要显示二值化图像 直接修改最后一个参数为需要的二值化阈值即可 +//------------------------------------------------------------------------------------------------------------------- +void oled_show_gray_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 threshold) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + // 检查一下你的显示调用的函数 自己计算一下哪里超过了屏幕显示范围 + zf_assert(128 > x); + zf_assert(8 > y); + zf_assert(NULL != image); + + int16 i = 0, j = 0; + uint8 dat = 0; + uint32 width_index = 0, height_index = 0; + + OLED_CS(0); + dis_height = dis_height - dis_height % 8; + for(j = 0; j < dis_height; j += 8) + { + oled_set_coordinate(x + 0, y + j / 8); + height_index = j * height / dis_height; + for(i = 0; i < dis_width; i ++) + { + width_index = i * width / dis_width; + dat = 0; + if(*(image + height_index * width + width_index + width * 0) > threshold) + { + dat |= 0x01; + } + if(*(image + height_index * width + width_index + width * 1) > threshold) + { + dat |= 0x02; + } + if(*(image + height_index * width + width_index + width * 2) > threshold) + { + dat |= 0x04; + } + if(*(image + height_index * width + width_index + width * 3) > threshold) + { + dat |= 0x08; + } + if(*(image + height_index * width + width_index + width * 4) > threshold) + { + dat |= 0x10; + } + if(*(image + height_index * width + width_index + width * 5) > threshold) + { + dat |= 0x20; + } + if(*(image + height_index * width + width_index + width * 6) > threshold) + { + dat |= 0x40; + } + if(*(image + height_index * width + width_index + width * 7) > threshold) + { + dat |= 0x80; + } + oled_write_data(dat); + } + } + OLED_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED 显示波形 +// 参数说明 x x 轴坐标设置 0-127 +// 参数说明 y y 轴坐标设置 0-7 +// 参数说明 *wave 波形数组指针 +// 参数说明 width 波形实际宽度 +// 参数说明 value_max 波形实际最大值 +// 参数说明 dis_width 波形显示宽度 参数范围 [0, 128] +// 参数说明 dis_value_max 波形显示最大值 参数范围 [0, 64] +// 返回参数 void +// 使用示例 oled_show_wave(0, 0, data, 128, 64, 128, 64); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void oled_show_wave (uint16 x, uint16 y, const uint16 *wave, uint16 width, uint16 value_max, uint16 dis_width, uint16 dis_value_max) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + // 检查一下你的显示调用的函数 自己计算一下哪里超过了屏幕显示范围 + zf_assert(128 > x); + zf_assert(8 > y); + zf_assert(NULL != wave); + + uint32 i = 0; + uint32 width_index = 0, value_max_index = 0; + uint8 dis_h = 0; + + uint32 x_temp = 0; + uint32 y_temp = 0; + + OLED_CS(0); + for(y_temp = 0; y_temp < dis_value_max; y_temp += 8) + { + oled_set_coordinate(x + 0, y + y_temp / 8); + for(x_temp = 0; x_temp < dis_width; x_temp ++) + { + oled_write_data(0x00); + } + } + for(i = 0; i < dis_width; i ++) + { + width_index = i * width / dis_width; + value_max_index = *(wave + width_index) * (dis_value_max - 1) / value_max; + + dis_h = (dis_value_max - 1) - value_max_index; + oled_set_coordinate(i + x, dis_h / 8 + y); + dis_h = (0x01 << dis_h % 8); + oled_write_data(dis_h); + } + OLED_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 汉字显示 +// 参数说明 x 横坐标 0-127 +// 参数说明 y 纵坐标 0-7 +// 参数说明 size 取模的时候设置的汉字字体大小，也就是一个汉字占用的点阵长宽为多少个点，取模的时候需要长宽是一样的。 +// 参数说明 *chinese_buffer 需要显示的汉字数组 +// 参数说明 number 需要显示多少位 +// 返回参数 void +// 使用示例 oled_show_chinese(0, 6, 16, (const uint8 *)oled_16x16_chinese, 4); +// 备注信息 使用PCtoLCD2002软件取模 阴码、逐行式、顺向 16*16 +//------------------------------------------------------------------------------------------------------------------- +void oled_show_chinese (uint16 x, uint16 y, uint8 size, const uint8 *chinese_buffer, uint8 number) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + // 检查一下你的显示调用的函数 自己计算一下哪里超过了屏幕显示范围 + zf_assert(128 > x); + zf_assert(8 > y); + zf_assert(NULL != chinese_buffer); + + int16 i = 0, j = 0, k = 0; + + OLED_CS(0); + for(i = 0; i < number; i ++) + { + for(j = 0; j < (size / 8); j ++) + { + oled_set_coordinate(x + i * size, y + j); + for(k = 0; 16 > k; k ++) + { + oled_write_data(*chinese_buffer); + chinese_buffer ++; + } + } + } + OLED_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED初始化函数 +// 参数说明 void +// 返回参数 void +// 使用示例 oled_init(); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void oled_init (void) +{ +#if OLED_USE_SOFT_SPI + soft_spi_init(&oled_spi, 0, OLED_SOFT_SPI_DELAY, OLED_D0_PIN, OLED_D1_PIN, SOFT_SPI_PIN_NULL, SOFT_SPI_PIN_NULL); +#else + spi_init(OLED_SPI, SPI_MODE0, OLED_SPI_SPEED, OLED_D0_PIN, OLED_D1_PIN, SPI_MISO_NULL, SPI_CS_NULL); +#endif + gpio_init(OLED_RES_PIN, GPO, GPIO_HIGH, GPO_PUSH_PULL); + gpio_init(OLED_DC_PIN , GPO, GPIO_HIGH, GPO_PUSH_PULL); + gpio_init(OLED_CS_PIN , GPO, GPIO_HIGH, GPO_PUSH_PULL); + + oled_set_dir(oled_display_dir); + + OLED_CS(0); + OLED_RES(0); + system_delay_ms(50); + OLED_RES(1); + + oled_write_command(0xae); // --turn off oled panel + oled_write_command(0x00); // ---set low column address + oled_write_command(0x10); // ---set high column address + oled_write_command(0x40); // --set start line address Set Mapping RAM Display Start Line (0x00~0x3F) + oled_write_command(0x81); // --set contrast control register + oled_write_command(OLED_BRIGHTNESS); // Set SEG Output Current Brightness + + if(OLED_CROSSWISE == oled_display_dir) + { + oled_write_command(0xa1); // --Set SEG/Column Mapping 0xa0左右反置 0xa1正常 + oled_write_command(0xc8); // Set COM/Row Scan Direction 0xc0上下反置 0xc8正常 + } + else + { + oled_write_command(0xa0); // --Set SEG/Column Mapping 0xa0左右反置 0xa1正常 + oled_write_command(0xc0); // Set COM/Row Scan Direction 0xc0上下反置 0xc8正常 + } + + oled_write_command(0xa6); // --set normal display + oled_write_command(0xa8); // --set multiplex ratio(1 to 64) + oled_write_command(0x3f); // --1/64 duty + oled_write_command(0xd3); // -set display offset Shift Mapping RAM Counter (0x00~0x3F) + oled_write_command(0x00); // -not offset + oled_write_command(0xd5); // --set display clock divide ratio/oscillator frequency + oled_write_command(0x80); // --set divide ratio, Set Clock as 100 Frames/Sec + oled_write_command(0xd9); // --set pre-charge period + oled_write_command(0xf1); // Set Pre-Charge as 15 Clocks & Discharge as 1 Clock + oled_write_command(0xda); // --set com pins hardware configuration + oled_write_command(0x12); + oled_write_command(0xdb); // --set vcomh + oled_write_command(0x40); // Set VCOM Deselect Level + oled_write_command(0x20); // -Set Page Addressing Mode (0x00/0x01/0x02) + oled_write_command(0x02); // + oled_write_command(0x8d); // --set Charge Pump enable/disable + oled_write_command(0x14); // --set(0x10) disable + oled_write_command(0xa4); // Disable Entire Display On (0xa4/0xa5) + oled_write_command(0xa6); // Disable Inverse Display On (0xa6/a7) + oled_write_command(0xaf); // --turn on oled panel + OLED_CS(1); + + oled_clear(); // 初始清屏 + oled_set_coordinate(0, 0); + oled_debug_init(); +} diff --git a/libraries/zf_device/zf_device_oled.h b/libraries/zf_device/zf_device_oled.h new file mode 100644 index 0000000..937d718 --- /dev/null +++ b/libraries/zf_device/zf_device_oled.h @@ -0,0 +1,136 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_oled +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* D0 查看 zf_device_oled.h 中 OLED_D0_PIN 宏定义 +* D1 查看 zf_device_oled.h 中 OLED_D1_PIN 宏定义 +* RES 查看 zf_device_oled.h 中 OLED_RES_PIN 宏定义 +* DC 查看 zf_device_oled.h 中 OLED_DC_PIN 宏定义 +* CS 查看 zf_device_oled.h 中 OLED_CS_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_oled_h_ +#define _zf_device_oled_h_ + +#include "zf_common_typedef.h" + +#define OLED_USE_SOFT_SPI (0 ) // 默认使用硬件 SPI 方式驱动 建议使用硬件 SPI 方式驱动 +#if OLED_USE_SOFT_SPI // 这两段 颜色正常的才是正确的 颜色灰的就是没有用的 +//====================================================软件 SPI 驱动==================================================== +#define OLED_SOFT_SPI_DELAY (1 ) // 软件 SPI 的时钟延时周期 数值越小 SPI 通信速率越快 +#define OLED_D0_PIN (D4) // 软件 SPI SCK 引脚 +#define OLED_D1_PIN (D6) // 软件 SPI MOSI 引脚 +//====================================================软件 SPI 驱动==================================================== +#else +//====================================================硬件 SPI 驱动==================================================== +#define OLED_SPI_SPEED (72 * 1000 * 1000) // 硬件 SPI 速率 +#define OLED_SPI (SPI_2) // 硬件 SPI 号 +#define OLED_D0_PIN (SPI2_MAP0_SCK_B13 ) // 硬件 SPI SCK 引脚 +#define OLED_D1_PIN (SPI2_MAP0_MOSI_B15) // 硬件 SPI MOSI 引脚 +//====================================================硬件 SPI 驱动==================================================== +#endif + +#define OLED_RES_PIN (B7 ) // 液晶复位引脚定义 +#define OLED_DC_PIN (D7 ) // 液晶命令位引脚定义 +#define OLED_CS_PIN (D4 ) // CS 片选引脚 + +#define OLED_BRIGHTNESS (0x7f) // 设置OLED亮度 越大越亮 范围0-0XFF +#define OLED_DEFAULT_DISPLAY_DIR (OLED_CROSSWISE) // 默认的显示方向 +#define OLED_DEFAULT_DISPLAY_FONT (OLED_6X8_FONT ) // 默认的字体模式 + +#define OLED_RES(x) ((x) ? (gpio_high(OLED_RES_PIN)) : (gpio_low(OLED_RES_PIN))) +#define OLED_DC(x) ((x) ? (gpio_high(OLED_DC_PIN)) : (gpio_low(OLED_DC_PIN))) +#define OLED_CS(x) ((x) ? (gpio_high(OLED_CS_PIN)) : (gpio_low(OLED_CS_PIN))) + +typedef enum +{ + OLED_CROSSWISE = 0, // 横屏模式 + OLED_CROSSWISE_180 = 1, // 横屏模式 旋转180 +}oled_dir_enum; + +typedef enum +{ + OLED_6X8_FONT = 0, // 6x8 字体 + OLED_8X16_FONT = 1, // 8x16 字体 + OLED_16X16_FONT = 2, // 16x16 字体 目前不支持 +}oled_font_size_enum; + +#define OLED_X_MAX (128) +#define OLED_Y_MAX (64 ) + +void oled_clear (void); +void oled_full (const uint8 color); +void oled_set_dir (oled_dir_enum dir); +void oled_set_font (oled_font_size_enum font); +void oled_draw_point (uint16 x, uint16 y, const uint8 color); + +void oled_show_string (uint16 x, uint16 y, const char ch[]); +void oled_show_int (uint16 x, uint16 y, const int32 dat, uint8 num); +void oled_show_uint (uint16 x, uint16 y, const uint32 dat, uint8 num); +void oled_show_float (uint16 x, uint16 y, const double dat, uint8 num, uint8 pointnum); + +void oled_show_binary_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height); +void oled_show_gray_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 threshold); + +void oled_show_wave (uint16 x, uint16 y, const uint16 *image, uint16 width, uint16 value_max, uint16 dis_width, uint16 dis_value_max); +void oled_show_chinese (uint16 x, uint16 y, uint8 size, const uint8 *chinese_buffer, uint8 number); + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED 128*64 显示小钻风图像 +// 参数说明 p 图像数组 +// 返回参数 void +// 使用示例 oled_displayimage7725(ov7725_image_binary[0]); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +#define oled_displayimage7725(p) (oled_show_binary_image(0, 0, (p), OV7725_W, OV7725_H, 128, 64)) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 OLED 128*64 显示总钻风图像 带二值化 +// 参数说明 p 图像数组 +// 参数说明 x 二值化显示阈值 +// 返回参数 void +// 使用示例 oled_displayimage03x(mt9v03x_image[0], 127); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +#define oled_displayimage03x(p,x) (oled_show_gray_image(0, 0, (p), MT9V03X_W, MT9V03X_H, 128, 64, (x))) + +void oled_init (void); + +#endif diff --git a/libraries/zf_device/zf_device_scc8660_dvp.c b/libraries/zf_device/zf_device_scc8660_dvp.c new file mode 100644 index 0000000..f4e4241 --- /dev/null +++ b/libraries/zf_device/zf_device_scc8660_dvp.c @@ -0,0 +1,644 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_scc8660_dvp_dvp +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +*߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* TXD 鿴 zf_device_scc8660_dvp.h SCC8660_COF_UART_TX 궨 +* RXD 鿴 zf_device_scc8660_dvp.h SCC8660_COF_UART_RX 궨 +* D0 鿴 zf_device_scc8660_dvp.h SCC8660_D0_PIN 궨 +* D1 鿴 zf_device_scc8660_dvp.h SCC8660_D1_PIN 궨 +* D2 鿴 zf_device_scc8660_dvp.h SCC8660_D2_PIN 궨 +* D3 鿴 zf_device_scc8660_dvp.h SCC8660_D3_PIN 궨 +* D4 鿴 zf_device_scc8660_dvp.h SCC8660_D4_PIN 궨 +* D5 鿴 zf_device_scc8660_dvp.h SCC8660_D5_PIN 궨 +* D6 鿴 zf_device_scc8660_dvp.h SCC8660_D6_PIN 궨 +* D7 鿴 zf_device_scc8660_dvp.h SCC8660_D7_PIN 궨 +* PCLK 鿴 zf_device_scc8660_dvp.h SCC8660_PCLK_PIN 궨 +* VSYNC 鿴 zf_device_scc8660_dvp.h SCC8660_VSY_PIN 궨 +* HSYNC 鿴 zf_device_scc8660_dvp.h SCC8660_HERF_PIN 궨 +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_device_type.h" +#include "zf_device_camera.h" +#include "zf_device_config.h" +#include "zf_driver_dvp.h" +#include "zf_driver_delay.h" +#include "zf_driver_soft_iic.h" +#include "zf_device_scc8660_dvp.h" + +vuint8 scc8660_finish_flag = 0; // һͼɼɱ־λ +__attribute__((aligned(4))) uint16 scc8660_image[SCC8660_H][SCC8660_W]; + +static fifo_struct *camera_receiver_fifo; +static scc8660_type_enum scc8660_type; + +//------------------------------------------------------------------------------------------------------------------- +// ͷڲϢ ڲ +// ˵ buff Ϣĵַ +// ز uint8 1-ʧ 0-ɹ +// ʹʾ if(scc8660_set_config(scc8660_set_confing_buffer)){} +// עϢ øúǰȳʼ +//------------------------------------------------------------------------------------------------------------------- +static uint8 scc8660_set_config (const int16 buff[SCC8660_CONFIG_FINISH][2]) +{ + uint8 uart_buffer[4]; + uint8 return_state = 0; +// uint16 temp_value = 0; + uint16 timeout_count = 0; + uint32 loop_count = 0; + uint32 uart_buffer_index = 0; + + // ò οֲ + // ʼͷ³ʼ + for(loop_count = SCC8660_MANUAL_WB; SCC8660_SET_REG_DATA > loop_count; loop_count --) + { + uart_buffer[0] = 0xA5; // ֡ͷ + uart_buffer[1] = buff[loop_count][0]; // ָ +// temp_value = buff[loop_count][1]; + uart_buffer[2] = buff[loop_count][1] >> 8; // ݸߵλ + uart_buffer[3] = (uint8)buff[loop_count][1]; // ݸߵλ + uart_write_buffer(SCC8660_COF_UART, uart_buffer, 4); // ͨڷ + system_delay_ms(2); + } + + do + { + if(3 <= fifo_used(camera_receiver_fifo)) // ȴ FIFO д + { + uart_buffer_index = 3; // Ȼ + fifo_read_buffer(camera_receiver_fifo, // FIFO ָ + uart_buffer, // ȡָ + &uart_buffer_index, // Ȼ + FIFO_READ_AND_CLEAN); // ȡղ + if((0xff == uart_buffer[1]) || (0xff == uart_buffer[2])) // жǷӦijɹ + { + return_state = 0; + break; + } + } + system_delay_ms(1); + }while(SCC8660_INIT_TIMEOUT > timeout_count ++); + // ϲֶͷõȫᱣͷ 51 Ƭ eeprom + // set_exposure_time õعݲ洢 eeprom + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// ȡͷڲϢ ڲ +// ˵ buff Ϣĵַ +// ز uint8 1-ʧ 0-ɹ +// ʹʾ if(scc8660_get_config(scc8660_get_confing_buffer)){} +// עϢ øúǰȳʼ +//------------------------------------------------------------------------------------------------------------------- +static uint8 scc8660_get_config (int16 buff[SCC8660_CONFIG_FINISH-1][2]) +{ + int8 loop_count = 0; + uint8 uart_buffer[4]; + uint8 return_state = 0; +// uint16 temp_value = 0; + uint16 timeout_count = 0; + uint32 uart_buffer_index = 0; + + for(loop_count = SCC8660_MANUAL_WB - 1; 0 <= loop_count; loop_count --) + { + uart_buffer[0] = 0xA5; // ֡ͷ + uart_buffer[1] = SCC8660_GET_STATUS; // ȡָ +// temp_value = buff[loop_count][0]; + uart_buffer[2] = buff[loop_count][0] >> 8; // ָߵλ + uart_buffer[3] = (uint8)buff[loop_count][0]; // ָߵλ + uart_write_buffer(SCC8660_COF_UART, uart_buffer, 4); // ͨڷ + + timeout_count = 0; + do + { + if(3 <= fifo_used(camera_receiver_fifo)) // ȴ FIFO д + { + uart_buffer_index = 3; // Ȼ + fifo_read_buffer(camera_receiver_fifo, // FIFO ָ + uart_buffer, // ȡָ + &uart_buffer_index, // Ȼ + FIFO_READ_AND_CLEAN); // ȡղ + buff[loop_count][1] = uart_buffer[1] << 8 | uart_buffer[2]; // ضд뻺 + break; + } + system_delay_ms(1); + }while(SCC8660_INIT_TIMEOUT > timeout_count ++); + if(SCC8660_INIT_TIMEOUT < timeout_count) // ʱ + { + return_state = 1; + break; + } + } + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// ȡͷ ID +// ˵ void +// ز uint16 0-汾ȷ N-汾Ŵ +// ʹʾ scc8660_uart_check_id(); // øúǰȳʼ +// עϢ +//------------------------------------------------------------------------------------------------------------------- +static uint8 scc8660_uart_check_id (void) +{ + uint8 uart_buffer[4]; + uint8 return_state = 1; + uint16 timeout_count = 0; + uint32 uart_buffer_index = 0; + + + if(fifo_used(camera_receiver_fifo)) + { + fifo_clear(camera_receiver_fifo); + } + + uart_write_byte(SCC8660_COF_UART, 0xFF); + uart_buffer[0] = 0xA5; + uart_buffer[1] = SCC8660_GET_WHO_AM_I; + uart_write_buffer(SCC8660_COF_UART, uart_buffer, 4); + + timeout_count = 0; + do + { + if(3 <= fifo_used(camera_receiver_fifo)) + { + uart_buffer_index = 3; + fifo_read_buffer(camera_receiver_fifo, uart_buffer, &uart_buffer_index, FIFO_READ_AND_CLEAN); + return_state = !(0x03 == uart_buffer[2]); + break; + } + system_delay_ms(1); + }while(SCC8660_INIT_TIMEOUT > timeout_count ++); + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// SCC8660 ͨŴڻص +// ˵ void +// ز void +// ʹʾ scc8660_uart_handler(); +// עϢ ͨ zf_device_type.c Ľӿڵ ûʹĬʱҪ +//------------------------------------------------------------------------------------------------------------------- +static void scc8660_uart_handler (void) +{ + uint8 data = 0; + uart_query_byte(SCC8660_COF_UART, &data); + if(NULL != camera_receiver_fifo) + { + if(0xA5 == data) + { + fifo_clear(camera_receiver_fifo); + } + fifo_write_element(camera_receiver_fifo, data); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// SCC8660 жϻص +// ˵ void +// ز void +// ʹʾ scc8660_vsync_handler(); +// עϢ ͨ zf_device_type.c Ľӿڵ ûʹĬʱҪ +//------------------------------------------------------------------------------------------------------------------- +static void scc8660_dvp_handler (void) +{ + scc8660_finish_flag = 1; // ͷɼɱ־λ1 +} + + +//------------------------------------------------------------------------------------------------------------------- +// ȡɫͷ̼汾 ڲ +// ˵ void +// ز uint16 汾 +// ʹʾ scc8660_get_version(); // øúǰȳʼͷô +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint16 scc8660_get_version (void) +{ + uint8 uart_buffer[4]; + uint16 temp_value = 0; + uint16 timeout_count = 0; + uint16 return_value = 0; + uint32 uart_buffer_index = 0; + + uart_buffer[0] = 0xA5; + uart_buffer[1] = SCC8660_GET_STATUS; + temp_value = SCC8660_GET_VERSION; + uart_buffer[2] = temp_value >> 8; + uart_buffer[3] = (uint8)temp_value; + + uart_write_buffer(SCC8660_COF_UART, uart_buffer, 4); + + do + { + if(3 <= fifo_used(camera_receiver_fifo)) + { + uart_buffer_index = 3; + fifo_read_buffer(camera_receiver_fifo, uart_buffer, &uart_buffer_index, FIFO_READ_AND_CLEAN); + return_value = uart_buffer[1] << 8 | uart_buffer[2]; + break; + } + system_delay_ms(1); + }while(SCC8660_INIT_TIMEOUT > timeout_count ++); + return return_value; +} + +//------------------------------------------------------------------------------------------------------------------- +// ͼ +// ˵ data Ҫõֵ +// ز uint8 1-ʧ 0-ɹ +// ʹʾ scc8660_set_brightness(data); // ͨúõIJᱻ51Ƭ +// עϢ øúǰȳʼͷô +//------------------------------------------------------------------------------------------------------------------- +uint8 scc8660_set_brightness (uint16 data) +{ + uint8 uart_buffer[4]; + uint8 return_state = 0; + uint16 temp_value = 0; + uint16 timeout_count = 0; + uint32 uart_buffer_index = 0; + + if(SCC8660_UART == scc8660_type) + { + do + { + uint8 *receiver_buffer = (uint8 *)malloc(SCC8660_COF_BUFFER_SIZE); + if(NULL == receiver_buffer) + { + zf_log(0, "FIFO buffer malloc error."); + return_state = 1; + break; + } + camera_receiver_fifo = (fifo_struct *)malloc(sizeof(fifo_struct)); + if(NULL == camera_receiver_fifo) + { + zf_log(0, "FIFO malloc error."); + free(receiver_buffer); + return_state = 1; + break; + } + fifo_init(camera_receiver_fifo, FIFO_DATA_8BIT, receiver_buffer, SCC8660_COF_BUFFER_SIZE); + + uart_buffer[0] = 0xA5; + uart_buffer[1] = SCC8660_SET_BRIGHT; + uart_buffer[2] = data >> 8; + uart_buffer[3] = (uint8)data; + + uart_write_buffer(SCC8660_COF_UART, uart_buffer, 4); + + do + { + if(3 <= fifo_used(camera_receiver_fifo)) + { + uart_buffer_index = 3; + fifo_read_buffer(camera_receiver_fifo, uart_buffer, &uart_buffer_index, FIFO_READ_AND_CLEAN); + temp_value = uart_buffer[1] << 8 | uart_buffer[2]; + break; + } + system_delay_ms(1); + }while(SCC8660_INIT_TIMEOUT > timeout_count ++); + if((temp_value != data) || (SCC8660_INIT_TIMEOUT <= timeout_count)) + { + return_state = 1; + } + if(NULL != receiver_buffer) + { + free(receiver_buffer); + free(camera_receiver_fifo); + camera_receiver_fifo = NULL; + } + }while(0); + } + else + { + return_state = scc8660_sccb_set_brightness(data); + } + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// ðƽ +// ˵ data Ҫõֵ +// ز uint8 1-ʧ 0-ɹ +// ʹʾ scc8660_set_white_balance(data); // øúǰȳʼͷô +// עϢ ͨúõIJᱻ51Ƭ +//------------------------------------------------------------------------------------------------------------------- +uint8 scc8660_set_white_balance (uint16 data) +{ + uint8 uart_buffer[4]; + uint8 return_state = 0; + uint16 temp_value = 0; + uint16 timeout_count = 0; + uint32 uart_buffer_index = 0; + + if(SCC8660_UART == scc8660_type) + { + do + { + uint8 *receiver_buffer = (uint8 *)malloc(SCC8660_COF_BUFFER_SIZE); + if(NULL == receiver_buffer) + { + zf_log(0, "FIFO buffer malloc error."); + return_state = 1; + break; + } + camera_receiver_fifo = (fifo_struct *)malloc(sizeof(fifo_struct)); + if(NULL == camera_receiver_fifo) + { + zf_log(0, "FIFO malloc error."); + free(receiver_buffer); + return_state = 1; + break; + } + fifo_init(camera_receiver_fifo, FIFO_DATA_8BIT, receiver_buffer, SCC8660_COF_BUFFER_SIZE); + + uart_buffer[0] = 0xA5; + uart_buffer[1] = SCC8660_SET_MANUAL_WB; + uart_buffer[2] = data >> 8; + uart_buffer[3] = (uint8)data; + + uart_write_buffer(SCC8660_COF_UART, uart_buffer, 4); + + do + { + if(3 <= fifo_used(camera_receiver_fifo)) + { + uart_buffer_index = 3; + fifo_read_buffer(camera_receiver_fifo, uart_buffer, &uart_buffer_index, FIFO_READ_AND_CLEAN); + temp_value = uart_buffer[1] << 8 | uart_buffer[2]; + break; + } + system_delay_ms(1); + }while(SCC8660_INIT_TIMEOUT > timeout_count ++); + if((temp_value != data) || (SCC8660_INIT_TIMEOUT <= timeout_count)) + { + return_state = 1; + } + if(NULL != receiver_buffer) + { + free(receiver_buffer); + free(camera_receiver_fifo); + camera_receiver_fifo = NULL; + } + }while(0); + } + else + { + return_state = scc8660_sccb_set_manual_wb(data); + } + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// ͷڲĴд +// ˵ addr ͷڲĴַ +// ˵ data Ҫд +// ز uint8 0-ɹ 1-ʧ 2-ڴʧ +// ʹʾ scc8660_set_reg(addr, data); // øúǰȳʼ +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 scc8660_set_reg (uint8 addr, uint16 data) +{ + uint8 uart_buffer[4]; + uint8 return_state = 0; + uint16 temp_value = 0; + uint16 timeout_count = 0; + uint32 uart_buffer_index = 0; + + if(SCC8660_UART == scc8660_type) + { + do + { + uint8 *receiver_buffer = (uint8 *)malloc(SCC8660_COF_BUFFER_SIZE); + if(NULL == receiver_buffer) + { + return_state = 2; + break; + } + camera_receiver_fifo = (fifo_struct *)malloc(sizeof(fifo_struct)); + if(NULL == camera_receiver_fifo) + { + free(receiver_buffer); + return_state = 2; + break; + } + fifo_init(camera_receiver_fifo, FIFO_DATA_8BIT, receiver_buffer, SCC8660_COF_BUFFER_SIZE); + + uart_buffer[0] = 0xA5; + uart_buffer[1] = SCC8660_SET_REG_ADDR; + uart_buffer[2] = 0x00; + uart_buffer[3] = (uint8)addr; + uart_write_buffer(SCC8660_COF_UART, uart_buffer, 4); + + system_delay_ms(10); + uart_buffer[0] = 0xA5; + uart_buffer[1] = SCC8660_SET_REG_DATA; + temp_value = data; + uart_buffer[2] = temp_value >> 8; + uart_buffer[3] = (uint8)temp_value; + uart_write_buffer(SCC8660_COF_UART, uart_buffer, 4); + + do + { + if(3 <= fifo_used(camera_receiver_fifo)) + { + uart_buffer_index = 3; + fifo_read_buffer(camera_receiver_fifo, uart_buffer, &uart_buffer_index, FIFO_READ_AND_CLEAN); + temp_value = uart_buffer[1] << 8 | uart_buffer[2]; + break; + } + system_delay_ms(1); + }while(SCC8660_INIT_TIMEOUT > timeout_count ++); + if((temp_value != data) || (SCC8660_INIT_TIMEOUT <= timeout_count)) + { + return_state = 1; + } + if(NULL != receiver_buffer) + { + free(receiver_buffer); + free(camera_receiver_fifo); + camera_receiver_fifo = NULL; + } + }while(0); + } + else + { + return_state = scc8660_sccb_set_reg(addr, data); + } + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// SCC8660 ͷʼ +// ˵ void +// ز uint8 1-ʧ 0-ɹ +// ʹʾ scc8660_init(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 scc8660_init (void) +{ + uint8 loop_count = 0; + uint8 return_state = 0; + uint8 *receiver_buffer = NULL; + soft_iic_info_struct scc8660_iic_struct; + + const int16 scc8660_set_confing_buffer[SCC8660_CONFIG_FINISH][2]= + { + {SCC8660_INIT, 0}, // ͷʼʼ + + {SCC8660_AUTO_EXP, SCC8660_AUTO_EXP_DEF}, // Զع + {SCC8660_BRIGHT, SCC8660_BRIGHT_DEF}, // + {SCC8660_FPS, SCC8660_FPS_DEF}, // ͼ֡ + {SCC8660_SET_COL, SCC8660_W}, // ͼ + {SCC8660_SET_ROW, SCC8660_H}, // ͼ + {SCC8660_PCLK_DIV, SCC8660_PCLK_DIV_DEF}, // PCLKƵϵ + {SCC8660_PCLK_MODE, SCC8660_PCLK_MODE_DEF}, // PCLKģʽ + {SCC8660_COLOR_MODE, SCC8660_COLOR_MODE_DEF}, // ͼɫģʽ + {SCC8660_DATA_FORMAT, SCC8660_DATA_FORMAT_DEF}, // ݸʽ + {SCC8660_MANUAL_WB, SCC8660_MANUAL_WB_DEF} // ֶƽ + }; + int16 scc8660_get_confing_buffer[SCC8660_CONFIG_FINISH - 1][2]= + { + {SCC8660_AUTO_EXP, 0}, + {SCC8660_BRIGHT, 0}, // + {SCC8660_FPS, 0}, // ͼ֡ + {SCC8660_SET_COL, 0}, // ͼ + {SCC8660_SET_ROW, 0}, // ͼ + {SCC8660_PCLK_DIV, 0}, // PCLKƵϵ + {SCC8660_PCLK_MODE, 0}, // PCLKģʽ + {SCC8660_COLOR_MODE, 0}, // ͼɫģʽ + {SCC8660_DATA_FORMAT, 0}, // ݸʽ + {SCC8660_MANUAL_WB, 0}, // ƽ + }; + + do + { + scc8660_type = SCC8660_SCCB; // ȳ SCCB ʽͨ + soft_iic_init(&scc8660_iic_struct, // SCCB + 0, // ַΪ 0 + SCC8660_COF_IIC_DELAY, // ʱӳ + SCC8660_COF_IIC_SCL, // SCL + SCC8660_COF_IIC_SDA); // SDA + + if(!scc8660_sccb_check_id(&scc8660_iic_struct)) // Իȡ ID + { + set_camera_type(CAMERA_COLOR, NULL, scc8660_dvp_handler); + return_state = scc8660_sccb_set_config(scc8660_set_confing_buffer); // ȡ ID в + } + else // ûлȡ ID һ + { + scc8660_type = SCC8660_UART; // л UART ʽͨ + set_camera_type(CAMERA_COLOR, scc8660_uart_handler, scc8660_dvp_handler); + receiver_buffer = (uint8 *)malloc(SCC8660_COF_BUFFER_SIZE); // 봮ͨõĻ + if(NULL == receiver_buffer) // ѿռ䲻 + { + return_state = 2; // 쳣 + break; + } + camera_receiver_fifo = (fifo_struct *)malloc(sizeof(fifo_struct)); // FIFO ռ + if(NULL == camera_receiver_fifo) // ѿռ䲻 + { + return_state = 2; // 쳣 + break; + } + fifo_init(camera_receiver_fifo, // Ŀռ FIFO + FIFO_DATA_8BIT, // λ 8bit + receiver_buffer, // ָĻ + SCC8660_COF_BUFFER_SIZE); // С + + // ʼ ͷ + uart_init(SCC8660_COF_UART, // ָ SCC8660 Ĵں + SCC8660_COF_BAUR, // ͨŲ + SCC8660_COF_UART_RX, // оƬ TX ͷģ RX + SCC8660_COF_UART_TX); // оƬ RX ͷģ TX + uart_rx_interrupt(SCC8660_COF_UART, 1); // ж + + if(scc8660_uart_check_id()) // ͨ UART ȡͷ ID + { + uart_rx_interrupt(SCC8660_COF_UART, 0); // ͷ ID ȷ رմڽж + return_state = 3; // һDzѡͷ + break; + } + do + { + if(scc8660_set_config(scc8660_set_confing_buffer)) // ͨ UART ò + { + uart_rx_interrupt(SCC8660_COF_UART, 0); // ͨųʱ˳ رմڽж + return_state = 1; // һ½û ûܾǻ + break; + } + if(scc8660_get_config(scc8660_get_confing_buffer)) // ͨ UART ضò 鿴Ƿȷ + { + uart_rx_interrupt(SCC8660_COF_UART, 0); // ͨųʱ˳ رմڽж + return_state = 1; // һ½û ûܾǻ + break; + } + // Աȷͻ ȷóɹ + for(loop_count = 0; SCC8660_CONFIG_FINISH - 1 > loop_count; loop_count ++) + { + if( scc8660_set_confing_buffer[loop_count + 1][0] != scc8660_get_confing_buffer[loop_count][0] || + scc8660_set_confing_buffer[loop_count + 1][1] != scc8660_get_confing_buffer[loop_count][1]) + { + break; + } + } + return_state = (SCC8660_CONFIG_FINISH - 1 == loop_count) ? 0 : 1; + }while(0); + } + if(!return_state) + { + // DVPųʼ + dvp_gpio_init( + SCC8660_D0_PIN, SCC8660_D1_PIN, SCC8660_D2_PIN, SCC8660_D3_PIN, + SCC8660_D4_PIN, SCC8660_D5_PIN, SCC8660_D6_PIN, SCC8660_D7_PIN, + SCC8660_PCLK_PIN, SCC8660_VSY_PIN, SCC8660_HERF_PIN); + + // DVPӿڳʼ + dvp_camera_init((uint32 *)&scc8660_image[0], (uint32 *)&scc8660_image[0], SCC8660_IMAGE_SIZE, SCC8660_H); + break; + } + set_camera_type(NO_CAMERE, NULL, NULL); + }while(0); + + free(receiver_buffer); // ͷŻڴ + free(camera_receiver_fifo); // ͷ FIFO ڴ + camera_receiver_fifo = NULL; // FIFO ָָ NULL + return return_state; +} diff --git a/libraries/zf_device/zf_device_scc8660_dvp.h b/libraries/zf_device/zf_device_scc8660_dvp.h new file mode 100644 index 0000000..881e3d9 --- /dev/null +++ b/libraries/zf_device/zf_device_scc8660_dvp.h @@ -0,0 +1,152 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_scc8660_dvp +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +*߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* TXD 鿴 zf_device_scc8660.h SCC8660_COF_UART_TX_DVP 궨 +* RXD 鿴 zf_device_scc8660.h SCC8660_COF_UART_RX_DVP 궨 +* D0 鿴 zf_device_scc8660.h SCC8660_D0_PIN_DVP 궨 +* D1 鿴 zf_device_scc8660.h SCC8660_D1_PIN_DVP 궨 +* D2 鿴 zf_device_scc8660.h SCC8660_D2_PIN_DVP 궨 +* D3 鿴 zf_device_scc8660.h SCC8660_D3_PIN_DVP 궨 +* D4 鿴 zf_device_scc8660.h SCC8660_D4_PIN_DVP 궨 +* D5 鿴 zf_device_scc8660.h SCC8660_D5_PIN_DVP 궨 +* D6 鿴 zf_device_scc8660.h SCC8660_D6_PIN_DVP 궨 +* D7 鿴 zf_device_scc8660.h SCC8660_D7_PIN_DVP 궨 +* PCLK 鿴 zf_device_scc8660.h SCC8660_PCLK_PIN_DVP 궨 +* VSYNC 鿴 zf_device_scc8660.h SCC8660_VSY_PIN_DVP 궨 +* HSYNC 鿴 zf_device_scc8660.h SCC8660_HERF_PIN_DVP 궨 +* ------------------------------------ +********************************************************************************************************************/ + + +#ifndef _zf_device_scc8660_h_ +#define _zf_device_scc8660_h_ + +#include "zf_common_typedef.h" + +//-------------------------------------------------------------------------------------------------- +// +//-------------------------------------------------------------------------------------------------- +#define SCC8660_COF_UART UART_5 // ͷʹõĴ +#define SCC8660_COF_BAUR 9600 // ͷõĴڲ ֹ޸ +#define SCC8660_COF_UART_RX UART5_MAP0_TX_C12 // ͷ UART-RX ҪڵƬ TX +#define SCC8660_COF_UART_TX UART5_MAP0_RX_D2 // ͷ UART-TX ҪڵƬ RX + +#define SCC8660_COF_IIC_DELAY (200) // ͫ IIC ʱ +#define SCC8660_COF_IIC_SCL (D2) // ͫ IIC-SCL +#define SCC8660_COF_IIC_SDA (C12) // ͫ IIC-SDA + +#define SCC8660_D0_PIN (A9 ) +#define SCC8660_D1_PIN (A10) +#define SCC8660_D2_PIN (C8 ) +#define SCC8660_D3_PIN (C9 ) +#define SCC8660_D4_PIN (C11) +#define SCC8660_D5_PIN (B6 ) +#define SCC8660_D6_PIN (B8 ) +#define SCC8660_D7_PIN (B9 ) + +#define SCC8660_PCLK_PIN (A6 ) +#define SCC8660_VSY_PIN (A5 ) +#define SCC8660_HERF_PIN (A4 ) +#define SCC8660_INIT_TIMEOUT (0x0080) // Ĭϵͷʼʱʱ Ϊλ + +//-------------------------------------------------------------------------------------------------- +// ͷĬϲ ڴ޸ͷ +//-------------------------------------------------------------------------------------------------- +#define SCC8660_W (160) // ʵͼֱʿ ѡΪ160 180 +#define SCC8660_H (120) // ʵͼֱʸ߶ ѡΪ120 160 +#define SCC8660_IMAGE_SIZE ( SCC8660_W * 2 * SCC8660_H ) // ͼС SCC8660_W*2*SCC8660_H ܳ 65535 +#define SCC8660_COF_BUFFER_SIZE ( 64 ) // ôڻС + +#define SCC8660_AUTO_EXP_DEF (0 ) // Զع ĬϲԶع Χ [0-1] 0Ϊر +#define SCC8660_BRIGHT_DEF (300) // ֶعĬϣ300 ֶعʱΧ0-65535 ԶعƼֵ100 Զعʱ÷Χ0-255 +#define SCC8660_FPS_DEF (60 ) // ͼ֡ Ĭϣ60 ѡΪ60 50 30 25 ʵ֡ʻҪSCC8660_PCLK_DIV +#define SCC8660_PCLK_DIV_DEF (0 ) // PCLKƵϵ Ĭϣ0 ѡΪ<0:1/1> <1:2/3> <2:1/2> <3:1/3> <4:1/4> <5:1/8> + // ƵϵԽPCLKƵԽͣPCLKԼDVPӿڵĸţPCLKƵӰ֡ʡ뱣Ĭϡ + // FPSΪ50֡pclkƵϵѡΪ5ͷ֡Ϊ50*1/8=6.25֡ + // £SCC8660_PCLK_DIVԽͼԽ +#define SCC8660_PCLK_MODE_DEF (1 ) // PCLKģʽ Ĭϣ0 ѡΪ[0,1] 0ź 1ź <ͨΪ0ʹSTM32DCMIӿڲɼҪΪ1> +#define SCC8660_COLOR_MODE_DEF (0 ) // ͼɫģʽ Ĭϣ0 ѡΪ[0,1] 0ɫģʽ 1ģʽɫʱͶߣ +#define SCC8660_DATA_FORMAT_DEF (0 ) // ݸʽ Ĭϣ0 ѡΪ[0-3] 0RGB565 1RGB565(ֽڽ) 2YUV422(YUYV) 3YUV422(UYVY) +#define SCC8660_MANUAL_WB_DEF (0 ) // ֶƽ Ĭϣ0 ѡΪ[0,0x65-0xa0] 0رֶƽ⣬Զƽ ֶƽ ֶƽʱ Χ0x65-0xa0 + +// ͷö +typedef enum +{ + SCC8660_INIT = 0x00, // ͷʼ + SCC8660_AUTO_EXP, // Զع + SCC8660_BRIGHT, // + SCC8660_FPS, // ͷ֡ + SCC8660_SET_COL, // ͼ + SCC8660_SET_ROW, // ͼ + SCC8660_PCLK_DIV, // ʱӷƵ + SCC8660_PCLK_MODE, // ʱģʽ + SCC8660_COLOR_MODE, // ɫģʽ + SCC8660_DATA_FORMAT, // ݸʽ + SCC8660_MANUAL_WB, // ֶƽ + SCC8660_CONFIG_FINISH, // λҪռλ + + SCC8660_GET_WHO_AM_I = 0xEF, // ˭жͷͺ + SCC8660_SET_BRIGHT = 0xF0, // + SCC8660_GET_STATUS = 0XF1, // ȡͷ + SCC8660_GET_VERSION = 0xF2, // ̼汾 + SCC8660_SET_MANUAL_WB = 0xF3, // ֶƽ + + SCC8660_SET_REG_ADDR = 0xFE, + SCC8660_SET_REG_DATA = 0xFF, +}scc8660_cmd_enum; + +// ͷӿö +typedef enum +{ + SCC8660_UART, + SCC8660_SCCB, +}scc8660_type_enum; + +extern vuint8 scc8660_finish_flag; // һͼɼɱ־λ +extern uint16 scc8660_image[SCC8660_H][SCC8660_W]; + +uint16 scc8660_get_id (void); +uint16 scc8660_get_parameter (uint16 config); +uint16 scc8660_get_version (void); +uint8 scc8660_set_bright (uint16 data); +uint8 scc8660_set_white_balance (uint16 data); +uint8 scc8660_set_reg (uint8 addr, uint16 data); + +uint8 scc8660_init (void); + +#endif diff --git a/libraries/zf_device/zf_device_tft180.c b/libraries/zf_device/zf_device_tft180.c new file mode 100644 index 0000000..2db1bd3 --- /dev/null +++ b/libraries/zf_device/zf_device_tft180.c @@ -0,0 +1,1030 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_tft180 +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* SCL 查看 zf_device_tft180.h 中 TFT180_SCL_PIN 宏定义 +* SDA 查看 zf_device_tft180.h 中 TFT180_SDA_PIN 宏定义 +* RES 查看 zf_device_tft180.h 中 TFT180_RES_PIN 宏定义 +* DC 查看 zf_device_tft180.h 中 TFT180_DC_PIN 宏定义 +* CS 查看 zf_device_tft180.h 中 TFT180_CS_PIN 宏定义 +* BL 查看 zf_device_tft180.h 中 TFT180_BL_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* 最大分辨率160*128 +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_common_font.h" +#include "zf_common_function.h" +#include "zf_driver_delay.h" +#include "zf_driver_soft_spi.h" +#include "zf_driver_spi.h" + +#include "zf_device_tft180.h" + +static uint16 tft180_pencolor = TFT180_DEFAULT_PENCOLOR; +static uint16 tft180_bgcolor = TFT180_DEFAULT_BGCOLOR; + +static tft180_dir_enum tft180_display_dir = TFT180_DEFAULT_DISPLAY_DIR; +static tft180_font_size_enum tft180_display_font = TFT180_DEFAULT_DISPLAY_FONT; + +static uint8 tft180_x_max = 160; +static uint8 tft180_y_max = 128; + +#if TFT180_USE_SOFT_SPI +static soft_spi_info_struct tft180_spi; +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 SPI 写 8bit 数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 tft180_write_8bit_data(dat); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define tft180_write_8bit_data(data) (soft_spi_write_8bit(&tft180_spi, (data))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 SPI 写 16bit 数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 tft180_write_16bit_data(x1 + 52); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define tft180_write_16bit_data(data) (soft_spi_write_16bit(&tft180_spi, (data))) +#else +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 SPI 写 8bit 数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 tft180_write_8bit_data(dat); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define tft180_write_8bit_data(data) (spi_write_8bit(TFT180_SPI, (data))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 IPS114 SPI 写 16bit 数据 +// 参数说明 data 数据 +// 返回参数 void +// 使用示例 ips114_write_16bit_data(x1 + 52); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +#define tft180_write_16bit_data(data) (spi_write_16bit(TFT180_SPI, (data))) +#endif + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 写命令 +// 参数说明 dat 数据 +// 返回参数 void +// 使用示例 tft180_write_index(0x2a); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static void tft180_write_index (const uint8 dat) +{ + TFT180_DC(0); + tft180_write_8bit_data(dat); + TFT180_DC(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示区域 内部调用 +// 参数说明 x1 起始x轴坐标 +// 参数说明 y1 起始y轴坐标 +// 参数说明 x2 结束x轴坐标 +// 参数说明 y2 结束y轴坐标 +// 返回参数 void +// 使用示例 tft180_set_region(0, 0, tft180_x_max - 1, tft180_y_max - 1); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static void tft180_set_region (uint16 x1, uint16 y1, uint16 x2, uint16 y2) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + // 检查一下你的显示调用的函数 自己计算一下哪里超过了屏幕显示范围 + zf_assert(x1 < tft180_x_max); + zf_assert(y1 < tft180_y_max); + zf_assert(x2 < tft180_x_max); + zf_assert(y2 < tft180_y_max); + + switch(tft180_display_dir) + { + case TFT180_PORTAIT: + case TFT180_PORTAIT_180: + { + tft180_write_index(0x2a); + tft180_write_8bit_data(0x00); + tft180_write_8bit_data(x1 + 2); + tft180_write_8bit_data(0x00); + tft180_write_8bit_data(x2 + 2); + + tft180_write_index(0x2b); + tft180_write_8bit_data(0x00); + tft180_write_8bit_data(y1 + 1); + tft180_write_8bit_data(0x00); + tft180_write_8bit_data(y2 + 1); + }break; + case TFT180_CROSSWISE: + case TFT180_CROSSWISE_180: + { + tft180_write_index(0x2a); + tft180_write_8bit_data(0x00); + tft180_write_8bit_data(x1 + 1); + tft180_write_8bit_data(0x0); + tft180_write_8bit_data(x2 + 1); + + tft180_write_index(0x2b); + tft180_write_8bit_data(0x00); + tft180_write_8bit_data(y1 + 2); + tft180_write_8bit_data(0x00); + tft180_write_8bit_data(y2 + 2); + }break; + } + tft180_write_index(0x2c); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 显示DEBUG信息初始化 +// 参数说明 void +// 返回参数 void +// 使用示例 tft180_debug_init(); +// 备注信息 内部使用 +//------------------------------------------------------------------------------------------------------------------- +static void tft180_debug_init (void) +{ + debug_output_struct info; + debug_output_struct_init(&info); + + info.type_index = 1; + info.display_x_max = tft180_x_max; + info.display_y_max = tft180_y_max; + + switch(tft180_display_font) + { + case TFT180_6X8_FONT: + { + info.font_x_size = 6; + info.font_y_size = 8; + }break; + case TFT180_8X16_FONT: + { + info.font_x_size = 8; + info.font_y_size = 16; + }break; + case TFT180_16X16_FONT: + { + // 暂不支持 + }break; + } + info.output_screen = tft180_show_string; + info.output_screen_clear = tft180_clear; + + debug_output_init(&info); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 清屏函数 +// 参数说明 void +// 返回参数 void +// 使用示例 tft180_clear(); +// 备注信息 将屏幕清空成背景颜色 +//------------------------------------------------------------------------------------------------------------------- +void tft180_clear (void) +{ + uint32 i = tft180_x_max * tft180_y_max; + + TFT180_CS(0); + tft180_set_region(0, 0, tft180_x_max - 1, tft180_y_max - 1); + for( ; 0 < i; i --) + { + tft180_write_16bit_data(tft180_bgcolor); + } + TFT180_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 清屏函数 +// 参数说明 color 颜色格式 RGB565 或者可以使用 zf_common_font.h 内常用颜色宏定义 +// 返回参数 void +// 使用示例 tft180_full(RGB565_YELLOW); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void tft180_full (const uint16 color) +{ + uint32 i = tft180_x_max * tft180_y_max; + + TFT180_CS(0); + tft180_set_region(0, 0, tft180_x_max - 1, tft180_y_max - 1); + for( ; 0 < i; i --) + { + tft180_write_16bit_data(color); + } + TFT180_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示方向 +// 参数说明 dir 显示方向 参照 zf_device_ips114.h 内 tft180_dir_enum 枚举体定义 +// 返回参数 void +// 使用示例 tft180_set_dir(TFT180_CROSSWISE); +// 备注信息 这个函数只有在初始化屏幕之前调用才生效 +//------------------------------------------------------------------------------------------------------------------- +void tft180_set_dir (tft180_dir_enum dir) +{ + tft180_display_dir = dir; + switch(tft180_display_dir) + { + case TFT180_PORTAIT: + case TFT180_PORTAIT_180: + { + tft180_x_max = 128; + tft180_y_max = 160; + }break; + case TFT180_CROSSWISE: + case TFT180_CROSSWISE_180: + { + tft180_x_max = 160; + tft180_y_max = 128; + }break; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示字体 +// 参数说明 dir 显示方向 参照 zf_device_tft180.h 内 tft180_font_size_enum 枚举体定义 +// 返回参数 void +// 使用示例 tft180_set_font(TFT180_8x16_FONT); +// 备注信息 字体可以随时自由设置 设置后生效 后续显示就是新的字体大小 +//------------------------------------------------------------------------------------------------------------------- +void tft180_set_font (tft180_font_size_enum font) +{ + tft180_display_font = font; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 设置显示颜色 +// 参数说明 pen 颜色格式 RGB565 或者可以使用 zf_common_font.h 内常用颜色宏定义 +// 参数说明 bgcolor 颜色格式 RGB565 或者可以使用 zf_common_font.h 内常用颜色宏定义 +// 返回参数 void +// 使用示例 tft180_set_color(RGB565_WHITE, RGB565_BLACK); +// 备注信息 字体颜色和背景颜色也可以随时自由设置 设置后生效 +//------------------------------------------------------------------------------------------------------------------- +void tft180_set_color (uint16 pen, const uint16 bgcolor) +{ + tft180_pencolor = pen; + tft180_bgcolor = bgcolor; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 画点 +// 参数说明 x 坐标x方向的起点 参数范围 [0, tft180_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, tft180_y_max-1] +// 参数说明 dat 需要显示的颜色 +// 返回参数 void +// 使用示例 tft180_draw_point(0, 0, RGB565_RED); // 坐标 0,0 画一个红色的点 +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void tft180_draw_point (uint16 x, uint16 y, const uint16 color) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < tft180_x_max); + zf_assert(y < tft180_y_max); + + TFT180_CS(0); + tft180_set_region(x, y, x, y); + tft180_write_16bit_data(color); + TFT180_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 画线 +// 参数说明 x_start 坐标x方向的起点 +// 参数说明 y_start 坐标y方向的起点 +// 参数说明 x_end 坐标x方向的终点 +// 参数说明 y_end 坐标y方向的终点 +// 参数说明 dat 需要显示的颜色 +// 返回参数 void +// 使用示例 tft180_draw_line(0, 0, 10, 10,RGB565_RED); // 坐标 0,0 到 10,10 画一条红色的线 +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void tft180_draw_line (uint16 x_start, uint16 y_start, uint16 x_end, uint16 y_end, const uint16 color) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x_start < tft180_x_max); + zf_assert(y_start < tft180_y_max); + zf_assert(x_end < tft180_x_max); + zf_assert(y_end < tft180_y_max); + + int16 x_dir = (x_start < x_end ? 1 : -1); + int16 y_dir = (y_start < y_end ? 1 : -1); + float temp_rate = 0; + float temp_b = 0; + + do + { + if(x_start != x_end) + { + temp_rate = (float)(y_start - y_end) / (float)(x_start - x_end); + temp_b = (float)y_start - (float)x_start * temp_rate; + } + else + { + while(y_start != y_end) + { + tft180_draw_point(x_start, y_start, color); + y_start += y_dir; + } + break; + } + + if(func_abs(y_start - y_end) > func_abs(x_start - x_end)) + { + while(y_start != y_end) + { + tft180_draw_point(x_start, y_start, color); + y_start += y_dir; + x_start = (int16)(((float)y_start - temp_b) / temp_rate); + } + } + else + { + while(x_start != x_end) + { + tft180_draw_point(x_start, y_start, color); + x_start += x_dir; + y_start = (int16)((float)x_start * temp_rate + temp_b); + } + } + }while(0); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 显示字符 +// 参数说明 x 坐标x方向的起点 参数范围 [0, tft180_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, tft180_y_max-1] +// 参数说明 dat 需要显示的字符 +// 返回参数 void +// 使用示例 tft180_show_char(0, 0, 'x'); // 坐标 0,0 写一个字符 x +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void tft180_show_char (uint16 x, uint16 y, const char dat) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < tft180_x_max); + zf_assert(y < tft180_y_max); + + uint8 i = 0, j = 0; + + TFT180_CS(0); + switch(tft180_display_font) + { + case TFT180_6X8_FONT: + { + for(i = 0; 6 > i; i ++) + { + tft180_set_region(x + i, y, x + i, y + 8); + // 减 32 因为是取模是从空格开始取得 空格在 ascii 中序号是 32 + uint8 temp_top = ascii_font_6x8[dat - 32][i]; + for(j = 0; 8 > j; j ++) + { + if(temp_top & 0x01) + { + tft180_write_16bit_data(tft180_pencolor); + } + else + { + tft180_write_16bit_data(tft180_bgcolor); + } + temp_top >>= 1; + } + } + }break; + case TFT180_8X16_FONT: + { + for(i = 0; 8 > i; i ++) + { + tft180_set_region(x + i, y, x + i, y + 15); + // 减 32 因为是取模是从空格开始取得 空格在 ascii 中序号是 32 + uint8 temp_top = ascii_font_8x16[dat - 32][i]; + uint8 temp_bottom = ascii_font_8x16[dat - 32][i + 8]; + for(j = 0; 8 > j; j ++) + { + if(temp_top & 0x01) + { + tft180_write_16bit_data(tft180_pencolor); + } + else + { + tft180_write_16bit_data(tft180_bgcolor); + } + temp_top >>= 1; + } + for(j = 0; 8 > j; j ++) + { + if(temp_bottom & 0x01) + { + tft180_write_16bit_data(tft180_pencolor); + } + else + { + tft180_write_16bit_data(tft180_bgcolor); + } + temp_bottom >>= 1; + } + } + }break; + case TFT180_16X16_FONT: + { + // 暂不支持 + }break; + } + TFT180_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 显示字符串 +// 参数说明 x 坐标x方向的起点 参数范围 [0, tft180_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, tft180_y_max-1] +// 参数说明 dat 需要显示的字符串 +// 返回参数 void +// 使用示例 tft180_show_string(0, 0, "seekfree"); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void tft180_show_string (uint16 x, uint16 y, const char dat[]) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < tft180_x_max); + zf_assert(y < tft180_y_max); + + uint16 j = 0; + while('\0' != dat[j]) + { + switch(tft180_display_font) + { + case TFT180_6X8_FONT: tft180_show_char(x + 6 * j, y, dat[j]); break; + case TFT180_8X16_FONT: tft180_show_char(x + 8 * j, y, dat[j]); break; + case TFT180_16X16_FONT: break; // 暂不支持 + } + j ++; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 显示32位有符号 (去除整数部分无效的0) +// 参数说明 x 坐标x方向的起点 参数范围 [0, tft180_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, tft180_y_max-1] +// 参数说明 dat 需要显示的变量 数据类型 int32 +// 参数说明 num 需要显示的位数 最高10位 不包含正负号 +// 返回参数 void +// 使用示例 tft180_show_int(0, 0, x, 3); // x 可以为 int32 int16 int8 类型 +// 备注信息 负数会显示一个 ‘-’号 +//------------------------------------------------------------------------------------------------------------------- +void tft180_show_int (uint16 x, uint16 y, const int32 dat, uint8 num) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < tft180_x_max); + zf_assert(y < tft180_y_max); + zf_assert(0 < num); + zf_assert(10 >= num); + + int32 dat_temp = dat; + int32 offset = 1; + char data_buffer[12]; + + memset(data_buffer, 0, 12); + memset(data_buffer, ' ', num + 1); + + // 用来计算余数显示 123 显示 2 位则应该显示 23 + if(10 > num) + { + for(; 0 < num; num --) + { + offset *= 10; + } + dat_temp %= offset; + } + func_int_to_str(data_buffer, dat_temp); + tft180_show_string(x, y, (const char *)&data_buffer); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 显示32位无符号 (去除整数部分无效的0) +// 参数说明 x 坐标x方向的起点 参数范围 [0, tft180_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, tft180_y_max-1] +// 参数说明 dat 需要显示的变量 数据类型 uint32 +// 参数说明 num 需要显示的位数 最高10位 不包含正负号 +// 返回参数 void +// 使用示例 tft180_show_uint(0, 0, x, 3); // x 可以为 uint32 uint16 uint8 类型 +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void tft180_show_uint (uint16 x, uint16 y, const uint32 dat, uint8 num) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < tft180_x_max); + zf_assert(y < tft180_y_max); + zf_assert(0 < num); + zf_assert(10 >= num); + + uint32 dat_temp = dat; + int32 offset = 1; + char data_buffer[12]; + memset(data_buffer, 0, 12); + memset(data_buffer, ' ', num); + + // 用来计算余数显示 123 显示 2 位则应该显示 23 + if(10 > num) + { + for(; 0 < num; num --) + { + offset *= 10; + } + dat_temp %= offset; + } + func_uint_to_str(data_buffer, dat_temp); + tft180_show_string(x, y, (const char *)&data_buffer); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 显示浮点数(去除整数部分无效的0) +// 参数说明 x 坐标x方向的起点 参数范围 [0, tft180_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, tft180_y_max-1] +// 参数说明 dat 需要显示的变量 数据类型 float +// 参数说明 num 整数位显示长度 最高8位 +// 参数说明 pointnum 小数位显示长度 最高6位 +// 返回参数 void +// 使用示例 tft180_show_float(0, 0, x, 2, 3); // 显示浮点数 整数显示2位 小数显示三位 +// 备注信息 特别注意当发现小数部分显示的值与你写入的值不一样的时候， +// 可能是由于浮点数精度丢失问题导致的，这并不是显示函数的问题， +// 有关问题的详情，请自行百度学习 浮点数精度丢失问题。 +// 负数会显示一个 ‘-’号 +//------------------------------------------------------------------------------------------------------------------- +void tft180_show_float (uint16 x, uint16 y, const double dat, uint8 num, uint8 pointnum) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < tft180_x_max); + zf_assert(y < tft180_y_max); + zf_assert(0 < num); + zf_assert(8 >= num); + zf_assert(0 < pointnum); + zf_assert(6 >= pointnum); + + double dat_temp = dat; + double offset = 1.0; + char data_buffer[17]; + memset(data_buffer, 0, 17); + memset(data_buffer, ' ', num + pointnum + 2); + + // 用来计算余数显示 123 显示 2 位则应该显示 23 + for(; 0 < num; num --) + { + offset *= 10; + } + dat_temp = dat_temp - ((int)dat_temp / (int)offset) * offset; + func_double_to_str(data_buffer, dat_temp, pointnum); + tft180_show_string(x, y, data_buffer); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 显示二值图像 数据每八个点组成一个字节数据 +// 参数说明 x 坐标x方向的起点 参数范围 [0, tft180_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, tft180_y_max-1] +// 参数说明 *image 图像数组指针 +// 参数说明 width 图像实际宽度 +// 参数说明 height 图像实际高度 +// 参数说明 dis_width 图像显示宽度 参数范围 [0, tft180_x_max] +// 参数说明 dis_height 图像显示高度 参数范围 [0, tft180_y_max] +// 返回参数 void +// 使用示例 tft180_show_binary_image(0, 0, ov7725_image_binary[0], OV7725_W, OV7725_H, OV7725_W / 2, OV7725_H / 2); +// 备注信息 用于显示小钻风的未解压的压缩二值化图像 +// 这个函数不可以用来直接显示总钻风的未压缩的二值化图像 +// 这个函数不可以用来直接显示总钻风的未压缩的二值化图像 +// 这个函数不可以用来直接显示总钻风的未压缩的二值化图像 +//------------------------------------------------------------------------------------------------------------------- +void tft180_show_binary_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < tft180_x_max); + zf_assert(y < tft180_y_max); + zf_assert(NULL != image); + + uint32 i = 0, j = 0; + uint8 temp = 0; + uint32 width_index = 0, height_index = 0; + + TFT180_CS(0); + tft180_set_region(x, y, x + dis_width - 1, y + dis_height - 1); // 设置显示区域 + + for(j = 0; j < dis_height; j ++) + { + height_index = j * height / dis_height; + for(i = 0; i < dis_width; i ++) + { + width_index = i * width / dis_width; + temp = *(image + height_index * width / 8 + width_index / 8); // 读取像素点 + if(0x80 & (temp << (width_index % 8))) + { + tft180_write_16bit_data(RGB565_WHITE); + } + else + { + tft180_write_16bit_data(RGB565_BLACK); + } + } + } + TFT180_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 显示 8bit 灰度图像 带二值化阈值 +// 参数说明 x 坐标x方向的起点 参数范围 [0, tft180_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, tft180_y_max-1] +// 参数说明 *image 图像数组指针 +// 参数说明 width 图像实际宽度 +// 参数说明 height 图像实际高度 +// 参数说明 dis_width 图像显示宽度 参数范围 [0, tft180_x_max] +// 参数说明 dis_height 图像显示高度 参数范围 [0, tft180_y_max] +// 参数说明 threshold 二值化显示阈值 0-不开启二值化 +// 返回参数 void +// 使用示例 tft180_show_gray_image(0, 0, mt9v03x_image[0], MT9V03X_W, MT9V03X_H, MT9V03X_W / 2, MT9V03X_H / 2, 0); +// 备注信息 用于显示总钻风的图像 +// 如果要显示二值化图像 直接修改最后一个参数为需要的二值化阈值即可 +// 如果要显示二值化图像 直接修改最后一个参数为需要的二值化阈值即可 +// 如果要显示二值化图像 直接修改最后一个参数为需要的二值化阈值即可 +//------------------------------------------------------------------------------------------------------------------- +void tft180_show_gray_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 threshold) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < tft180_x_max); + zf_assert(y < tft180_y_max); + zf_assert(NULL != image); + + uint32 i = 0, j = 0; + uint16 color = 0,temp = 0; + uint32 width_index = 0, height_index = 0; + + TFT180_CS(0); + tft180_set_region(x, y, x + dis_width - 1, y + dis_height - 1); // 设置显示区域 + + for(j = 0; j < dis_height; j ++) + { + height_index = j * height / dis_height; + for(i = 0; i < dis_width; i ++) + { + width_index = i * width / dis_width; + temp = *(image + height_index * width + width_index); // 读取像素点 + if(threshold == 0) + { + color = (0x001f & ((temp) >> 3)) << 11; + color = color | (((0x003f) & ((temp) >> 2)) << 5); + color = color | (0x001f & ((temp) >> 3)); + tft180_write_16bit_data(color); + } + else if(temp < threshold) + { + tft180_write_16bit_data(RGB565_BLACK); + } + else + { + tft180_write_16bit_data(RGB565_WHITE); + } + } + } + TFT180_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 显示 RGB565 彩色图像 +// 参数说明 x 坐标x方向的起点 参数范围 [0, tft180_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, tft180_y_max-1] +// 参数说明 *image 图像数组指针 +// 参数说明 width 图像实际宽度 +// 参数说明 height 图像实际高度 +// 参数说明 dis_width 图像显示宽度 参数范围 [0, tft180_x_max] +// 参数说明 dis_height 图像显示高度 参数范围 [0, tft180_y_max] +// 参数说明 color_mode 色彩模式 0-低位在前 1-高位在前 +// 返回参数 void +// 使用示例 tft180_show_rgb565_image(0, 0, scc8660_image[0], SCC8660_W, SCC8660_H, SCC8660_W / 2, SCC8660_H / 2, 1); +// 备注信息 用于显示凌瞳的 RGB565 的图像 +// 如果要显示低位在前的其他 RGB565 图像 修改最后一个参数即可 +// 如果要显示低位在前的其他 RGB565 图像 修改最后一个参数即可 +// 如果要显示低位在前的其他 RGB565 图像 修改最后一个参数即可 +//------------------------------------------------------------------------------------------------------------------- +void tft180_show_rgb565_image (uint16 x, uint16 y, const uint16 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 color_mode) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < tft180_x_max); + zf_assert(y < tft180_y_max); + zf_assert(NULL != image); + + uint32 i = 0, j = 0; + uint16 color = 0; + uint32 width_index = 0, height_index = 0; + + TFT180_CS(0); + tft180_set_region(x, y, x + dis_width - 1, y + dis_height - 1); // 设置显示区域 + + for(j = 0; j < dis_height; j ++) + { + height_index = j * height / dis_height; + for(i = 0; i < dis_width; i ++) + { + width_index = i * width / dis_width; + color = *(image + height_index * width + width_index); // 读取像素点 + if(color_mode) + { + color = ((color & 0xff) << 8) | (color >> 8); + } + tft180_write_16bit_data(color); + } + } + TFT180_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 显示波形 +// 参数说明 x 坐标x方向的起点 参数范围 [0, tft180_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, tft180_y_max-1] +// 参数说明 *wave 波形数组指针 +// 参数说明 width 波形实际宽度 +// 参数说明 value_max 波形实际最大值 +// 参数说明 dis_width 波形显示宽度 参数范围 [0, tft180_x_max] +// 参数说明 dis_value_max 波形显示最大值 参数范围 [0, tft180_y_max] +// 返回参数 void +// 使用示例 tft180_show_wave(32, 64, data, 128, 64, 64, 32); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void tft180_show_wave (uint16 x, uint16 y, const uint16 *wave, uint16 width, uint16 value_max, uint16 dis_width, uint16 dis_value_max) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < tft180_x_max); + zf_assert(y < tft180_y_max); + zf_assert(NULL != wave); + + uint32 i = 0, j = 0; + uint32 width_index = 0, value_max_index = 0; + + TFT180_CS(0); + tft180_set_region(x, y, x + dis_width - 1, y + dis_value_max - 1); // 设置显示区域 + for(i = 0; i < dis_value_max; i ++) + { + for(j = 0; j < dis_width; j ++) + { + tft180_write_16bit_data(tft180_bgcolor); + } + } + TFT180_CS(1); + + for(i = 0; i < dis_width; i ++) + { + width_index = i * width / dis_width; + value_max_index = *(wave + width_index) * (dis_value_max - 1) / value_max; + tft180_draw_point(i + x, (dis_value_max - 1) - value_max_index + y, tft180_pencolor); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 汉字显示 +// 参数说明 x 坐标x方向的起点 参数范围 [0, tft180_x_max-1] +// 参数说明 y 坐标y方向的起点 参数范围 [0, tft180_y_max-1] +// 参数说明 size 取模的时候设置的汉字字体大小 也就是一个汉字占用的点阵长宽为多少个点 取模的时候需要长宽是一样的 +// 参数说明 *chinese_buffer 需要显示的汉字数组 +// 参数说明 number 需要显示多少位 +// 参数说明 color 显示颜色 +// 返回参数 void +// 使用示例 tft180_show_chinese(0, 0, 16, chinese_test[0], 4, RGB565_RED);//显示font文件里面的 示例 +// 备注信息 使用PCtoLCD2002软件取模 阴码、逐行式、顺向 16*16 +//------------------------------------------------------------------------------------------------------------------- +void tft180_show_chinese (uint16 x, uint16 y, uint8 size, const uint8 *chinese_buffer, uint8 number, const uint16 color) +{ + // 如果程序在输出了断言信息 并且提示出错位置在这里 + // 那么一般是屏幕显示的时候超过屏幕分辨率范围了 + zf_assert(x < tft180_x_max); + zf_assert(y < tft180_y_max); + zf_assert(NULL != chinese_buffer); + + int i = 0, j = 0, k = 0; + uint8 temp = 0, temp1 = 0, temp2 = 0; + const uint8 *p_data = chinese_buffer; + + temp2 = size / 8; + + TFT180_CS(0); + tft180_set_region(x, y, number * size - 1 + x, y + size - 1); + + for(i = 0; i < size; i ++) + { + temp1 = number; + p_data = chinese_buffer + i * temp2; + while(temp1 --) + { + for(k = 0; k < temp2; k ++) + { + for(j = 8; 0 < j; j --) + { + temp = (*p_data >> (j - 1)) & 0x01; + if(temp) + { + tft180_write_16bit_data(color); + } + else + { + tft180_write_16bit_data(tft180_bgcolor); + } + } + p_data ++; + } + p_data = p_data - temp2 + temp2 * size; + } + } + TFT180_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 初始化 +// 返回参数 void +// 返回参数 void +// 使用示例 tft180_init(); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void tft180_init (void) +{ +#if TFT180_USE_SOFT_SPI + soft_spi_init(&tft180_spi, 0, TFT180_SOFT_SPI_DELAY, TFT180_SCL_PIN, TFT180_SDA_PIN, SOFT_SPI_PIN_NULL, SOFT_SPI_PIN_NULL); +#else + spi_init(TFT180_SPI, SPI_MODE0, TFT180_SPI_SPEED, TFT180_SCL_PIN, TFT180_SDA_PIN, SPI_MISO_NULL, SPI_CS_NULL); +#endif + + gpio_init(TFT180_DC_PIN, GPO, GPIO_LOW, GPO_PUSH_PULL); + gpio_init(TFT180_RES_PIN, GPO, GPIO_LOW, GPO_PUSH_PULL); + gpio_init(TFT180_CS_PIN, GPO, GPIO_HIGH, GPO_PUSH_PULL); + gpio_init(TFT180_BL_PIN, GPO, GPIO_HIGH, GPO_PUSH_PULL); + + tft180_set_dir(tft180_display_dir); + tft180_set_color(tft180_pencolor, tft180_bgcolor); + + TFT180_RST(0); + system_delay_ms(10); + + TFT180_RST(1); + system_delay_ms(120); + TFT180_CS(0); + + tft180_write_index(0x11); + system_delay_ms(120); + + tft180_write_index(0xB1); + tft180_write_8bit_data(0x01); + tft180_write_8bit_data(0x2C); + tft180_write_8bit_data(0x2D); + + tft180_write_index(0xB2); + tft180_write_8bit_data(0x01); + tft180_write_8bit_data(0x2C); + tft180_write_8bit_data(0x2D); + + tft180_write_index(0xB3); + tft180_write_8bit_data(0x01); + tft180_write_8bit_data(0x2C); + tft180_write_8bit_data(0x2D); + tft180_write_8bit_data(0x01); + tft180_write_8bit_data(0x2C); + tft180_write_8bit_data(0x2D); + + tft180_write_index(0xB4); + tft180_write_8bit_data(0x07); + + tft180_write_index(0xC0); + tft180_write_8bit_data(0xA2); + tft180_write_8bit_data(0x02); + tft180_write_8bit_data(0x84); + tft180_write_index(0xC1); + tft180_write_8bit_data(0xC5); + + tft180_write_index(0xC2); + tft180_write_8bit_data(0x0A); + tft180_write_8bit_data(0x00); + + tft180_write_index(0xC3); + tft180_write_8bit_data(0x8A); + tft180_write_8bit_data(0x2A); + tft180_write_index(0xC4); + tft180_write_8bit_data(0x8A); + tft180_write_8bit_data(0xEE); + + tft180_write_index(0xC5); + tft180_write_8bit_data(0x0E); + + tft180_write_index(0x36); + switch(tft180_display_dir) // y x v + { + case TFT180_PORTAIT: tft180_write_8bit_data(1<<7 | 1<<6 | 0<<5); break; + case TFT180_PORTAIT_180: tft180_write_8bit_data(0<<7 | 0<<6 | 0<<5); break; + case TFT180_CROSSWISE: tft180_write_8bit_data(1<<7 | 0<<6 | 1<<5); break; + case TFT180_CROSSWISE_180: tft180_write_8bit_data(0<<7 | 1<<6 | 1<<5); break; + } + + tft180_write_index(0xe0); + tft180_write_8bit_data(0x0f); + tft180_write_8bit_data(0x1a); + tft180_write_8bit_data(0x0f); + tft180_write_8bit_data(0x18); + tft180_write_8bit_data(0x2f); + tft180_write_8bit_data(0x28); + tft180_write_8bit_data(0x20); + tft180_write_8bit_data(0x22); + tft180_write_8bit_data(0x1f); + tft180_write_8bit_data(0x1b); + tft180_write_8bit_data(0x23); + tft180_write_8bit_data(0x37); + tft180_write_8bit_data(0x00); + tft180_write_8bit_data(0x07); + tft180_write_8bit_data(0x02); + tft180_write_8bit_data(0x10); + + tft180_write_index(0xe1); + tft180_write_8bit_data(0x0f); + tft180_write_8bit_data(0x1b); + tft180_write_8bit_data(0x0f); + tft180_write_8bit_data(0x17); + tft180_write_8bit_data(0x33); + tft180_write_8bit_data(0x2c); + tft180_write_8bit_data(0x29); + tft180_write_8bit_data(0x2e); + tft180_write_8bit_data(0x30); + tft180_write_8bit_data(0x30); + tft180_write_8bit_data(0x39); + tft180_write_8bit_data(0x3f); + tft180_write_8bit_data(0x00); + tft180_write_8bit_data(0x07); + tft180_write_8bit_data(0x03); + tft180_write_8bit_data(0x10); + + tft180_write_index(0x2a); + tft180_write_8bit_data(0x00); + tft180_write_8bit_data(0x00 + 2); + tft180_write_8bit_data(0x00); + tft180_write_8bit_data(0x80 + 2); + + tft180_write_index(0x2b); + tft180_write_8bit_data(0x00); + tft180_write_8bit_data(0x00 + 3); + tft180_write_8bit_data(0x00); + tft180_write_8bit_data(0x80 + 3); + + tft180_write_index(0xF0); + tft180_write_8bit_data(0x01); + tft180_write_index(0xF6); + tft180_write_8bit_data(0x00); + + tft180_write_index(0x3A); + tft180_write_8bit_data(0x05); + tft180_write_index(0x29); + TFT180_CS(1); + + tft180_clear(); + tft180_debug_init(); +} diff --git a/libraries/zf_device/zf_device_tft180.h b/libraries/zf_device/zf_device_tft180.h new file mode 100644 index 0000000..ff21a03 --- /dev/null +++ b/libraries/zf_device/zf_device_tft180.h @@ -0,0 +1,159 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_device_tft180 +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* 接线定义： +* ------------------------------------ +* 模块管脚 单片机管脚 +* SCL 查看 zf_device_tft180.h 中 TFT180_SCL_PIN 宏定义 +* SDA 查看 zf_device_tft180.h 中 TFT180_SDA_PIN 宏定义 +* RES 查看 zf_device_tft180.h 中 TFT180_RES_PIN 宏定义 +* DC 查看 zf_device_tft180.h 中 TFT180_DC_PIN 宏定义 +* CS 查看 zf_device_tft180.h 中 TFT180_CS_PIN 宏定义 +* BL 查看 zf_device_tft180.h 中 TFT180_BL_PIN 宏定义 +* VCC 3.3V电源 +* GND 电源地 +* 最大分辨率160*128 +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_tft180_h_ +#define _zf_device_tft180_h_ + +#include "zf_common_typedef.h" + +#define TFT180_USE_SOFT_SPI (0) // 默认使用硬件 SPI 方式驱动 建议使用硬件 SPI 方式驱动 +#if TFT180_USE_SOFT_SPI // 这两段 颜色正常的才是正确的 颜色灰的就是没有用的 +//====================================================软件 SPI 驱动==================================================== +#define TFT180_SOFT_SPI_DELAY (1 ) // 软件 SPI 的时钟延时周期 数值越小 SPI 通信速率越快 +#define TFT180_SCL_PIN (B13) // 软件 SPI SCK 引脚 +#define TFT180_SDA_PIN (B15) // 软件 SPI MOSI 引脚 +//====================================================软件 SPI 驱动==================================================== +#else +//====================================================硬件 SPI 驱动==================================================== +#define TFT180_SPI_SPEED (72 * 1000 * 1000) // 硬件 SPI 速率 +#define TFT180_SPI (SPI_2) // 硬件 SPI 号 +#define TFT180_SCL_PIN (SPI2_MAP0_SCK_B13) // 硬件 SPI SCK 引脚 +#define TFT180_SDA_PIN (SPI2_MAP0_MOSI_B15) // 硬件 SPI MOSI 引脚 +//====================================================硬件 SPI 驱动==================================================== +#endif + +#define TFT180_RES_PIN (B7) // 液晶复位引脚定义 +#define TFT180_DC_PIN (D7) // 液晶命令位引脚定义 +#define TFT180_CS_PIN (D4) // CS 片选引脚 +#define TFT180_BL_PIN (D0) // 液晶背光引脚定义 + +#define TFT180_DEFAULT_DISPLAY_DIR (TFT180_PORTAIT) // 默认的显示方向 +#define TFT180_DEFAULT_PENCOLOR (RGB565_RED) // 默认的画笔颜色 +#define TFT180_DEFAULT_BGCOLOR (RGB565_WHITE) // 默认的背景颜色 +#define TFT180_DEFAULT_DISPLAY_FONT (TFT180_8X16_FONT) // 默认的字体模式 + +#define TFT180_DC(x) ((x) ? (gpio_high(TFT180_DC_PIN)) : (gpio_low(TFT180_DC_PIN))) +#define TFT180_RST(x) ((x) ? (gpio_high(TFT180_RES_PIN)) : (gpio_low(TFT180_RES_PIN))) +#define TFT180_CS(x) ((x) ? (gpio_high(TFT180_CS_PIN)) : (gpio_low(TFT180_CS_PIN))) +#define TFT180_BLK(x) ((x) ? (gpio_high(TFT180_BL_PIN)) : (gpio_low(TFT180_BL_PIN))) + +typedef enum +{ + TFT180_PORTAIT = 0, // 竖屏模式 + TFT180_PORTAIT_180 = 1, // 竖屏模式 旋转180 + TFT180_CROSSWISE = 2, // 横屏模式 + TFT180_CROSSWISE_180 = 3, // 横屏模式 旋转180 +}tft180_dir_enum; + +typedef enum +{ + TFT180_6X8_FONT = 0, // 6x8 字体 + TFT180_8X16_FONT = 1, // 8x16 字体 + TFT180_16X16_FONT = 2, // 16x16 字体 目前不支持 +}tft180_font_size_enum; + +void tft180_clear (void); +void tft180_full (const uint16 color); +void tft180_set_dir (tft180_dir_enum dir); +void tft180_set_font (tft180_font_size_enum font); +void tft180_set_color (const uint16 pen, const uint16 bgcolor); +void tft180_draw_point (uint16 x, uint16 y, const uint16 color); +void tft180_draw_line (uint16 x_start, uint16 y_start, uint16 x_end, uint16 y_end, const uint16 color); + +void tft180_show_char (uint16 x, uint16 y, const char dat); +void tft180_show_string (uint16 x, uint16 y, const char dat[]); +void tft180_show_int (uint16 x,uint16 y, const int32 dat, uint8 num); +void tft180_show_uint (uint16 x,uint16 y, const uint32 dat, uint8 num); +void tft180_show_float (uint16 x,uint16 y, const double dat, uint8 num, uint8 pointnum); + +void tft180_show_binary_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height); +void tft180_show_gray_image (uint16 x, uint16 y, const uint8 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 threshold); +void tft180_show_rgb565_image (uint16 x, uint16 y, const uint16 *image, uint16 width, uint16 height, uint16 dis_width, uint16 dis_height, uint8 color_mode); + +void tft180_show_wave (uint16 x, uint16 y, const uint16 *wave, uint16 width, uint16 value_max, uint16 dis_width, uint16 dis_value_max); +void tft180_show_chinese (uint16 x, uint16 y, uint8 size, const uint8 *chinese_buffer, uint8 number, const uint16 color); + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 显示小钻风图像 +// 参数说明 p 图像数组 +// 参数说明 width 显示宽度 +// 参数说明 height 显示高度 +// 返回参数 void +// 使用示例 tft180_displayimage7725(ov7725_image_binary[0], 80, 60); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +#define tft180_displayimage7725(p, width, height) (tft180_show_binary_image(0, 0, (p), OV7725_W, OV7725_H, (width), (height))) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 显示总钻风图像 不带二值化 显示灰度图像 +// 参数说明 p 图像数组 +// 参数说明 width 显示宽度 +// 参数说明 height 显示高度 +// 返回参数 void +// 使用示例 tft180_displayimage03x(mt9v03x_image[0], 94, 60); +// 备注信息 如果要显示二值化图像就去调用 tft180_show_gray_image 函数 +//------------------------------------------------------------------------------------------------------------------- +#define tft180_displayimage03x(p, width, height) (tft180_show_gray_image(0, 0, (p), MT9V03X_W, MT9V03X_H, (width), (height), 0)) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 TFT180 显示凌瞳图像 +// 参数说明 p 图像数组 +// 参数说明 width 显示宽度 +// 参数说明 height 显示高度 +// 返回参数 void +// 使用示例 tft180_displayimage8660(scc8660_image[0], 80, 60); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +#define tft180_displayimage8660(p, width, height) (tft180_show_rgb565_image(0, 0, (p), SCC8660_W, SCC8660_H, (width), (height), 1)) + +void tft180_init (void); + +#endif + diff --git a/libraries/zf_device/zf_device_type.c b/libraries/zf_device/zf_device_type.c new file mode 100644 index 0000000..fac355e --- /dev/null +++ b/libraries/zf_device/zf_device_type.c @@ -0,0 +1,105 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_type +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "zf_device_type.h" + + +static void type_default_callback (void); + +camera_type_enum camera_type = NO_CAMERE; // ͷͱ +callback_function camera_uart_handler = type_default_callback; // ͨѶжϺָ룬ݳʼʱõĺת +callback_function camera_dvp_handler = type_default_callback; // DVPжϺָ룬ݳʼʱõĺת + +wireless_type_enum wireless_type = NO_WIRELESS; +callback_function wireless_module_uart_handler= type_default_callback; // ߴڽжϺָ룬ݳʼʱõĺת + +tof_type_enum tof_type = NO_TOF; +callback_function tof_module_exti_handler = type_default_callback; // ToF ģ INT ж + +//------------------------------------------------------------------------------------------------------------------- +// Ĭϻص +// ˵ void +// ز void +// ʹʾ +// עϢ ֹûгʼ豸ʱܷ +//------------------------------------------------------------------------------------------------------------------- +static void type_default_callback (void) +{ +} + +//------------------------------------------------------------------------------------------------------------------- +// ͷ +// ˵ type_set ѡͷ +// ˵ vsync_callback 豸ijжϻص +// ˵ dma_callback 豸 DMA жϻص +// ˵ uart_callback 豸Ĵڻص +// ز void +// ʹʾ set_camera_type(CAMERA_GRAYSCALE); +// עϢ һɸͷʼڲ +//------------------------------------------------------------------------------------------------------------------- +void set_camera_type (camera_type_enum type_set, callback_function uart_callback, callback_function dvp_callback) +{ + camera_type = type_set; + camera_dvp_handler = ((dvp_callback == NULL) ? (type_default_callback) : (dvp_callback)); + camera_uart_handler = ((uart_callback == NULL) ? (type_default_callback) : (uart_callback)); +} + +//------------------------------------------------------------------------------------------------------------------- +// ģ +// ˵ type_set ѡģ +// ˵ uart_callback 豸Ĵڻص +// ز void +// ʹʾ set_wireless_type(WIRELESS_UART, uart_callback); +// עϢ һɸͷʼڲ +//------------------------------------------------------------------------------------------------------------------- +void set_wireless_type (wireless_type_enum type_set, callback_function uart_callback) +{ + wireless_type = type_set; + wireless_module_uart_handler = ((uart_callback == NULL) ? (type_default_callback) : (uart_callback)); +} + +//------------------------------------------------------------------------------------------------------------------- +// ToF ģ +// ˵ type_set ѡ ToF ģ +// ˵ exti_callback 豸ⲿжϻص +// ز void +// ʹʾ set_tof_type(TOF_DL1A, dl1a_int_handler); +// עϢ һɸͷʼڲ +//------------------------------------------------------------------------------------------------------------------- +void set_tof_type (tof_type_enum type_set, callback_function exti_callback) +{ + tof_type = type_set; + tof_module_exti_handler = ((exti_callback == NULL) ? (type_default_callback) : (exti_callback)); +} diff --git a/libraries/zf_device/zf_device_type.h b/libraries/zf_device/zf_device_type.h new file mode 100644 index 0000000..c74c0a2 --- /dev/null +++ b/libraries/zf_device/zf_device_type.h @@ -0,0 +1,83 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_type +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +#ifndef _zf_device_type_h_ +#define _zf_device_type_h_ + +#include "zf_common_typedef.h" + +typedef enum +{ + NO_CAMERE = 0, // ͷ + CAMERA_BIN_IIC, // С IIC 汾 + CAMERA_BIN_UART, // С UART 汾 + CAMERA_GRAYSCALE, // + CAMERA_COLOR, // ͫ +}camera_type_enum; + +typedef enum +{ + NO_WIRELESS = 0, // 豸 + WIRELESS_UART, // ߴ + BLUETOOTH_CH9141, // CH9141 + WIFI_UART, // Wi-Fi + WIRELESS_CH573, + WIFI_SPI, // Wi-Fi SPI +}wireless_type_enum; + +typedef enum +{ + NO_TOF = 0, // 豸 + TOF_DL1A, // DL1A + TOF_DL1B, // DL1B +}tof_type_enum; + +typedef void (*callback_function)(void); + +extern camera_type_enum camera_type; +extern wireless_type_enum wireless_type; +extern tof_type_enum tof_type; + +extern callback_function camera_uart_handler; +extern callback_function camera_dvp_handler; +extern callback_function wireless_module_uart_handler; +extern callback_function tof_module_exti_handler; + + +void set_camera_type (camera_type_enum type_set, callback_function uart_callback, callback_function dvp_callback); +void set_wireless_type (wireless_type_enum type_set, callback_function uart_callback); +void set_tof_type (tof_type_enum type_set, callback_function exti_callback); + + +#endif diff --git a/libraries/zf_device/zf_device_virtual_oscilloscope.c b/libraries/zf_device/zf_device_virtual_oscilloscope.c new file mode 100644 index 0000000..4c0674d --- /dev/null +++ b/libraries/zf_device/zf_device_virtual_oscilloscope.c @@ -0,0 +1,98 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_virtual_oscilloscope +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "zf_device_virtual_oscilloscope.h" + +uint8_t virtual_oscilloscope_data[10]; + +//------------------------------------------------------------------------------------------------------------------- +// @brief CRC У ڲʹ û +// @param buff Ҫ CRC ݵַ +// @param crc_cnt Ҫ CRC ݸ +// @return uint16 CRC У +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +static uint16 crc_check (uint8 *buff, uint8 crc_cnt) +{ + uint16 crc_temp; + uint8 i,j; + crc_temp = 0xffff; + + for (i=0;i>1) ^ 0xa001; + else + crc_temp = crc_temp >> 1; + } + } + return(crc_temp); +} + +//------------------------------------------------------------------------------------------------------------------- +// @brief ʾת +// @param data1 Ҫ͵ĵһ +// @param data2 Ҫ͵ĵڶ +// @param data3 Ҫ͵ĵ +// @param data4 Ҫ͵ĵĸ +// @param *dat ת֮ݵĵַ +// @return void +// ʹʾ uint8_t data_buffer[10]; +// virtual_oscilloscope_data_conversion(100,200,300,400, data_buffer); +// wireless_uart_send_buff(data_buffer, 10); +//------------------------------------------------------------------------------------------------------------------- +void virtual_oscilloscope_data_conversion (const int16 data1, const int16 data2, const int16 data3, const int16 data4) +{ + uint16 crc_16 = 0; + + virtual_oscilloscope_data[0] = (uint8)((uint16)data1&0xff); + virtual_oscilloscope_data[1] = (uint8)((uint16)data1>>8); + + virtual_oscilloscope_data[2] = (uint8)((uint16)data2&0xff); + virtual_oscilloscope_data[3] = (uint8)((uint16)data2>>8); + + virtual_oscilloscope_data[4] = (uint8)((uint16)data3&0xff); + virtual_oscilloscope_data[5] = (uint8)((uint16)data3>>8); + + virtual_oscilloscope_data[6] = (uint8)((uint16)data4&0xff); + virtual_oscilloscope_data[7] = (uint8)((uint16)data4>>8); + + crc_16 = crc_check(virtual_oscilloscope_data,8); + virtual_oscilloscope_data[8] = (uint8)(crc_16&0xff); + virtual_oscilloscope_data[9] = (uint8)(crc_16>>8); +} diff --git a/libraries/zf_device/zf_device_virtual_oscilloscope.h b/libraries/zf_device/zf_device_virtual_oscilloscope.h new file mode 100644 index 0000000..a40895a --- /dev/null +++ b/libraries/zf_device/zf_device_virtual_oscilloscope.h @@ -0,0 +1,45 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_virtual_oscilloscope +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_device_virtual_oscilloscope_h_ +#define _zf_device_virtual_oscilloscope_h_ + +#include "zf_common_typedef.h" + +extern uint8_t virtual_oscilloscope_data[10]; + +void virtual_oscilloscope_data_conversion (const int16 data1, const int16 data2, const int16 data3, const int16 data4); + +#endif diff --git a/libraries/zf_device/zf_device_w25q32.c b/libraries/zf_device/zf_device_w25q32.c new file mode 100644 index 0000000..78d5c54 --- /dev/null +++ b/libraries/zf_device/zf_device_w25q32.c @@ -0,0 +1,401 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_w25q32 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* //------------------Ӳ SPI ------------------// +* SPC 鿴 zf_device_w25q32.h W25Q32_SPC_PIN 궨 +* SDI 鿴 zf_device_w25q32.h W25Q32_SDI_PIN 궨 +* SDO 鿴 zf_device_w25q32.h W25Q32_SDO_PIN 궨 +* CS 鿴 zf_device_w25q32.h W25Q32_CS_PIN 궨 +* //------------------Ӳ SPI ------------------// +* Դ +* VCC 3.3VԴ +* GND Դ +* ------------------------------------ +********************************************************************************************************************/ + +#include "zf_device_w25q32.h" + + +static uint8 w25q32_read_dat() +{ + // W25Q32_CS(0); + uint8 dat = spi_read_8bit(W25Q32_SPI); + // W25Q32_CS(1); + return dat; +} + +static void w25q32_read_dats(uint8 *dat, uint32 len) +{ + // W25Q32_CS(0); + spi_read_8bit_array(W25Q32_SPI, dat, len); + // W25Q32_CS(1); +} + +static void w25q32_write_dat(uint8 dat) +{ + // W25Q32_CS(0); + spi_write_8bit(W25Q32_SPI, dat); + // W25Q32_CS(1); +} + + +static void w25q32_write_dats(uint8 *dat, uint32 len) +{ + // W25Q32_CS(0); + spi_write_8bit_array(W25Q32_SPI, dat, len); + // W25Q32_CS(1); +} + +//------------------------------------------------------------------------------------------------------------------- +// дʹ ڲ +// ˵ void +// ز void +//------------------------------------------------------------------------------------------------------------------- +static void w25q32_write_enable(void) +{ + W25Q32_CS(0); + w25q32_write_dat(W25Q32_WRITE_ENABLE); //дʹ + W25Q32_CS(1); +} + +////------------------------------------------------------------------------------------------------------------------- +//// @brief дʧ ڲ +//// @param void +//// @return void +////------------------------------------------------------------------------------------------------------------------- +//static void w25q32_write_disable(void) +//{ +// W25Q32_CS(0); +// w25q32_write_dat(W25Q32_WRITE_DISABLE); //дָֹ +// W25Q32_CS(1); +//} + + + +//------------------------------------------------------------------------------------------------------------------- +// ȡ״̬ ڲ +// ˵ void +// ز uint8 Ĵ״ֵ̬ +// BIT7 6 5 4 3 2 1 0 +// SPR RV TB BP2 BP1 BP0 WEL BUSY +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +static uint8 w25q32_read_state(void) +{ + uint8 byte=0; + W25Q32_CS(0); + //Ͷȡ״̬Ĵ + //ȡһֽ + w25q32_write_dat(W25Q32_READ_STATUS_REG_1); // Ͷȡ + byte = w25q32_read_dat(); // ȡһֽ + W25Q32_CS(1); + return byte; +} + + +//------------------------------------------------------------------------------------------------------------------- +// ȴæ ڲ +// ˵ void +// ز void +//------------------------------------------------------------------------------------------------------------------- +static void w25q32_wait_busy(void) +{ + while ((w25q32_read_state()&0x01)==0x01); // ȴBUSYλ +} + + +//------------------------------------------------------------------------------------------------------------------- +// оƬid ڲ +// ˵ void +// ز uint16 IDֵ +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +static uint16 w25q32_read_device_id(void) +{ + uint8 send_dat[4] = {W25Q32_DEVICE_ID, 0x00, 0x00, 0x00}; + uint8 read_dat[2] = {0}; + W25Q32_CS(0); + w25q32_write_dats(send_dat, 4); + w25q32_read_dats(read_dat, 2); + W25Q32_CS(1); + + return read_dat[0] << 8 | read_dat[1]; +} + +//------------------------------------------------------------------------------------------------------------------- +// W25Q32(Ҫȴ20) +// ˵ void +// ز void +//------------------------------------------------------------------------------------------------------------------- +void w25q32_erase_chip(void) +{ + w25q32_wait_busy(); + W25Q32_CS(0); //ʹ + w25q32_write_dat(W25Q32_CHIP_ERASE); //Ƭ + W25Q32_CS(1); //ȡƬѡ + w25q32_wait_busy(); //ȴоƬ +} + + +//------------------------------------------------------------------------------------------------------------------- +// ȡһֽ ڲ +// ˵ uint32 ȡַ24bit +// ز uint8 ȡֵ +// @since v1.0 +// ʹʾ w25q32_read_byte(0x000001); +//------------------------------------------------------------------------------------------------------------------- +static uint8 w25q32_read_byte(uint32 addr) +{ + uint8 temp; + W25Q32_CS(0); + + w25q32_write_dat(W25Q32_READ_DATA); // Ͷȡ + w25q32_write_dat((uint8)((addr)>>16)); // 24bitַ + w25q32_write_dat((uint8)((addr)>>8)); + w25q32_write_dat((uint8)addr); + temp = w25q32_read_dat(); // ȡһֽ + + W25Q32_CS(1); + return temp; +} + +//------------------------------------------------------------------------------------------------------------------- +// Уw25q32Ƿ +// ˵ block_num Ҫд Χ W25Q32_BLOCK_00 - W25Q32_BLOCK_63 +// ˵ sector_num Ҫд Χ W25Q32_SECTION_00 - W25Q32_SECTION_15 +// ˵ page_num ǰҳı Χ W25Q32_PAGE_00 - W25Q32_PAGE_15 +// ز 1ݣ0ûݣҪݵдµӦöв +// @since v1.0 +// ʹʾ w25q32_check(W25Q32_BLOCK_63, W25Q32_SECTION_15, W25Q32_PAGE_00); +//------------------------------------------------------------------------------------------------------------------- +uint8 w25q32_check (w25q32_block_enum block_num, w25q32_section_enum sector_num, w25q32_page_enum page_num) +{ + uint16 temp_loop; + uint32 addr = (W25Q32_BASE_ADDR + + W25Q32_BLOCK_SIZE*block_num + + W25Q32_SECTION_SIZE*sector_num + + W25Q32_PAGE_SIZE*page_num); // ȡǰַ + + for(temp_loop = 0; temp_loop < W25Q32_PAGE_SIZE; temp_loop++) // ѭȡ Flash ֵ + { + if( w25q32_read_byte(addr + temp_loop) != 0xff ) // 0xff Ǿֵ + return 1; + } + return 0; +} + + +//------------------------------------------------------------------------------------------------------------------- +// һ +// ˵ block_num Ҫд Χ W25Q32_BLOCK_00 - W25Q32_BLOCK_63 +// ˵ sector_num Ҫд Χ W25Q32_SECTION_00 - W25Q32_SECTION_15 +// ز +// @since v1.0 +// ʹʾ w25q32_erase_sector(W25Q32_BLOCK_63, W25Q32_SECTION_15); +//------------------------------------------------------------------------------------------------------------------- +uint8 w25q32_erase_sector(w25q32_block_enum block_num, w25q32_section_enum sector_num) +{ + uint32 addr = (W25Q32_BASE_ADDR + + W25Q32_BLOCK_SIZE*block_num + + W25Q32_SECTION_SIZE*sector_num + + W25Q32_PAGE_SIZE*0); // ȡǰַ + + W25Q32_CS(0); + + w25q32_write_dat(W25Q32_SECTOR_ERASE); // Ͳ + w25q32_write_dat((uint8)((addr)>>16)); // 24bitַ + w25q32_write_dat((uint8)((addr)>>8)); + w25q32_write_dat((uint8)addr); + + W25Q32_CS(1); + w25q32_wait_busy(); // ȴ + return 0; +} + + + + +//------------------------------------------------------------------------------------------------------------------- +// Ӹõַʼȡ ڲʹ +// ˵ addr ʼȡĵַ24bit +// ˵ buff ݴ洢 +// ˵ len Ҫȡij(65535) +// ز +// @since v1.0 +// ʹʾ w25q32_erase_sector(0x000001, buf, 16); +//------------------------------------------------------------------------------------------------------------------- +static void w25q32_read_addr_dats(uint32 addr, uint8 *buff, uint16 len) +{ + W25Q32_CS(0); + w25q32_write_dat(W25Q32_FAST_READ); // Ͷȡ + w25q32_write_dat((uint8)((addr)>>16)); // 24bitַ + w25q32_write_dat((uint8)((addr)>>8)); + w25q32_write_dat((uint8)addr); + w25q32_read_dat(); // ٶȡҪһֽΪֽڡ + w25q32_read_dats(buff, len); + + W25Q32_CS(1);//ȡƬѡ +} + + +//------------------------------------------------------------------------------------------------------------------- +// Ӹõַʼд ڲʹ +// ˵ addr ʼдĵַ24bit +// ˵ buff ݴ洢 +// ˵ len Ҫдij(256,lenܳҳʣֽ) +// ز +// @since v1.0 +// ʹʾ w25q32_write_addr_dats(0x000001, buf, 16); +//------------------------------------------------------------------------------------------------------------------- +static void w25q32_write_addr_dats(uint32 addr, uint8 *buff, uint16 len) +{ + + W25Q32_CS(0); + + w25q32_write_dat(W25Q32_PAGE_PROGRAM); // дҳ + w25q32_write_dat((uint8)((addr)>>16)); // 24bitַ + w25q32_write_dat((uint8)((addr)>>8)); + w25q32_write_dat((uint8)addr); + w25q32_write_dats(buff, len); + W25Q32_CS(1); + w25q32_wait_busy(); // ȴд +} + +//------------------------------------------------------------------------------------------------------------------- +// ȡһҳ +// ˵ block_num Ҫȡ Χ W25Q32_BLOCK_00 - W25Q32_BLOCK_63 +// ˵ sector_num Ҫȡ Χ W25Q32_SECTION_00 - W25Q32_SECTION_15 +// ˵ page_num Ҫȡҳ Χ W25Q32_PAGE_00 - W25Q32_PAGE_15 +// ˵ buf Ҫȡݵַ ͱΪuint8 * +// ˵ len Ҫȡݳ Χ 1-256 +// ز NULL +// @since v1.0 +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void w25q32_read_page(w25q32_block_enum block_num, w25q32_section_enum sector_num, w25q32_page_enum page_num, + uint8 *buf, uint16 len) +{ + uint32 addr = (W25Q32_BASE_ADDR + + W25Q32_BLOCK_SIZE*block_num + + W25Q32_SECTION_SIZE*sector_num + + W25Q32_PAGE_SIZE*page_num); // ȡǰ Flash ַ + + w25q32_read_addr_dats(addr, buf, len); +} + +//------------------------------------------------------------------------------------------------------------------- +// дһҳ +// ˵ block_num Ҫȡ Χ W25Q32_BLOCK_00 - W25Q32_BLOCK_63 +// ˵ sector_num Ҫȡ Χ W25Q32_SECTION_00 - W25Q32_SECTION_15 +// ˵ page_num Ҫȡҳ Χ W25Q32_PAGE_00 - W25Q32_PAGE_15 +// ˵ buf Ҫȡݵַ ͱΪuint8 * +// ˵ len Ҫȡݳ Χ 1-256 +// ز NULL +// @since v1.0 +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void w25q32_write_page(w25q32_block_enum block_num, w25q32_section_enum sector_num, w25q32_page_enum page_num, + uint8 *buf, uint16 len) +{ + uint32 flash_addr = (W25Q32_BASE_ADDR + + W25Q32_BLOCK_SIZE*block_num + + W25Q32_SECTION_SIZE*sector_num + + W25Q32_PAGE_SIZE*page_num); // ȡǰ Flash ַ + + w25q32_write_addr_dats(flash_addr, buf, len); +} + + +//------------------------------------------------------------------------------------------------------------------- +// Լ ڲ +// ˵ void +// ز void +//------------------------------------------------------------------------------------------------------------------- +static uint8 w25q32_self_check(void) +{ + uint8 ret = 0; + uint16 dat = 0; + volatile int16 timeout_count = W25Q32_TIMEOUT_COUNT; + +///* Winbond SPIFalsh ID */ +//#define W25Q80 0XEF13 +//#define W25Q16 0XEF14 +//#define W25Q32 0XEF15 +//#define W25Q64 0XEF16 +//#define W25Q128 0XEF17 + + while(((dat & 0xEF10) != 0xEF10) && timeout_count) // ж ID Ƿȷ + { + timeout_count--; + + dat = w25q32_read_device_id(); + + system_delay_ms(1); + } + + if(timeout_count < 0) + { + ret = 1; + } + else + { + ret = 0; + } + + return ret; +} + +//------------------------------------------------------------------------------------------------------------------- +// ʼ W25Q32 +// ˵ void +// ز uint8 1-ʼʧ 0-ʼɹ +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +uint8 w25q32_init(void) +{ + spi_init(W25Q32_SPI, SPI_MODE0, W25Q32_SPI_SPEED, W25Q32_SPC_PIN, W25Q32_SDI_PIN, W25Q32_SDO_PIN, W25Q32_CS_PIN); + + if( w25q32_self_check() ) + { + zf_log(0, "W25Q32 self check error."); + return 1; + } + + w25q32_write_enable(); // дʹ + return 0; +} diff --git a/libraries/zf_device/zf_device_w25q32.h b/libraries/zf_device/zf_device_w25q32.h new file mode 100644 index 0000000..645980a --- /dev/null +++ b/libraries/zf_device/zf_device_w25q32.h @@ -0,0 +1,242 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_w25q32 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* //------------------Ӳ SPI ------------------// +* SPC 鿴 zf_device_w25q32.h W25Q32_SPC_PIN 궨 +* SDI 鿴 zf_device_w25q32.h W25Q32_SDI_PIN 궨 +* SDO 鿴 zf_device_w25q32.h W25Q32_SDO_PIN 궨 +* CS 鿴 zf_device_w25q32.h W25Q32_CS_PIN 궨 +* //------------------Ӳ SPI ------------------// +* Դ +* VCC 3.3VԴ +* GND Դ +* ------------------------------------ +********************************************************************************************************************/ + +#ifndef _zf_device_w25q32_h_ +#define _zf_device_w25q32_h_ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" + +#include "zf_driver_delay.h" +#include "zf_driver_spi.h" +#include "zf_driver_soft_iic.h" + + +#define W25Q32_BASE_ADDR (0x00000000) // W25Q32FALSH׵ַ +#define W25Q32_PAGE_SIZE (0x00000100) // 256 byte +#define W25Q32_SECTION_SIZE (W25Q32_PAGE_SIZE *16) // 4K byte +#define W25Q32_BLOCK_SIZE (W25Q32_SECTION_SIZE *16) // 64K byte + +//W25Q326464*65536 = 4194304 Byte4194304/1024/1024 = 4MB,Ѱַռ䣺0x000000~0x3FFFFF + +//W25QXXϵFLASHͬ +//ͬͺŵflashвͬĿW25Q1632W25Q3264Դƣϸġ +//3.2W25QXXϵFLASHоƬͬͺŵͬɶ +//1 = 16 +//1 = 16 * 16 * 256ֽڣByte= 65536Byte = 64KB65536Byte/1024=64KB +//1 = 16ҳ +//1 = 16 * 256Byte= 4096Byte = 4KB +//1ҳ = 256ֽ + + +// ö Flash öٶ岻û޸ +typedef enum +{ + W25Q32_BLOCK_00, + W25Q32_BLOCK_01, + W25Q32_BLOCK_02, + W25Q32_BLOCK_03, + W25Q32_BLOCK_04, + W25Q32_BLOCK_05, + W25Q32_BLOCK_06, + W25Q32_BLOCK_07, + W25Q32_BLOCK_08, + W25Q32_BLOCK_09, + W25Q32_BLOCK_10, + W25Q32_BLOCK_11, + W25Q32_BLOCK_12, + W25Q32_BLOCK_13, + W25Q32_BLOCK_14, + W25Q32_BLOCK_15, + W25Q32_BLOCK_16, + W25Q32_BLOCK_17, + W25Q32_BLOCK_18, + W25Q32_BLOCK_19, + W25Q32_BLOCK_20, + W25Q32_BLOCK_21, + W25Q32_BLOCK_22, + W25Q32_BLOCK_23, + W25Q32_BLOCK_24, + W25Q32_BLOCK_25, + W25Q32_BLOCK_26, + W25Q32_BLOCK_27, + W25Q32_BLOCK_28, + W25Q32_BLOCK_29, + W25Q32_BLOCK_30, + W25Q32_BLOCK_31, + W25Q32_BLOCK_32, + W25Q32_BLOCK_33, + W25Q32_BLOCK_34, + W25Q32_BLOCK_35, + W25Q32_BLOCK_36, + W25Q32_BLOCK_37, + W25Q32_BLOCK_38, + W25Q32_BLOCK_39, + W25Q32_BLOCK_40, + W25Q32_BLOCK_41, + W25Q32_BLOCK_42, + W25Q32_BLOCK_43, + W25Q32_BLOCK_44, + W25Q32_BLOCK_45, + W25Q32_BLOCK_46, + W25Q32_BLOCK_47, + W25Q32_BLOCK_48, + W25Q32_BLOCK_49, + W25Q32_BLOCK_50, + W25Q32_BLOCK_51, + W25Q32_BLOCK_52, + W25Q32_BLOCK_53, + W25Q32_BLOCK_54, + W25Q32_BLOCK_55, + W25Q32_BLOCK_56, + W25Q32_BLOCK_57, + W25Q32_BLOCK_58, + W25Q32_BLOCK_59, + W25Q32_BLOCK_60, + W25Q32_BLOCK_61, + W25Q32_BLOCK_62, + W25Q32_BLOCK_63 +}w25q32_block_enum; + +// ö Flash öٶ岻û޸ +typedef enum +{ + W25Q32_SECTION_00, + W25Q32_SECTION_01, + W25Q32_SECTION_02, + W25Q32_SECTION_03, + W25Q32_SECTION_04, + W25Q32_SECTION_05, + W25Q32_SECTION_06, + W25Q32_SECTION_07, + W25Q32_SECTION_08, + W25Q32_SECTION_09, + W25Q32_SECTION_10, + W25Q32_SECTION_11, + W25Q32_SECTION_12, + W25Q32_SECTION_13, + W25Q32_SECTION_14, + W25Q32_SECTION_15, +}w25q32_section_enum; + +// ö Flash ҳ öٶ岻û޸ +typedef enum +{ + W25Q32_PAGE_00, + W25Q32_PAGE_01, + W25Q32_PAGE_02, + W25Q32_PAGE_03, + W25Q32_PAGE_04, + W25Q32_PAGE_05, + W25Q32_PAGE_06, + W25Q32_PAGE_07, + W25Q32_PAGE_08, + W25Q32_PAGE_09, + W25Q32_PAGE_10, + W25Q32_PAGE_11, + W25Q32_PAGE_12, + W25Q32_PAGE_13, + W25Q32_PAGE_14, + W25Q32_PAGE_15, +}w25q32_page_enum; + +//====================================================Ӳ SPI ==================================================== +#define W25Q32_SPI_SPEED system_clock/8 // Ӳ SPI +#define W25Q32_SPI SPI_3 // Ӳ SPI +#define W25Q32_SPC_PIN SPI1_MAP1_SCK_B3 // Ӳ SPI SCK +#define W25Q32_SDI_PIN SPI1_MAP1_MISO_B4 // Ӳ SPI MOSI +#define W25Q32_SDO_PIN SPI1_MAP1_MOSI_B5 // Ӳ SPI MISO +//====================================================Ӳ SPI ==================================================== +#define W25Q32_CS_PIN A15 // CS Ƭѡ +#define W25Q32_CS(x) (x? (gpio_high(W25Q32_CS_PIN)): (gpio_low(W25Q32_CS_PIN))) + +#define W25Q32_TIMEOUT_COUNT 0x00FF + +//================================================ ICM20602 ڲַ================================================ +#define W25Q32_WRITE_ENABLE 0x06 +#define W25Q32_WRITE_DISABLE 0x04 + +#define W25Q32_READ_STATUS_REG_1 0x05 +#define W25Q32_READ_STATUS_REG_2 0x35 +#define W25Q32_READ_STATUS_REG_3 0x15 +#define W25Q32_WRITE_STATUS_REG_1 0x01 +#define W25Q32_WRITE_STATUS_REG_2 0x31 +#define W25Q32_WRITE_STATUS_REG_3 0x11 +#define W25Q32_PAGE_PROGRAM 0x02 +#define W25Q32_READ_DATA 0x03 +#define W25Q32_FAST_READ 0x0B +#define W25Q32_SECTOR_ERASE 0x20 +#define W25Q32_32KB_BLOCK_ERASE 0x52 +#define W25Q32_64KB_BLOCK_ERASE 0xD8 +#define W25Q32_CHIP_ERASE 0xC7 +#define W25Q32_SUSPEND 0x75 +#define W25Q32_RESUME 0x7A +#define W25Q32_READ_UID 0x4B +#define W25Q32_JEDEC_ID 0x9F // W25Q32 0xEF40 +#define W25Q32_DEVICE_ID 0x90 // W25Q32 0xEF15 +#define W25Q32_RESET_ENABLE 0x66 +#define W25Q32_RESET_DEVICE 0x99 +//================================================ ICM20602 ڲַ================================================ + + +void w25q32_erase_chip(void); +uint8 w25q32_check (w25q32_block_enum block_num, w25q32_section_enum sector_num, w25q32_page_enum page_num); +uint8 w25q32_erase_sector (w25q32_block_enum block_num, w25q32_section_enum sector_num); + +void w25q32_read_page (w25q32_block_enum block_num, w25q32_section_enum sector_num, w25q32_page_enum page_num, + uint8 *buf, uint16 len); + +void w25q32_write_page (w25q32_block_enum block_num, w25q32_section_enum sector_num, w25q32_page_enum page_num, + uint8 *buf, uint16 len); +uint8 w25q32_init(); + +//SPI_FLASHдʹ + +#endif diff --git a/libraries/zf_device/zf_device_wifi_spi.c b/libraries/zf_device/zf_device_wifi_spi.c new file mode 100644 index 0000000..e6601a7 --- /dev/null +++ b/libraries/zf_device/zf_device_wifi_spi.c @@ -0,0 +1,1381 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_wifi_spi +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2023-05-25 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* RST 鿴 zf_device_wifi_spi.h WIFI_SPI_RST_PIN 궨 +* INT 鿴 zf_device_wifi_spi.h WIFI_SPI_INT_PIN 궨 +* CS 鿴 zf_device_wifi_spi.h WIFI_SPI_CS_PIN 궨 +* MISO 鿴 zf_device_wifi_spi.h WIFI_SPI_MISO_PIN 궨 +* SCK 鿴 zf_device_wifi_spi.h WIFI_SPI_SCK_PIN 궨 +* MOSI 鿴 zf_device_wifi_spi.h WIFI_SPI_MOSI_PIN 궨 +* 5V 5V Դ +* GND Դ +* +* ------------------------------------ +*********************************************************************************************************************/ + +#include "stdio.h" +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_common_fifo.h" +#include "zf_common_function.h" +#include "zf_driver_delay.h" +#include "zf_driver_gpio.h" +#include "zf_common_interrupt.h" +#include "zf_driver_exti.h" +#include "zf_driver_spi.h" +#include "zf_device_type.h" + +#include "zf_device_wifi_spi.h" + +#define WAIT_TIME_OUT (10000) // ָȴʱ λms + +#define WIFI_SPI_WRITE_MAX 4092 // һSPIͨѶ͵ݳ + +#define WIFI_SPI_WRITE_REQUEST 0x01 +#define WIFI_SPI_CHECK_STATE 0x02 +#define WIFI_SPI_WRITE_DATA 0x03 +#define WIFI_SPI_READ_DATA 0x04 +#define WIFI_SPI_WRITE_END 0x07 +#define WIFI_SPI_READ_END 0x08 + +#define WIFI_SPI_WRITE_ADDR 0x00 +#define WIFI_SPI_STATE_ADDR 0x04 + +volatile wifi_spi_buffer_state_enum wifi_buffer_state; +volatile wifi_spi_transmit_state_enum wifi_transmit_state; + +static fifo_struct wifi_spi_fifo; +static uint8 wifi_spi_buffer[WIFI_SPI_BUFFER_SIZE]; // ݴ + +vuint8 wifi_spi_ack_flag = 0; // 0ģδӦ 1ģӦ +uint8 wifi_spi_init_flag; // 0ģδʼɹδ 1ģӲɹʼ +vuint8 wifi_spi_packet_num; // ͵ݰID +vuint32 wifi_spi_send_remain_length; // ʣķͳ + +uint8 wifi_spi_receive_buffer[WIFI_SPI_WRITE_MAX]; + +wifi_spi_information_struct wifi_spi_information; +//------------------------------------------------------------------------------------------------------------------- +// @brief дݵģ +// @param length Ҫдij +// @return void +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +static void wifi_spi_write_request(uint16 length) +{ + wifi_spi_buffer_struct head; + + head.cmd = WIFI_SPI_WRITE_REQUEST; + head.addr = WIFI_SPI_WRITE_ADDR; + head.dummy = 0x00; + head.magic = 0xFE; + head.sequence = wifi_spi_packet_num++; + head.length = length; + + wifi_transmit_state = TRANSMIT_WRITE_REQUEST; + gpio_set_level(WIFI_SPI_CS_PIN, 0); + spi_write_8bit_array(WIFI_SPI_INDEX, (const uint8 *)&head.cmd, 7); + gpio_set_level(WIFI_SPI_CS_PIN, 1); +} + +//------------------------------------------------------------------------------------------------------------------- +// @brief ȡģ״̬ +// @param *length Ҫȡдij +// @return WIFI_SPI_BUFFER_STATE_enum ģ״̬ +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +static wifi_spi_buffer_state_enum wifi_spi_read_state(uint16 *length) +{ + wifi_spi_buffer_struct head = {0}; + + head.cmd = WIFI_SPI_CHECK_STATE; + head.addr = WIFI_SPI_STATE_ADDR; + head.dummy = 0x00; + + wifi_spi_ack_flag = 0; + wifi_transmit_state = TRANSMIT_READ_STATE; + gpio_set_level(WIFI_SPI_CS_PIN, 0); + spi_transfer_8bit(WIFI_SPI_INDEX, (const uint8 *)&head.cmd, &head.cmd, 7); + gpio_set_level(WIFI_SPI_CS_PIN, 1); + + if(BUFFER_WRITE == head.magic) + { + wifi_spi_packet_num = head.sequence; + } + *length = head.length; + + return (wifi_spi_buffer_state_enum)head.magic; +} + +//------------------------------------------------------------------------------------------------------------------- +// @brief ݷ +// @param void +// @return void +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +static void wifi_spi_send_done(void) +{ + wifi_spi_buffer_struct head; + + head.cmd = WIFI_SPI_WRITE_END; + head.addr = WIFI_SPI_WRITE_ADDR; + head.dummy = 0x00; + + gpio_set_level(WIFI_SPI_CS_PIN, 0); + spi_write_8bit_array(WIFI_SPI_INDEX, (const uint8 *)&head.cmd, 3); + gpio_set_level(WIFI_SPI_CS_PIN, 1); + wifi_transmit_state = TRANSMIT_IDLE; +} + +//------------------------------------------------------------------------------------------------------------------- +// @brief ݽ +// @param void +// @return void +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +static void wifi_spi_receive_done(void) +{ + wifi_spi_buffer_struct head; + + head.cmd = WIFI_SPI_READ_END; + head.addr = WIFI_SPI_WRITE_ADDR; + head.dummy = 0x00; + + gpio_set_level(WIFI_SPI_CS_PIN, 0); + spi_write_8bit_array(WIFI_SPI_INDEX, (const uint8 *)&head.cmd, 3); + gpio_set_level(WIFI_SPI_CS_PIN, 1); + wifi_transmit_state = TRANSMIT_IDLE; +} + +//------------------------------------------------------------------------------------------------------------------- +// @brief ݵģ +// @param *buff Ҫдݵ׵ַ +// @param length Ҫдݵij +// @return void +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +static void wifi_spi_send_data(const uint8 *buff, uint16 length) +{ + wifi_spi_buffer_struct head; + + head.cmd = WIFI_SPI_WRITE_DATA; + head.addr = WIFI_SPI_WRITE_ADDR; + head.dummy = 0x00; + + wifi_transmit_state = TRANSMIT_WRITE; + gpio_set_level(WIFI_SPI_CS_PIN, 0); + spi_write_8bit_array(WIFI_SPI_INDEX, (const uint8 *)&head.cmd, 3); + spi_write_8bit_array(WIFI_SPI_INDEX, buff, length); + gpio_set_level(WIFI_SPI_CS_PIN, 1); + wifi_spi_send_done(); +} + +//------------------------------------------------------------------------------------------------------------------- +// @brief ݵģ飨Դַ +// @param *multi_buffer ԴַԼÿԴַҪ͵ij +// @return void +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +static void wifi_spi_send_data_multi(wifi_spi_send_multi_struct *multi_buffer) +{ + uint8 i; + wifi_spi_buffer_struct head; + + head.cmd = WIFI_SPI_WRITE_DATA; + head.addr = WIFI_SPI_WRITE_ADDR; + head.dummy = 0x00; + + wifi_transmit_state = TRANSMIT_WRITE; + gpio_set_level(WIFI_SPI_CS_PIN, 0); + spi_write_8bit_array(WIFI_SPI_INDEX, (const uint8 *)&head.cmd, 3); + + for(i = 0; i < WIFI_SPI_MAX_MULTI; i++) + { + if(NULL != multi_buffer->source[i]) spi_write_8bit_array(WIFI_SPI_INDEX, multi_buffer->source[i], multi_buffer->length[i]); + } + gpio_set_level(WIFI_SPI_CS_PIN, 1); + wifi_spi_send_done(); +} + +//------------------------------------------------------------------------------------------------------------------- +// @brief ģ鷢͵ +// @param *buff Ļ׵ַ +// @param length Ҫյij +// @return void +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +static void wifi_spi_receive_data(uint8 *buff, uint16 length) +{ + wifi_spi_buffer_struct head; + + head.cmd = WIFI_SPI_READ_DATA; + head.addr = WIFI_SPI_WRITE_ADDR; + head.dummy = 0x00; + + wifi_transmit_state = TRANSMIT_READ; + gpio_set_level(WIFI_SPI_CS_PIN, 0); + spi_transfer_8bit(WIFI_SPI_INDEX, (const uint8 *)&head.cmd, &head.cmd, 3); + spi_transfer_8bit(WIFI_SPI_INDEX, (const uint8 *)buff, buff, length); + gpio_set_level(WIFI_SPI_CS_PIN, 1); + wifi_spi_receive_done(); +} + +//------------------------------------------------------------------------------------------------------------------- +// @brief ģ +// @param *str ַ׵ַ +// @return void +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +static void wifi_spi_send_command(const char *str) +{ + uint8 state = 0; + uint16 send_length; + uint16 wait_time = 0; + + // + send_length = (uint16)strlen(str); + + // ȴ + while(TRANSMIT_IDLE != wifi_transmit_state); + + + // ûн뷢״̬ + while(BUFFER_WRITE != wifi_buffer_state) + { + wifi_spi_ack_flag = 0; + wifi_spi_write_request(send_length); + while(!wifi_spi_ack_flag) + { + wait_time++; + if((WAIT_TIME_OUT / 4) <= wait_time) + { + state = 1; + wifi_spi_init_flag = 0; // ģѶϿ + break; + } + system_delay_ms(1); + } + + if(1 == state) + { + break; + } + } + + wifi_buffer_state = BUFFER_IDLE; + + if(0 == state) // ͨѶδʱ + { + wifi_spi_send_remain_length = send_length; + // Ϣ + wifi_spi_send_data((const uint8 *)str, send_length); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// @brief ģ״̬ȡģ鷢͵ +// @param void +// @return void +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +void wifi_spi_check_state_read_buffer(void) +{ + uint16 wifi_spi_receive_length; // νյ + + // ѯWIFIģ״̬ + wifi_buffer_state = wifi_spi_read_state(&wifi_spi_receive_length); + + // ҪȡWIFIģݣ򱣴Ҫȡij + if(BUFFER_READ == wifi_buffer_state) + { + wifi_spi_receive_data((uint8 *)wifi_spi_receive_buffer, wifi_spi_receive_length); + fifo_write_buffer(&wifi_spi_fifo, wifi_spi_receive_buffer, wifi_spi_receive_length); // FIFO + } + else if(BUFFER_IDLE == wifi_buffer_state) + { + // ģڲ״̬ΪУ״̬ҲΪ + wifi_transmit_state = TRANSMIT_IDLE; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// @brief ݵģ +// @param *buff Ҫ͵׵ַ +// @param length Ҫ͵ij +// @return uint32 ʣδͳ +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +uint32 wifi_spi_write_data(const uint8 *buff, uint32 length) +{ + uint16 send_length; + uint32 wait_time; + + // ¼Ҫ͵ij + wifi_spi_send_remain_length = length; + + while(wifi_spi_send_remain_length) + { + send_length = (uint16)func_limit_ab(wifi_spi_send_remain_length, 1, WIFI_SPI_WRITE_MAX); + + // + wifi_spi_ack_flag = 0; + wifi_spi_write_request(send_length); + + // ȴ5 + wait_time = 5000; + while(!wifi_spi_ack_flag) + { + wait_time--; + if(0 == wait_time) break; + system_delay_ms(1); + } + + if(BUFFER_WRITE == wifi_buffer_state) + { + // Ϣ + wifi_spi_send_data(buff, send_length); + buff += send_length; + wifi_spi_send_remain_length -= send_length; + wifi_buffer_state = BUFFER_IDLE; + } + else + { + break; + } + } + + return wifi_spi_send_remain_length; +} + +//------------------------------------------------------------------------------------------------------------------- +// @brief ݵģ(Դַ) +// @param *multi_buffer ԴַԼÿԴַҪ͵ij +// @return uint32 ʣδͳ +// Sample usage: ܳȲܳ4092 +//------------------------------------------------------------------------------------------------------------------- +uint32 wifi_spi_write_data_multi(wifi_spi_send_multi_struct *multi_buffer) +{ + uint16 send_length; + uint32 wait_time; + + // ¼Ҫ͵ij + send_length = multi_buffer->length[0] + multi_buffer->length[1] + multi_buffer->length[2] + multi_buffer->length[3] + multi_buffer->length[4] + multi_buffer->length[5] + multi_buffer->length[6] + multi_buffer->length[7]; + + if(WIFI_SPI_WRITE_MAX >= send_length) + { + // + wifi_spi_ack_flag = 0; + wifi_spi_write_request(send_length); + + // ȴ5 + wait_time = 5000; + while(!wifi_spi_ack_flag) + { + wait_time--; + if(0 == wait_time) break; + system_delay_ms(1); + } + + if(BUFFER_WRITE == wifi_buffer_state) + { + // Ϣ + wifi_spi_send_data_multi(multi_buffer); + send_length = 0; + wifi_buffer_state = BUFFER_IDLE; + } + } + + return send_length; +} + +//-------------------------------------------------------------------------------------------------- +// ȴģӦ +// ˵ *wait_buffer ȴӦַ +// ˵ timeout ʱʱ +// ز uint8 0ģӦָ 1ģδӦָݻʱ +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_spi_wait_ack (char *wait_buffer, uint32 timeout) +{ + uint8 return_state = 1; + char receiver_buffer[8] = {0, 0, 0, 0, 0, 0, 0, 0}; + uint32 receiver_len = 8; + + do + { + system_delay_ms(1); + // жϽջǷҪӦָ ѭҷ0 + receiver_len = 8; + fifo_read_tail_buffer(&wifi_spi_fifo, (uint8 *)receiver_buffer, &receiver_len, FIFO_READ_ONLY); + + if(strstr(receiver_buffer, wait_buffer)) + { + return_state = 0; + break; + } + else if(strstr(receiver_buffer, "ERROR") || strstr(receiver_buffer, "busy")) + { + // յģæ ѭҷ1 + return_state = 1; + break; + } + }while(timeout --); + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// WiFiջ +// ˵ void +// ز void +// ʹʾ wifi_spi_clear_receive_buffer(); +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static void wifi_spi_clear_receive_buffer (void) +{ + // WiFiջ + fifo_clear(&wifi_spi_fifo); +} + +//-------------------------------------------------------------------------------------------------- +// ģݽ +// ˵ *target_buffer Ŀŵַָ ַ +// ˵ *origin_buffer Դַָ ַ +// ˵ start_char ʼȡֽ "1234" д '2' ʼȡ Ӧ '2' +// ˵ end_char ȡֽ "1234" '4' ȡ Ӧ '\0'(0x00 ַ һַβ) +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_data_parse(wifi_spi_information.mac, wifi_spi_receive_buffer, '"', '"'); // ûȡmacַ󣬵ô˺ȡmacַ +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_spi_data_parse (uint8 *target_buffer, uint8 *origin_buffer, char start_char, char end_char) +{ + uint8 return_state = 0; + char *location1; + char *location2; + location1 = strchr((char *)origin_buffer, start_char); + if(location1) + { + location1 ++; + location2 = strchr(location1, end_char); + if(location2) + { + memcpy(target_buffer, location1, location2-location1); + } + else + { + return_state = 1; + } + } + else + { + return_state = 1; + } + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// 鿴ģ汾Ϣ +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_get_version(); +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_spi_get_version (void) +{ + char *location1; + uint8 return_state = 0; + uint8 receiver_buffer[256]; + uint32 receiver_len = 256; + + wifi_spi_clear_receive_buffer(); // WiFiջ + wifi_spi_send_command("AT+GMR\r\n"); + do + { + + if(wifi_spi_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + break; + } + + fifo_read_buffer(&wifi_spi_fifo, receiver_buffer, &receiver_len, FIFO_READ_ONLY); + location1 = strrchr((char *)receiver_buffer, ':'); + if(wifi_spi_data_parse(wifi_spi_information.version, (uint8 *)location1, ':', '(')) + { + return_state = 1; + break; + } + }while(0); + wifi_spi_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ģ +// ˵ model 0:رģĻд ģд +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_echo_set("1");//ģд +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_spi_echo_set (char *model) +{ + uint8 return_state = 0; + + wifi_spi_clear_receive_buffer(); // WiFiջ + + if('1' == *model) + { + wifi_spi_send_command("ATE1\r\n"); + } + else + { + wifi_spi_send_command("ATE0\r\n"); + } + + return_state = wifi_spi_wait_ack("OK", WAIT_TIME_OUT); + wifi_spi_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ѯģ MAC ַ +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ if(wifi_spi_get_mac()){} +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_spi_get_mac (void) +{ + uint8 return_state = 0; + uint8 receiver_buffer[64]; + uint32 receiver_len = 64; + + wifi_spi_clear_receive_buffer(); // WiFiջ + wifi_spi_send_command("AT+CIPAPMAC?\r\n"); + do + { + if(wifi_spi_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + break; + } + + fifo_read_buffer(&wifi_spi_fifo, receiver_buffer, &receiver_len, FIFO_READ_ONLY); + if(wifi_spi_data_parse(wifi_spi_information.mac, receiver_buffer, '"', '"')) + { + return_state = 1; + break; + } + }while(0); + wifi_spi_clear_receive_buffer(); // WiFiջ + + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ѯģĿWIFI IP ַ(ȡģ鵱ǰĹģʽ) +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ if(wifi_spi_get_ip()){} +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_spi_get_ip (void) +{ + uint8 return_state = 0; + + wifi_spi_clear_receive_buffer(); // WiFiջ + if(WIFI_SPI_STATION == wifi_spi_information.mode) + { + wifi_spi_send_command("AT+CIPSTA?\r\n"); + } + else if(WIFI_SPI_SOFTAP == wifi_spi_information.mode) + { + wifi_spi_send_command("AT+CIPAP?\r\n"); + } + + do + { + if(wifi_spi_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + break; + } + uint8 receiver_buffer[128]; + uint32 receiver_len = 128; + fifo_read_buffer(&wifi_spi_fifo, receiver_buffer, &receiver_len, FIFO_READ_ONLY); + if(wifi_spi_data_parse(wifi_spi_information.local_ip, receiver_buffer, '"', '"')) + { + return_state = 1; + break; + } + }while(0); + wifi_spi_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ѯģϢ +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ if(wifi_spi_get_information()){} +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_spi_get_information (void) +{ + uint8 return_state = 0; + do + { + // ȡģ汾 + if(wifi_spi_get_version()) + { + return_state = 1; + break; + } + // ȡģIPַ + if(wifi_spi_get_ip()) + { + return_state = 1; + break; + } + // ȡģMACϢ + if(wifi_spi_get_mac()) + { + return_state = 1; + break; + } + memcpy(wifi_spi_information.local_port, "no port", 7); + }while(0); + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// WiFi +// ˵ wifi_ssid WiFi +// ˵ pass_word WiFi +// ˵ model 0:ѯWiFi WiFi +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_get_or_connect_wifi("WiFi_name", "Pass_word", 1); +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_spi_set_wifi (char *wifi_ssid, char *pass_word) +{ + char temp[64]; + uint8 return_state = 0; + + wifi_spi_clear_receive_buffer(); // WiFiջ + if(WIFI_SPI_SOFTAP == wifi_spi_information.mode) + { + sprintf(temp, "AT+CWSAP=\"%s\",\"%s\",5,3\r\n", wifi_ssid, pass_word); + wifi_spi_send_command(temp); + } + else + { + sprintf(temp, "AT+CWJAP=\"%s\",\"%s\"\r\n", wifi_ssid, pass_word); + wifi_spi_send_command(temp); + } + return_state = wifi_spi_wait_ack("OK", WAIT_TIME_OUT); + wifi_spi_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ϵǷԶWiFi +// ˵ model 0:ϵ粻Զwifi ϵԶwifi +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_auto_connect_wifi(0); //ϵ粻Զwifi +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_spi_auto_connect_wifi (char *model) +{ + char temp[64]; + uint8 return_state = 0; + + wifi_spi_clear_receive_buffer(); // WiFiջ + sprintf(temp, "AT+CWAUTOCONN=%s\r\n", model); + wifi_spi_send_command(temp); + return_state = wifi_spi_wait_ack("OK", WAIT_TIME_OUT); + wifi_spi_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ģʽ +// ˵ model 0: ģʽ 1ģʽ +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_set_connect_model("1"); +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_spi_set_connect_model (char *model) +{ + char temp[64]; + uint8 return_state = 0; + + wifi_spi_clear_receive_buffer(); // WiFiջ + sprintf(temp, "AT+CIPMUX=%s\r\n", model); + wifi_spi_send_command(temp); + return_state = wifi_spi_wait_ack("OK", WAIT_TIME_OUT); + wifi_spi_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ôģʽ +// ˵ model C 0: ͨģʽ IPϿ +// C 1: Wi-Fi ͸ģʽ֧ TCP ӡUDP ̶ͨŶԶˡSSL ӵ IPϿ᲻ϳ +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_set_transfer_model("1"); +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_spi_set_transfer_model (char *model) +{ + char temp[64]; + uint8 return_state = 0; + + wifi_spi_clear_receive_buffer(); // WiFiջ + sprintf(temp, "AT+CIPMODE=%s\r\n", model); + wifi_spi_send_command(temp); + return_state = wifi_spi_wait_ack("OK", WAIT_TIME_OUT); + wifi_spi_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ģģʽ (Station/SoftAP/Station+SoftAP) +// ˵ state 0: Wi-Fi ģʽҹر Wi-Fi RF----1: Station ģʽ----2: SoftAP ģʽ----3: SoftAP+Station ģʽ +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_set_model("1"); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_spi_set_model (wifi_spi_mode_enum mode) +{ + uint8 return_state = 0; + + wifi_spi_clear_receive_buffer(); // WiFiջ + + if(WIFI_SPI_SOFTAP == mode) + { + wifi_spi_send_command("AT+CWMODE=2\r\n"); + } + else + { + wifi_spi_send_command("AT+CWMODE=1\r\n"); + } + // ģ鹤ģʽ + wifi_spi_information.mode = mode; + return_state = wifi_spi_wait_ack("OK", WAIT_TIME_OUT); + wifi_spi_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// Ͽwifi +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_disconnected_wifi(); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_spi_disconnected_wifi (void) +{ + uint8 return_state = 0; + + wifi_spi_clear_receive_buffer(); // WiFiջ + wifi_spi_send_command("AT+CWQAP\r\n"); + return_state = wifi_spi_wait_ack("OK", WAIT_TIME_OUT); + wifi_spi_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ͸ģʽ +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_entry_serianet(); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_spi_entry_serianet (void) +{ + uint8 return_state = 0; + + wifi_spi_clear_receive_buffer(); // WiFiջ + wifi_spi_send_command("AT+CIPSEND\r\n"); + return_state = wifi_spi_wait_ack("OK", WAIT_TIME_OUT); + wifi_spi_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ˳͸ģʽ +// ˵ model 0:ر͸ģʽ ͸ģʽ +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_exit_serianet(1); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_spi_exit_serianet (void) +{ + wifi_spi_clear_receive_buffer(); // WiFiջ + + system_delay_ms(20); + wifi_spi_send_command("+++"); + system_delay_ms(1000); + + return 0; +} + +//-------------------------------------------------------------------------------------------------- +// TCP +// ˵ ip Զ IPv4 ַIPv6 ַ +// ˵ port Զ˶˿ֵ +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_connect_tcp_servers("192.168.101.110", "8080"); +// עϢ ӲϵԵTCP Գʹӵ +// ʹWiFi ܻᵼģTCPȴϳʱ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_spi_connect_tcp_servers (char *ip, char *port, wifi_spi_transfer_mode_enum mode) +{ + char temp[64]; + uint8 return_state = 0; + + wifi_spi_clear_receive_buffer(); // WiFiջ + do + { + if(wifi_spi_set_connect_model("0")) + { + return_state = 1; + break; + } + + wifi_spi_clear_receive_buffer(); // WiFiջ + sprintf(temp, "AT+CIPSTARTEX=\"TCP\",\"%s\",%s\r\n", ip, port); + wifi_spi_send_command(temp); + + if(wifi_spi_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + wifi_spi_information.connect_state = WIFI_SPI_SERVER_OFF; + break; + } + + wifi_spi_clear_receive_buffer(); // WiFiջ + + // ôģʽ + if(wifi_spi_set_transfer_model(WIFI_SPI_COMMAND == mode ? "0" : "1")) + { + return_state = 1; + break; + } + + wifi_spi_clear_receive_buffer(); // WiFiջ + wifi_spi_send_command("AT+CIPSTATE?\r\n"); + if(wifi_spi_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + break; + } + else + { + uint8 receiver_buffer[128]; + uint32 receiver_len = 128; + fifo_read_buffer(&wifi_spi_fifo, receiver_buffer, &receiver_len, FIFO_READ_ONLY); + char* buffer_index = (char *)receiver_buffer; + char* end_index; + + buffer_index += 22; + buffer_index += strlen(ip); + buffer_index += strlen(port); + end_index = strchr(buffer_index, ','); + + memcpy(wifi_spi_information.local_port, " ", 7); + memcpy(wifi_spi_information.local_port, buffer_index, (end_index - buffer_index)); + } + + wifi_spi_information.connect_state = WIFI_SPI_SERVER_ON; + wifi_spi_information.connect_mode = WIFI_SPI_TCP_CLIENT; + wifi_spi_information.transfer_mode = mode; + + wifi_spi_clear_receive_buffer(); // WiFiջ + if(WIFI_SPI_SERIANET == mode) // ͸ģʽֱӿ͸ + { + if(wifi_spi_entry_serianet()) + { + return_state = 1; + break; + } + } + + }while(0); + wifi_spi_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// UDP +// ˵ *ip Զ IPv4 ַIPv6 ַ ַʽ +// ˵ *port Զ˶˿ֵ ַʽ +// ˵ *local_port Զ IPv4 ַIPv6 ַ ַʽ +// ˵ mode ģͨģʽ +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_connect_udp_client("192.168.101.110", "8080", "8080", WIFI_SPI_COMMAND); +// עϢ ԶID +//-------------------------------------------------------------------------------------------------- +uint8 wifi_spi_connect_udp_client (char *ip, char *port, char *local_port, wifi_spi_transfer_mode_enum mode) +{ + char temp[64]; + uint8 return_state = 0; + + wifi_spi_clear_receive_buffer(); // WiFiջ + do + { + if(wifi_spi_set_connect_model("0")) + { + return_state = 1; + break; + } + + wifi_spi_clear_receive_buffer(); // WiFiջ + + sprintf(temp, "AT+CIPSTARTEX=\"UDP\",\"%s\",%s,%s\r\n", ip, port, local_port); + wifi_spi_send_command(temp); + + if(wifi_spi_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + wifi_spi_information.connect_state = WIFI_SPI_SERVER_OFF; + break; + } + + wifi_spi_clear_receive_buffer(); // WiFiջ + if(wifi_spi_set_transfer_model(WIFI_SPI_COMMAND == mode ? "0" : "1")) // ôģʽ + { + return_state = 1; + break; + } + + wifi_spi_clear_receive_buffer(); // WiFiջ + if(WIFI_SPI_SERIANET == mode) // ͸ģʽֱӿ͸ + { + if(wifi_spi_entry_serianet()) + { + return_state = 1; + break; + } + } + memcpy(wifi_spi_information.local_port, " ", 7); + memcpy(wifi_spi_information.local_port, local_port, strlen(local_port)); + wifi_spi_information.connect_state = WIFI_SPI_SERVER_ON; + wifi_spi_information.connect_mode = WIFI_SPI_UDP_CLIENT; + wifi_spi_information.transfer_mode = mode; + }while(0); + wifi_spi_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// Ͽ TCP Server ʹñӿڽϿ +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_spi_disconnect_link(); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_spi_disconnect_link (void) +{ + uint8 return_state = 0; + + wifi_spi_clear_receive_buffer(); // WiFiջ + do + { + if(WIFI_SPI_TCP_SERVER == wifi_spi_information.connect_mode) + { + wifi_spi_send_command("AT+CIPCLOSE=5\r\n"); + } + else + { + wifi_spi_send_command("AT+CIPCLOSE\r\n"); + } + + if(wifi_spi_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + wifi_spi_information.connect_state = WIFI_SPI_SERVER_OFF; + break; + } + }while(0); + wifi_spi_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// WiFiģ ֽں +// ˵ data Ҫ͵ +// ز uint32 ʣδݳ +// ʹʾ wifi_spi_send_byte(0xa5); +// עϢ ģΪTCPʱݺĬϽݷһģĿͻ +//------------------------------------------------------------------------------------------------------------------- +uint32 wifi_spi_send_byte (uint8 data) +{ + char temp[64]; + uint8 temp_length; + uint16 send_length; + + send_length = 1; + if(wifi_spi_init_flag) + { + if(WIFI_SPI_SERVER_ON == wifi_spi_information.connect_state) + { + if(WIFI_SPI_COMMAND == wifi_spi_information.transfer_mode) + { + wifi_spi_clear_receive_buffer(); // WiFiջ + temp_length = (uint8)sprintf(temp, "AT+CIPSEND="); + + if(WIFI_SPI_TCP_SERVER == wifi_spi_information.connect_mode) + { + temp_length += sprintf(&temp[temp_length], "0,"); + } + + temp_length += sprintf(&temp[temp_length], "%u\r\n", send_length); + + wifi_spi_send_command(temp); + if(0 == wifi_spi_wait_ack("OK", WAIT_TIME_OUT)) // ȴģӦ + { + wifi_spi_clear_receive_buffer(); // WiFiջ + wifi_spi_write_data(&data, send_length); + wifi_spi_wait_ack("bytes", 50); + wifi_spi_clear_receive_buffer(); // WiFiջ + wifi_spi_wait_ack("OK", WAIT_TIME_OUT); + } + + wifi_spi_clear_receive_buffer(); // WiFiջ + } + else + { + send_length = (uint16)wifi_spi_write_data(&data, send_length); + } + } + } + + return send_length; +} + +//------------------------------------------------------------------------------------------------------------------- +// WiFiģ ͻ +// ˵ buff Ҫ͵ݵַ +// ˵ len ͳ +// ز uint32 ʣδݳ +// ʹʾ wifi_spi_send_buffer("123", 3); +// עϢ ģΪTCPʱݺĬϽݷһģĿͻ +//------------------------------------------------------------------------------------------------------------------- +uint32 wifi_spi_send_buffer (const uint8 *buff, uint32 len) +{ + char temp[64]; + uint8 temp_length; + uint16 send_length; + + if(wifi_spi_init_flag) + { + if(WIFI_SPI_SERVER_ON == wifi_spi_information.connect_state) + { + if(WIFI_SPI_COMMAND == wifi_spi_information.transfer_mode) + { + while(len) + { + if((WIFI_SPI_WRITE_MAX * 2) < len) send_length = WIFI_SPI_WRITE_MAX * 2; + else + { + send_length = (uint16)len; + } + len -= send_length; + + wifi_spi_clear_receive_buffer(); // WiFiջ + temp_length = (uint8)sprintf(temp, "AT+CIPSEND="); + + if(WIFI_SPI_TCP_SERVER == wifi_spi_information.connect_mode) + { + temp_length += sprintf(&temp[temp_length], "0,"); + } + + temp_length += sprintf(&temp[temp_length], "%u\r\n", send_length); + + wifi_spi_send_command(temp); + if(0 == wifi_spi_wait_ack("OK", WAIT_TIME_OUT)) // ȴģӦ + { + wifi_spi_clear_receive_buffer(); // WiFiջ + wifi_spi_write_data(buff, send_length); + wifi_spi_wait_ack("bytes", 50); + wifi_spi_clear_receive_buffer(); // WiFiջ + wifi_spi_wait_ack("OK", WAIT_TIME_OUT); + } + buff += send_length; + } + + wifi_spi_clear_receive_buffer(); // WiFiջ + } + else + { + len = wifi_spi_write_data(buff, len); + } + } + } + + return len; +} + +//------------------------------------------------------------------------------------------------------------------- +// WiFiģ ͻ(Դַ) +// @param *multi_buffer ԴַԼÿԴַҪ͵ij +// ز uint32 ʣδݳ +// ʹʾ +// עϢ ҪͶʱô˺ԼĽͨѶʱ䣬ܳȲܳ4092 +//------------------------------------------------------------------------------------------------------------------- +uint32 wifi_spi_send_buffer_multi (wifi_spi_send_multi_struct *multi_buffer) +{ + uint8 i; + uint16 remain_length; + + if(wifi_spi_init_flag) + { + if(WIFI_SPI_SERVER_ON == wifi_spi_information.connect_state) + { + if(WIFI_SPI_COMMAND == wifi_spi_information.transfer_mode) + { + for(i = 0; i < WIFI_SPI_MAX_MULTI; i++) + { + if(multi_buffer->source[i]) wifi_spi_send_buffer(multi_buffer->source[i], multi_buffer->length[i]); + } + } + else + { + remain_length = (uint16)wifi_spi_write_data_multi(multi_buffer); + } + } + } + + return remain_length; +} + +//------------------------------------------------------------------------------------------------------------------- +// WiFiģ ַ +// ˵ *str Ҫ͵ +// ز uint32 ʣδݳ +// ʹʾ wifi_spi_send_string("123"); +// עϢ ģΪTCPʱݺĬϽݷһģĿͻ +//------------------------------------------------------------------------------------------------------------------- +uint32 wifi_spi_send_string (const char *str) +{ + char temp[64]; + uint8 temp_length; + uint16 send_length; + + send_length = (uint16)strlen(str); + if(wifi_spi_init_flag) + { + if(WIFI_SPI_SERVER_ON == wifi_spi_information.connect_state) + { + if(WIFI_SPI_COMMAND == wifi_spi_information.transfer_mode) + { + wifi_spi_clear_receive_buffer(); // WiFiջ + temp_length = (uint8)sprintf(temp, "AT+CIPSEND="); + + if(WIFI_SPI_TCP_SERVER == wifi_spi_information.connect_mode) + { + temp_length += sprintf(&temp[temp_length], "0,"); + } + + temp_length += sprintf(&temp[temp_length], "%u\r\n", send_length); + + wifi_spi_send_command(temp); + if(0 == wifi_spi_wait_ack("OK", WAIT_TIME_OUT)) // ȴģӦ + { + wifi_spi_clear_receive_buffer(); // WiFiջ + wifi_spi_write_data((uint8 *)str, send_length); + wifi_spi_wait_ack("bytes", 50); + wifi_spi_clear_receive_buffer(); // WiFiջ + wifi_spi_wait_ack("OK", WAIT_TIME_OUT); + } + + wifi_spi_clear_receive_buffer(); // WiFiջ + } + else + { + send_length = (uint16)wifi_spi_write_data((uint8 *)str, send_length); + } + } + } + + return send_length; +} + +//------------------------------------------------------------------------------------------------------------------- +// WiFi ģݽպ +// ˵ buffer ݵĴŵַ +// ˵ len 鳤ȣֱдʹsizeof +// ز uint32 ʵʽյݳ +// ʹʾ uint8 test_buffer[256]; wifi_spi_read_buffer(&test_buffer[0], sizeof(test_buffer)); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 wifi_spi_read_buffer (uint8 *buffer, uint32 len) +{ + fifo_read_buffer(&wifi_spi_fifo, buffer, &len, FIFO_READ_AND_CLEAN); + return len; +} + +//-------------------------------------------------------------------------------------------------- +// wifi spi handshakeжϻص +// ˵ void +// ز void +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +void wifi_spi_callback (void) +{ + wifi_spi_check_state_read_buffer(); + wifi_spi_ack_flag = 1; // ACK־λ1 + +} + + +//------------------------------------------------------------------------------------------------------------------- +// WiFi ģʼ +// ˵ *wifi_ssid Ŀӵ WiFi ַʽ +// ˵ *pass_word Ŀӵ WiFi ַʽ +// ˵ wifi_mode ģĹģʽ zf_device_wireless_spi.h wifi_spi_mode_enum ö +// ز uint8 ģʼ״̬ 0-ɹ 1- +// ʹʾ wifi_spi_init("SEEKFREE_2.4G", "SEEKFREEV2", WIFI_UART_STATION); +// עϢ ʼôã֮ģл +// Ϣ zf_device_wireless_spi.h ļ޸ +//------------------------------------------------------------------------------------------------------------------- +uint8 wifi_spi_init (char *wifi_ssid, char *pass_word, wifi_spi_mode_enum wifi_mode) +{ + uint8 return_state = 0; + uint32 temp_isr; + + spi_init(WIFI_SPI_INDEX, SPI_MODE0, WIFI_SPI_SPEED, WIFI_SPI_SCK_PIN, WIFI_SPI_MOSI_PIN, WIFI_SPI_MISO_PIN, SPI_CS_NULL);//ӲSPIʼ + set_wireless_type(WIFI_SPI, wifi_spi_callback); + fifo_init(&wifi_spi_fifo, FIFO_DATA_8BIT, wifi_spi_buffer, WIFI_SPI_BUFFER_SIZE); + + gpio_init(WIFI_SPI_CS_PIN, GPO, 1, GPO_PUSH_PULL); + gpio_init(WIFI_SPI_RST_PIN, GPO, 1, GPO_PUSH_PULL); + + + temp_isr = interrupt_global_disable(); + + exti_init(WIFI_SPI_INT_PIN, EXTI_TRIGGER_RISING); + interrupt_set_priority(EXTI1_IRQn, (0<<5) || 1); + + gpio_set_level(WIFI_SPI_RST_PIN, 0); + system_delay_ms(50); + gpio_set_level(WIFI_SPI_RST_PIN, 1); + system_delay_ms(1000); + + EXTI_ClearITPendingBit(EXTI_Line1); + NVIC_ClearPendingIRQ(EXTI1_IRQn); + interrupt_global_enable(temp_isr); + + do + { + if(wifi_spi_echo_set("0")) // رģд + { + zf_log(0, "exit echo failed"); + return_state = 1; + break; + } + + if(wifi_spi_auto_connect_wifi("0")) // رԶ + { + zf_log(0, "close auto connect failed"); + return_state = 1; + break; + } + + if(wifi_spi_set_model(wifi_mode)) // ģʽ + { + zf_log(0, "set run mode failed"); + return_state = 1; + break; + } + + if(wifi_spi_set_wifi((char *)wifi_ssid, (char *)pass_word)) // wifi ߿ȵ + { + zf_log(0, "wifi set failed"); + return_state = 1; + break; + } + + if(wifi_spi_get_information()) // ģȡ + { + zf_log(0, "get module information failed"); + return_state = 1; + break; + } + // zf_log(0, "seekfree wifi spi init succeed"); +#if WIFI_SPI_AUTO_CONNECT == 1 + if(wifi_spi_connect_tcp_servers(WIFI_SPI_TARGET_IP, WIFI_SPI_TARGET_PORT, WIFI_SPI_SERIANET)) // TCP + { + zf_log(0, "connect TCP server failed"); + return_state = 1; + break; + } + // zf_log(0, "connect TCP client succeed"); +#endif +#if WIFI_SPI_AUTO_CONNECT == 2 + if(wifi_spi_connect_udp_client(WIFI_SPI_TARGET_IP, WIFI_SPI_TARGET_PORT, WIFI_SPI_LOCAL_PORT, WIFI_SPI_SERIANET)) // UDP + { + zf_log(0, "connect UDP server failed"); + return_state = 1; + break; + } + // zf_log(0, "connect UDP server succeed"); +#endif + + // ģʼɹ + wifi_spi_init_flag = 1; + }while(0); + + return return_state; +} diff --git a/libraries/zf_device/zf_device_wifi_spi.h b/libraries/zf_device/zf_device_wifi_spi.h new file mode 100644 index 0000000..e8fb1ba --- /dev/null +++ b/libraries/zf_device/zf_device_wifi_spi.h @@ -0,0 +1,182 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_wifi_spi +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2023-05-25 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* RST 鿴 zf_device_wifi_spi.h WIFI_SPI_RST_PIN 궨 +* INT 鿴 zf_device_wifi_spi.h WIFI_SPI_INT_PIN 궨 +* CS 鿴 zf_device_wifi_spi.h WIFI_SPI_CS_PIN 궨 +* MISO 鿴 zf_device_wifi_spi.h WIFI_SPI_MISO_PIN 궨 +* SCK 鿴 zf_device_wifi_spi.h WIFI_SPI_SCK_PIN 궨 +* MOSI 鿴 zf_device_wifi_spi.h WIFI_SPI_MOSI_PIN 궨 +* 5V 5V Դ +* GND Դ +* +* ------------------------------------ +*********************************************************************************************************************/ + +#ifndef _zf_device_wifi_spi_h +#define _zf_device_wifi_spi_h + +#include "zf_common_typedef.h" + +#define WIFI_SPI_INDEX ( SPI_2 ) // ʹõSPI +#define WIFI_SPI_SPEED ( 20 * 1000 * 1000) // Ӳ SPI +#define WIFI_SPI_SCK_PIN ( SPI2_MAP0_SCK_B13 ) // SPI_SCK +#define WIFI_SPI_MOSI_PIN ( SPI2_MAP0_MOSI_B15 ) // SPI_MOSI +#define WIFI_SPI_MISO_PIN ( SPI2_MAP0_MISO_B14 ) // SPI_MISO IPSûMISOţȻҪ壬spiijʼʱҪʹ +#define WIFI_SPI_CS_PIN ( C0 ) // SPI_CS CS +#define WIFI_SPI_INT_PIN ( C1 ) // ж +#define WIFI_SPI_RST_PIN ( A7 ) // 帴λ + + +#define WIFI_SPI_BUFFER_SIZE ( 1024 ) // SPIյĻС + +#define WIFI_SPI_AUTO_CONNECT ( 0 ) // ǷʼʱTCPUDP 0- 1-ԶTCP͸ģʽ 2-ԶUDP͸ģʽ 3ԶTCP + +#if (WIFI_SPI_AUTO_CONNECT > 2) +#error "WIFI_SPI_AUTO_CONNECT ֵֻΪ [0,1,2]" +#else +#define WIFI_SPI_TARGET_IP "192.168.2.52" // Ŀ IP +#define WIFI_SPI_TARGET_PORT "8080" // ĿĶ˿ +#define WIFI_SPI_LOCAL_PORT "8080" // ˿ +#endif + +#define WIFI_SPI_MAX_MULTI ( 8 ) // ַͣ8ַ + +typedef enum +{ + BUFFER_IDLE, // ģĻǿе + BUFFER_READ, // ģĻҪȡ + BUFFER_WRITE, // ģĻǿд +}wifi_spi_buffer_state_enum; + +typedef enum +{ + TRANSMIT_IDLE, // ǰûд + TRANSMIT_WRITE_REQUEST, // ģ鷢һ + TRANSMIT_READ_STATE, // ȡģ״̬ + TRANSMIT_READ, // ڶȡģڲ + TRANSMIT_WRITE, // ģд +}wifi_spi_transmit_state_enum; + +typedef enum +{ + WIFI_SPI_STATION, // 豸ģʽ + WIFI_SPI_SOFTAP, // APģʽ +}wifi_spi_mode_enum; + +typedef enum +{ + WIFI_SPI_COMMAND, // ʹķʽ + WIFI_SPI_SERIANET, // ʹ͸ķʽ +}wifi_spi_transfer_mode_enum; + +typedef enum +{ + WIFI_SPI_TCP_CLIENT, // ģTCP + WIFI_SPI_TCP_SERVER, // ģΪTCP + WIFI_SPI_UDP_CLIENT, // ģUDP +}wifi_spi_connect_mode_enum; + +typedef enum +{ + WIFI_SPI_SERVER_OFF, // ģδӷ + WIFI_SPI_SERVER_ON, // ģѾӷ +}wifi_spi_connect_state_enum; + +typedef enum +{ + WIFI_SPI_LINK_0, // ģ鵱ǰ 0 + WIFI_SPI_LINK_1, // ģ鵱ǰ 1 + WIFI_SPI_LINK_2, // ģ鵱ǰ 2 + WIFI_SPI_LINK_3, // ģ鵱ǰ 3 + WIFI_SPI_LINK_4, // ģ鵱ǰ 4 +}wifi_spi_link_id_enum; + +typedef struct +{ + uint8 reserve; + uint8 cmd; + uint8 addr; + uint8 dummy; + uint8 magic; + uint8 sequence; + uint16 length; +}wifi_spi_buffer_struct; + +typedef struct +{ + uint8 version[12]; // ̼汾 ַʽ + uint8 mac[20]; // MAC ַ ַʽ + uint8 local_ip[17]; // IP ַ ַʽ + uint8 local_port[10]; // ˿ں ַʽ + uint8 remote_ip[5][17]; // Զ IP ַ ַʽ + wifi_spi_mode_enum mode; // WIFI ģʽ + wifi_spi_transfer_mode_enum transfer_mode; // ǰģʽ + wifi_spi_connect_mode_enum connect_mode; // ģʽ + wifi_spi_connect_state_enum connect_state; // +}wifi_spi_information_struct; + +typedef struct +{ + uint8 *source[WIFI_SPI_MAX_MULTI]; + uint16 length[WIFI_SPI_MAX_MULTI]; +}wifi_spi_send_multi_struct; + +extern wifi_spi_information_struct wifi_spi_information; + + +uint8 wifi_spi_disconnected_wifi (void); // Ͽ WIFI +uint8 wifi_spi_entry_serianet (void); // ͸ģʽ +uint8 wifi_spi_exit_serianet (void); // ر͸ģʽ + +uint8 wifi_spi_connect_tcp_servers (char *ip, char *port, wifi_spi_transfer_mode_enum mode); // TCP +uint8 wifi_spi_connect_udp_client (char *ip, char *port, char *local_port, wifi_spi_transfer_mode_enum mode); // UDP +uint8 wifi_spi_disconnect_link (void); // Ͽ TCP Server ʹñӿڽϿ + + +uint32 wifi_spi_send_byte (uint8 data); // WIFI ģ鷢ֽں +uint32 wifi_spi_send_buffer (const uint8 *buff, uint32 length); // WIFI ģ鷢ͻ +uint32 wifi_spi_send_buffer_multi (wifi_spi_send_multi_struct *multi_buffer); // WIFI ģ鷢Ͷ໺ +uint32 wifi_spi_send_string (const char *str); // WIFI ģ鷢ַ + +uint32 wifi_spi_read_buffer (uint8 *buff, uint32 len); // WIFI ģݽպ + +uint8 wifi_spi_init (char *wifi_ssid, char *pass_word, wifi_spi_mode_enum wifi_mode); // WIFI ģʼ + +#endif + diff --git a/libraries/zf_device/zf_device_wifi_uart.c b/libraries/zf_device/zf_device_wifi_uart.c new file mode 100644 index 0000000..159fd3f --- /dev/null +++ b/libraries/zf_device/zf_device_wifi_uart.c @@ -0,0 +1,1213 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_wifi_uart +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* RX 鿴 zf_device_wifi_uart.h WRIELESS_UART_RX_PINx 궨 +* TX 鿴 zf_device_wifi_uart.h WRIELESS_UART_TX_PINx 궨 +* RTS 鿴 zf_device_wifi_uart.h WRIELESS_UART_RTS_PINx 궨 +* RST 鿴 zf_device_wifi_uart.h WRIELESS_UART_RST_PINx 궨 +* VCC 5V Դ +* GND Դ +* +* ------------------------------------ +*********************************************************************************************************************/ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_common_fifo.h" +#include "zf_common_function.h" +#include "zf_driver_delay.h" +#include "zf_driver_gpio.h" +#include "zf_driver_uart.h" +#include "zf_device_type.h" + +#include "zf_device_wifi_uart.h" + + + +#define WAIT_TIME_OUT (10000) // ָȴʱ λms + +wifi_uart_information_struct wifi_uart_information; // ģ + +static fifo_struct wifi_uart_fifo; +static uint8 wifi_uart_buffer[WIFI_UART_BUFFER_SIZE]; // ݴ +static uint8 wifi_uart_data; + +//-------------------------------------------------------------------------------------------------- +// ȴģӦ +// ˵ *wait_buffer ȴӦַ +// ˵ timeout ʱʱ +// ز uint8 0ģӦָ 1ģδӦָݻʱ +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_uart_wait_ack (char *wait_buffer, uint32 timeout) +{ + uint8 return_state = 1; + char receiver_buffer[8] = {0, 0, 0, 0, 0, 0, 0, 0}; + uint32 receiver_len = 8; + + do + { + system_delay_ms(1); + // жϽջǷҪӦָ ѭҷ0 + receiver_len = 8; + fifo_read_tail_buffer(&wifi_uart_fifo, (uint8 *)receiver_buffer, &receiver_len, FIFO_READ_ONLY); + if(strstr(receiver_buffer, wait_buffer)) + { + return_state = 0; + break; + } + else if(strstr(receiver_buffer, "ERROR") || strstr(receiver_buffer, "busy")) + { + // յģæ ѭҷ1 + return_state = 1; + break; + } + }while(timeout --); + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// WiFiջ +// ˵ void +// ز void +// ʹʾ wifi_uart_clear_receive_buffer(); +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static void wifi_uart_clear_receive_buffer (void) +{ + // WiFiջ + fifo_clear(&wifi_uart_fifo); +} + +//-------------------------------------------------------------------------------------------------- +// ģݽ +// ˵ *target_buffer Ŀŵַָ ַ +// ˵ *origin_buffer Դַָ ַ +// ˵ start_char ʼȡֽ "1234" д '2' ʼȡ Ӧ '2' +// ˵ end_char ȡֽ "1234" '4' ȡ Ӧ '\0'(0x00 ַ һַβ) +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_data_parse(wifi_uart_information.mac, wifi_uart_receive_buffer, '"', '"'); // ûȡmacַ󣬵ô˺ȡmacַ +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_data_parse (uint8 *target_buffer, uint8 *origin_buffer, char start_char, char end_char) +{ + uint8 return_state = 0; + char *location1 = NULL; + char *location2 = NULL; + location1 = strchr((char *)origin_buffer, start_char); + if(location1) + { + location1 ++; + location2 = strchr(location1, end_char); + if(location2) + { + memcpy(target_buffer, location1, location2-location1); + } + else + { + return_state = 1; + } + } + else + { + return_state = 1; + } + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// 鿴ģ汾Ϣ +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_get_version(); +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_uart_get_version (void) +{ + char *location1 = NULL; + uint8 return_state = 0; + uint8 receiver_buffer[256]; + uint32 receiver_len = 256; + + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "AT+GMR\r\n"); + do + { + + if(wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + break; + } + + fifo_read_buffer(&wifi_uart_fifo, receiver_buffer, &receiver_len, FIFO_READ_ONLY); + location1 = strrchr((char *)receiver_buffer, ':'); + if(wifi_data_parse(wifi_uart_information.wifi_uart_version, (uint8 *)location1, ':', '(')) + { + return_state = 1; + break; + } + }while(0); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ģ +// ˵ model 0:رģĻд ģд +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_echo_set("1");//ģд +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_uart_echo_set (char *model) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "ATE"); + uart_write_string(WIFI_UART_INDEX, model); + uart_write_string(WIFI_UART_INDEX, "\r\n"); + return_state = wifi_uart_wait_ack("OK", WAIT_TIME_OUT); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ģĴ +// ˵ baudrate ַ֧ΧΪ 80 ~ 5000000 +// ˵ databits λ 55 bit λ----66 bit λ----77 bit λ----88 bit λ +// ˵ stopbits ֹͣλ 11 bit ֹͣλ----21.5 bit ֹͣλ----32 bit ֹͣλ +// ˵ parity Уλ 0None----1Odd----2Even +// ˵ flow_control 0ʹ----1ʹ RTS----2ʹ CTS----3ͬʱʹ RTS CTS +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_uart_config_set("115200", "8", "1", "0", "1"); +// עϢ ڲ ʱ 粻 +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_uart_uart_config_set (char *baudrate, char *databits, char *stopbits, char *parity, char *flow_control) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "AT+UART_CUR="); + uart_write_string(WIFI_UART_INDEX, baudrate); + uart_write_string(WIFI_UART_INDEX, ","); + uart_write_string(WIFI_UART_INDEX, databits); + uart_write_string(WIFI_UART_INDEX, ","); + uart_write_string(WIFI_UART_INDEX, stopbits); + uart_write_string(WIFI_UART_INDEX, ","); + uart_write_string(WIFI_UART_INDEX, parity); + uart_write_string(WIFI_UART_INDEX, ","); + uart_write_string(WIFI_UART_INDEX, flow_control); + uart_write_string(WIFI_UART_INDEX, "\r\n"); + return_state = wifi_uart_wait_ack("OK", WAIT_TIME_OUT); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ѯģ MAC ַ +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ if(wifi_uart_get_mac()){} +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_uart_get_mac (void) +{ + uint8 return_state = 0; + uint8 receiver_buffer[64]; + uint32 receiver_len = 64; + + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "AT+CIPAPMAC?\r\n"); + do + { + if(wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + break; + } + + fifo_read_buffer(&wifi_uart_fifo, receiver_buffer, &receiver_len, FIFO_READ_ONLY); + if(wifi_data_parse(wifi_uart_information.wifi_uart_mac, receiver_buffer, '"', '"')) + { + return_state = 1; + break; + } + }while(0); + wifi_uart_clear_receive_buffer(); // WiFiջ + + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ѯģĿWIFI IP ַ(ȡģ鵱ǰĹģʽ) +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ if(wifi_uart_get_ip()){} +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_uart_get_ip (void) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + if(WIFI_UART_STATION == wifi_uart_information.wifi_uart_mode) + { + uart_write_string(WIFI_UART_INDEX, "AT+CIPSTA?\r\n"); + } + else if(WIFI_UART_SOFTAP == wifi_uart_information.wifi_uart_mode) + { + uart_write_string(WIFI_UART_INDEX, "AT+CIPAP?\r\n"); + } + + do + { + if(wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + break; + } + uint8 receiver_buffer[128]; + uint32 receiver_len = 128; + fifo_read_buffer(&wifi_uart_fifo, receiver_buffer, &receiver_len, FIFO_READ_ONLY); + if(wifi_data_parse(wifi_uart_information.wifi_uart_local_ip, receiver_buffer, '"', '"')) + { + return_state = 1; + break; + } + }while(0); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ѯģϢ +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ if(wifi_uart_get_information()){} +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_uart_get_information (void) +{ + uint8 return_state = 0; + do + { + // ȡģ汾 + if(wifi_uart_get_version()) + { + return_state = 1; + break; + } + // ȡģIPַ + if(wifi_uart_get_ip()) + { + return_state = 1; + break; + } + // ȡģMACϢ + if(wifi_uart_get_mac()) + { + return_state = 1; + break; + } + memcpy(wifi_uart_information.wifi_uart_local_port, "no port", 7); + }while(0); + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// WiFi +// ˵ wifi_ssid WiFi +// ˵ pass_word WiFi +// ˵ model 0:ѯWiFi WiFi +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_get_or_connect_wifi("WiFi_name", "Pass_word", 1); +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_uart_set_wifi (char *wifi_ssid, char *pass_word) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + if(WIFI_UART_SOFTAP == wifi_uart_information.wifi_uart_mode) + { + uart_write_string(WIFI_UART_INDEX, "AT+CWSAP=\""); + uart_write_string(WIFI_UART_INDEX, wifi_ssid); + uart_write_string(WIFI_UART_INDEX, "\",\""); + uart_write_string(WIFI_UART_INDEX, pass_word); + uart_write_string(WIFI_UART_INDEX, "\",5,3\r\n"); + } + else + { + uart_write_string(WIFI_UART_INDEX, "AT+CWJAP=\""); + uart_write_string(WIFI_UART_INDEX, wifi_ssid); + uart_write_string(WIFI_UART_INDEX, "\",\""); + uart_write_string(WIFI_UART_INDEX, pass_word); + uart_write_string(WIFI_UART_INDEX, "\"\r\n"); + } + return_state = wifi_uart_wait_ack("OK", WAIT_TIME_OUT); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ϵǷԶWiFi +// ˵ model 0:ϵ粻Զwifi ϵԶwifi +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_auto_connect_wifi(0); //ϵ粻Զwifi +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_uart_auto_connect_wifi (char *model) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "AT+CWAUTOCONN="); + uart_write_string(WIFI_UART_INDEX, model); + uart_write_string(WIFI_UART_INDEX, "\r\n"); + return_state = wifi_uart_wait_ack("OK", WAIT_TIME_OUT); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ģʽ +// ˵ model 0: ģʽ 1ģʽ +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_set_connect_model("1"); +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_uart_set_connect_model (char *model) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "AT+CIPMUX="); + uart_write_string(WIFI_UART_INDEX, model); + uart_write_string(WIFI_UART_INDEX, "\r\n"); + return_state = wifi_uart_wait_ack("OK", WAIT_TIME_OUT); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ôģʽ +// ˵ model C 0: ͨģʽ IPϿ +// C 1: Wi-Fi ͸ģʽ֧ TCP ӡUDP ̶ͨŶԶˡSSL ӵ IPϿ᲻ϳ +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_set_transfer_model("1"); +// עϢ ڲ +//-------------------------------------------------------------------------------------------------- +static uint8 wifi_uart_set_transfer_model (char *model) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "AT+CIPMODE="); + uart_write_string(WIFI_UART_INDEX, model); + uart_write_string(WIFI_UART_INDEX, "\r\n"); + return_state = wifi_uart_wait_ack("OK", WAIT_TIME_OUT); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ģλ +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_soft_reset(); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_uart_soft_reset (void) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "+++"); + system_delay_ms(100); + uart_write_string(WIFI_UART_INDEX, "\r\n"); + system_delay_ms(100); + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "AT+RST\r\n"); + return_state = wifi_uart_wait_ack("ready", WAIT_TIME_OUT); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ģӲλ +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_reset(); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_uart_reset (void) +{ +#if WIFI_UART_HARDWARE_RST + uint8 return_state = 0; + + gpio_set_level(WIFI_UART_RST_PIN, 0); + system_delay_ms(50); + gpio_set_level(WIFI_UART_RST_PIN, 1); + system_delay_ms(200); + wifi_uart_clear_receive_buffer(); // WiFiջ + return_state = wifi_uart_wait_ack("ready", WAIT_TIME_OUT); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +#else + return wifi_uart_soft_reset(); +#endif +} + +//-------------------------------------------------------------------------------------------------- +// ģģʽ (Station/SoftAP/Station+SoftAP) +// ˵ state 0: Wi-Fi ģʽҹر Wi-Fi RF----1: Station ģʽ----2: SoftAP ģʽ----3: SoftAP+Station ģʽ +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_set_model("1"); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_uart_set_model (wifi_uart_mode_enum mode) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + if(WIFI_UART_SOFTAP == mode) + { + uart_write_string(WIFI_UART_INDEX, "AT+CWMODE=2\r\n"); + } + else + { + uart_write_string(WIFI_UART_INDEX, "AT+CWMODE=1\r\n"); + } + // ģ鹤ģʽ + wifi_uart_information.wifi_uart_mode = mode; + return_state = wifi_uart_wait_ack("OK", WAIT_TIME_OUT); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// Ͽwifi +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_disconnected_wifi(); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_uart_disconnected_wifi (void) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "AT+CWQAP\r\n"); + return_state = wifi_uart_wait_ack("OK", WAIT_TIME_OUT); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ͸ģʽ +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_entry_serianet(); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_uart_entry_serianet (void) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "AT+CIPSEND\r\n"); + return_state = wifi_uart_wait_ack("OK", WAIT_TIME_OUT); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ˳͸ģʽ +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_exit_serianet(); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_uart_exit_serianet (void) +{ + wifi_uart_clear_receive_buffer(); // WiFiջ + + system_delay_ms(20); + uart_write_string(WIFI_UART_INDEX, "+++"); + system_delay_ms(1000); + + return 0; +} + +//-------------------------------------------------------------------------------------------------- +// TCP +// ˵ ip Զ IPv4 ַIPv6 ַ +// ˵ port Զ˶˿ֵ +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_connect_tcp_servers("192.168.101.110", "8080"); +// עϢ ӲϵԵTCP Գʹӵ +// ʹWiFi ܻᵼģTCPȴϳʱ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_uart_connect_tcp_servers (char *ip, char *port, wifi_uart_transfer_mode_enum mode) +{ + zf_assert(NULL != ip); + zf_assert(NULL != port); + + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + do + { + if(wifi_uart_set_connect_model("0")) + { + return_state = 1; + break; + } + + wifi_uart_clear_receive_buffer(); // WiFiջ + + uart_write_string(WIFI_UART_INDEX, "AT+CIPSTARTEX=\"TCP\",\""); + uart_write_string(WIFI_UART_INDEX, ip); + uart_write_string(WIFI_UART_INDEX, "\","); + uart_write_string(WIFI_UART_INDEX, port); + uart_write_string(WIFI_UART_INDEX, "\r\n"); + if(wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + wifi_uart_information.wifi_uart_connect_state = WIFI_UART_SERVER_OFF; + break; + } + + wifi_uart_clear_receive_buffer(); // WiFiջ + + // ôģʽ + if(wifi_uart_set_transfer_model(WIFI_UART_COMMAND == mode ? "0" : "1")) + { + return_state = 1; + break; + } + + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "AT+CIPSTATE?\r\n"); + if(wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + break; + } + else + { + uint8 receiver_buffer[128]; + uint32 receiver_len = 128; + fifo_read_buffer(&wifi_uart_fifo, receiver_buffer, &receiver_len, FIFO_READ_ONLY); + char* buffer_index = (char *)receiver_buffer; + char* end_index = NULL; + + buffer_index += 22; + buffer_index += strlen(ip); + buffer_index += strlen(port); + end_index = strchr(buffer_index, ','); + + memcpy(wifi_uart_information.wifi_uart_local_port, " ", 7); + memcpy(wifi_uart_information.wifi_uart_local_port, buffer_index, (end_index - buffer_index)); + } + + wifi_uart_information.wifi_uart_connect_state = WIFI_UART_SERVER_ON; + wifi_uart_information.wifi_uart_connect_mode = WIFI_UART_TCP_CLIENT; + wifi_uart_information.wifi_uart_transfer_mode = mode; + + wifi_uart_clear_receive_buffer(); // WiFiջ + if(WIFI_UART_SERIANET == mode) // ͸ģʽֱӿ͸ + { + if(wifi_uart_entry_serianet()) + { + return_state = 1; + break; + } + } + + }while(0); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// UDP +// ˵ *ip Զ IPv4 ַIPv6 ַ ַʽ +// ˵ *port Զ˶˿ֵ ַʽ +// ˵ *local_port Զ IPv4 ַIPv6 ַ ַʽ +// ˵ mode ģͨģʽ +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_connect_udp_client("192.168.101.110", "8080", "8080", WIFI_UART_COMMAND); +// עϢ ԶID +//-------------------------------------------------------------------------------------------------- +uint8 wifi_uart_connect_udp_client (char *ip, char *port, char *local_port, wifi_uart_transfer_mode_enum mode) +{ + zf_assert(NULL != ip); + zf_assert(NULL != port); + zf_assert(NULL != local_port); + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + do + { + if(wifi_uart_set_connect_model("0")) + { + return_state = 1; + break; + } + + wifi_uart_clear_receive_buffer(); // WiFiջ + + uart_write_string(WIFI_UART_INDEX, "AT+CIPSTARTEX=\"UDP\",\""); + uart_write_string(WIFI_UART_INDEX, ip); + uart_write_string(WIFI_UART_INDEX, "\","); + uart_write_string(WIFI_UART_INDEX, port); + uart_write_string(WIFI_UART_INDEX, ","); + uart_write_string(WIFI_UART_INDEX, local_port); + uart_write_string(WIFI_UART_INDEX, "\r\n"); + + if(wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + wifi_uart_information.wifi_uart_connect_state = WIFI_UART_SERVER_OFF; + break; + } + + wifi_uart_clear_receive_buffer(); // WiFiջ + if(wifi_uart_set_transfer_model(WIFI_UART_COMMAND == mode ? "0" : "1")) // ôģʽ + { + return_state = 1; + break; + } + + wifi_uart_clear_receive_buffer(); // WiFiջ + if(WIFI_UART_SERIANET == mode) // ͸ģʽֱӿ͸ + { + if(wifi_uart_entry_serianet()) + { + return_state = 1; + break; + } + } + memcpy(wifi_uart_information.wifi_uart_local_port, " ", 7); + memcpy(wifi_uart_information.wifi_uart_local_port, local_port, strlen(local_port)); + wifi_uart_information.wifi_uart_connect_state = WIFI_UART_SERVER_ON; + wifi_uart_information.wifi_uart_connect_mode = WIFI_UART_UDP_CLIENT; + wifi_uart_information.wifi_uart_transfer_mode = mode; + }while(0); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// Ͽ TCP Server ʹñӿڽϿ +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_disconnect_link(); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_uart_disconnect_link (void) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + do + { + if(WIFI_UART_TCP_SERVER == wifi_uart_information.wifi_uart_connect_mode) + { + uart_write_string(WIFI_UART_INDEX, "AT+CIPCLOSE=5\r\n"); + } + else + { + uart_write_string(WIFI_UART_INDEX, "AT+CIPCLOSE\r\n"); + } + + if(wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + wifi_uart_information.wifi_uart_connect_state = WIFI_UART_SERVER_OFF; + break; + } + }while(0); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// TCP Server Ͽָ TCP/UDP Client зӦ +// ˵ link_id ҪϿĿ +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_disconnect_link_with_id(WIFI_UART_LINK_0); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_uart_disconnect_link_with_id (wifi_uart_link_id_enum link_id) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + do + { + if(WIFI_UART_TCP_SERVER == wifi_uart_information.wifi_uart_connect_mode) + { + uart_write_string(WIFI_UART_INDEX, "AT+CIPCLOSE="); + uart_write_byte(WIFI_UART_INDEX, link_id + 0x30); + uart_write_string(WIFI_UART_INDEX, "\r\n"); + } + else + { + break; + } + + if(wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + wifi_uart_information.wifi_uart_connect_state = WIFI_UART_SERVER_OFF; + break; + } + }while(0); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// TCP +// ˵ *port ˿ֵ ַʽ +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_entry_tcp_servers("80"); +// עϢ ԶID +//-------------------------------------------------------------------------------------------------- +uint8 wifi_uart_entry_tcp_servers (char *port) +{ + zf_assert(NULL != port); + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + do + { + if(wifi_uart_set_transfer_model("0")) // ôģʽΪͨģʽ + { + return_state = 1; + break; + } + wifi_uart_clear_receive_buffer(); // WiFiջ + + if(wifi_uart_set_connect_model("1")) // ģʽΪģʽ + { + return_state = 1; + break; + } + wifi_uart_clear_receive_buffer(); // WiFiջ + + uart_write_string(WIFI_UART_INDEX, "AT+CIPSERVER=1,"); + uart_write_string(WIFI_UART_INDEX, port); + uart_write_string(WIFI_UART_INDEX, "\r\n"); + + if(wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) + { + return_state = 1; + wifi_uart_information.wifi_uart_connect_state = WIFI_UART_SERVER_OFF; + break; + } + memcpy(wifi_uart_information.wifi_uart_local_port, " ", 7); + memcpy(wifi_uart_information.wifi_uart_local_port, port, strlen(port)); + wifi_uart_information.wifi_uart_connect_state = WIFI_UART_SERVER_ON; + wifi_uart_information.wifi_uart_transfer_mode = WIFI_UART_COMMAND; + wifi_uart_information.wifi_uart_connect_mode = WIFI_UART_TCP_SERVER; + }while(0); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// ر TCP +// ˵ void +// ز uint8 0ɹ 1ʧ +// ʹʾ wifi_uart_exit_tcp_servers(); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_uart_exit_tcp_servers (void) +{ + uint8 return_state = 0; + + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "AT+CIPSERVER=0,1\r\n"); + return_state = wifi_uart_wait_ack("OK", WAIT_TIME_OUT); + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} + +//-------------------------------------------------------------------------------------------------- +// TCP Server ģʽ¼鵱ǰ ȡ IP +// ˵ void +// ز uint8 ǰ +// ʹʾ wifi_uart_tcp_servers_check_link(); +// עϢ +//-------------------------------------------------------------------------------------------------- +uint8 wifi_uart_tcp_servers_check_link (void) +{ + uint8 return_value = 0; + uint8 loop_temp = 0; + uint8 linke_index = 0; + + uint8 receiver_buffer[256]; + uint32 receiver_len = 256; + + char* buffer_index = NULL; + char* start_index = NULL; + char* end_index = NULL; + + for(loop_temp = 0; 5 > loop_temp; loop_temp ++) + { + memset(wifi_uart_information.wifi_uart_remote_ip[loop_temp], 0, 15); + } + + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_string(WIFI_UART_INDEX, "AT+CIPSTATE?\r\n"); + + if(0 == wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) + { + fifo_read_buffer(&wifi_uart_fifo, receiver_buffer, &receiver_len, FIFO_READ_ONLY); + buffer_index = (char *)receiver_buffer; + for(loop_temp = 0; 5 > loop_temp; loop_temp ++) + { + start_index = strchr(buffer_index, ':'); + if(NULL == start_index) + { + break; + } + start_index ++; + linke_index = *(start_index) - 0x30; + start_index += 9; + end_index = strchr((const char *)(start_index), '"'); + memset(wifi_uart_information.wifi_uart_remote_ip[linke_index], 0, 15); + memcpy(wifi_uart_information.wifi_uart_remote_ip[linke_index], start_index, (end_index - start_index)); + buffer_index = end_index; + } + } + wifi_uart_clear_receive_buffer(); // WiFiջ + return return_value; +} + +//------------------------------------------------------------------------------------------------------------------- +// WiFi ģ ͺ +// ˵ buff Ҫ͵ݵַ +// ˵ len ͳ +// ز uint32 ʣδݳ +// ʹʾ wifi_uart_send_buffer("123", 3); +// עϢ ģΪTCPʱݺĬϽݷһģĿͻ +//------------------------------------------------------------------------------------------------------------------- +uint32 wifi_uart_send_buffer (const uint8 *buffer, uint32 len) +{ + zf_assert(NULL != buffer); + int32 timeout = WAIT_TIME_OUT; + + char lenth[32] = {0}; + + if(WIFI_UART_SERVER_ON == wifi_uart_information.wifi_uart_connect_state) + { + if(WIFI_UART_COMMAND == wifi_uart_information.wifi_uart_transfer_mode) + { + wifi_uart_clear_receive_buffer(); // WiFiջ + + func_int_to_str(lenth,len); + if(8192 < len) + { + uart_write_string(WIFI_UART_INDEX, "AT+CIPSENDL="); + } + else + { + uart_write_string(WIFI_UART_INDEX, "AT+CIPSEND="); + } + if(WIFI_UART_TCP_SERVER == wifi_uart_information.wifi_uart_connect_mode) + { + uart_write_string(WIFI_UART_INDEX, "0,"); + } + + uart_write_string(WIFI_UART_INDEX, lenth); + uart_write_string(WIFI_UART_INDEX, "\r\n"); + + if(0 == wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) // ȴģӦ + { + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_buffer(WIFI_UART_INDEX, buffer, len); + if(0 == wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) // ȴģӦ + { + len = 0; + } + } + + } + else + { + while(len --) + { + while(gpio_get_level(WIFI_UART_RTS_PIN) && 0 < timeout -- ); // RTSΪ͵ƽ + if(0 >= timeout) + { + break; + } + uart_write_byte(WIFI_UART_INDEX, *buffer); // + buffer ++; + } + } + } + wifi_uart_clear_receive_buffer(); // WiFiջ + return len; +} + +//------------------------------------------------------------------------------------------------------------------- +// WiFi ģΪ TCP ָĿ豸ͺ +// ˵ buff Ҫ͵ݵַ +// ˵ len ͳ +// ˵ id Ŀ client id +// ز uint32 ʣδݳ +// ʹʾ wifi_uart_tcp_servers_send_buffer("123", 3, WIFI_UART_LINK_0); +// עϢ ģΪTCPʱݺĬϽݷһģĿͻ +//------------------------------------------------------------------------------------------------------------------- +uint32 wifi_uart_tcp_servers_send_buffer (uint8 *buff, uint32 len, wifi_uart_link_id_enum id) +{ + zf_assert(NULL != buff); + char lenth[32] = {0}; + + if( WIFI_UART_COMMAND == wifi_uart_information.wifi_uart_transfer_mode && \ + WIFI_UART_TCP_SERVER == wifi_uart_information.wifi_uart_connect_mode) + { + wifi_uart_clear_receive_buffer(); // WiFiջ + + func_int_to_str(lenth,len); + if(8192 < len) + { + uart_write_string(WIFI_UART_INDEX, "AT+CIPSENDL="); + } + else + { + uart_write_string(WIFI_UART_INDEX, "AT+CIPSEND="); + } + + uart_write_byte(WIFI_UART_INDEX, (id + '0')); + uart_write_string(WIFI_UART_INDEX, ","); + + uart_write_string(WIFI_UART_INDEX, lenth); + uart_write_string(WIFI_UART_INDEX, "\r\n"); + + if(0 == wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) // ȴģӦ + { + // ģ + wifi_uart_clear_receive_buffer(); // WiFiջ + uart_write_buffer(WIFI_UART_INDEX, buff, len); + if(0 == wifi_uart_wait_ack("OK", WAIT_TIME_OUT)) // ȴģӦ + { + len = 0; + } + } + } + wifi_uart_clear_receive_buffer(); // WiFiջ + return len; +} + +//------------------------------------------------------------------------------------------------------------------- +// WiFi ģݽպ +// ˵ buffer ݵĴŵַ +// ˵ len 鳤ȣֱдʹsizeof +// ز uint16 ʵʽյݳ +// ʹʾ uint8 test_buffer[256]; wifi_uart_read_buffer(&test_buffer[0], sizeof(test_buffer)); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 wifi_uart_read_buffer (uint8 *buffer, uint32 len) +{ + zf_assert(NULL != buffer); + uint32 read_len = len; + fifo_read_buffer(&wifi_uart_fifo, buffer, &read_len, FIFO_READ_AND_CLEAN); + return read_len; +} + +//-------------------------------------------------------------------------------------------------- +// WiFi ڻص +// ˵ void +// ز void +// ʹʾ wireless_uart_callback(); +// עϢ ú ISR ļ жϳ򱻵 +// ɴжϷ wireless_module_uart_handler() +// wireless_module_uart_handler() ñ +//-------------------------------------------------------------------------------------------------- +void wifi_uart_callback (void) +{ + uart_query_byte(WIFI_UART_INDEX, &wifi_uart_data); // ȡ + fifo_write_buffer(&wifi_uart_fifo, &wifi_uart_data, 1); // FIFO +} + +//------------------------------------------------------------------------------------------------------------------- +// WiFi ģʼ +// ˵ *wifi_ssid Ŀӵ WiFi ַʽ +// ˵ *pass_word Ŀӵ WiFi ַʽ +// ˵ wifi_mode ģĹģʽ zf_device_wireless_uart.h wifi_uart_mode_enum ö +// ز uint8 ģʼ״̬ 0-ɹ 1- +// ʹʾ wifi_uart_init("SEEKFREE_2.4G", "SEEKFREEV2", WIFI_UART_STATION); +// עϢ ʼôã֮ģл +// Ϣ zf_device_wireless_uart.h ļ޸ +//------------------------------------------------------------------------------------------------------------------- +uint8 wifi_uart_init (char *wifi_ssid, char *pass_word, wifi_uart_mode_enum wifi_mode) +{ + zf_assert(NULL != wifi_ssid); + zf_assert(NULL != pass_word); + char uart_baud[32] = {0}; + uint8 return_state = 0; + + // ģ + set_wireless_type(WIFI_UART, wifi_uart_callback); + fifo_init(&wifi_uart_fifo, FIFO_DATA_8BIT, wifi_uart_buffer, WIFI_UART_BUFFER_SIZE); + gpio_init(WIFI_UART_RTS_PIN, GPI, 0, GPI_PULL_UP); // ʼ +#if WIFI_UART_HARDWARE_RST + gpio_init(WIFI_UART_RST_PIN, GPO, 1, GPO_PUSH_PULL); // ʼλ +#endif + uart_init(WIFI_UART_INDEX, 115200, WIFI_UART_RX_PIN, WIFI_UART_TX_PIN); // ʼWiFiģʹõĴ + uart_rx_interrupt(WIFI_UART_INDEX, 1); + do + { + if(wifi_uart_reset()) // ģ + { + // һ RST ŵ + // ûн RST Ӳλ + // ͻһֱ + // Ӳλ ʹλ + // ޷λĻͶϵһ + zf_log(0, "reset failed"); + return_state = 1; + break; + } + func_int_to_str(uart_baud, WIFI_UART_BAUD); // WiFiģʹõIJʲ + if(wifi_uart_uart_config_set(uart_baud, "8", "1", "0", "1")) // ýӿģĹڲ + { + zf_log(0, "set config failed"); + return_state = 1; + break; + } + // ³ʼWiFiģʹõĴ + uart_init(WIFI_UART_INDEX, WIFI_UART_BAUD, WIFI_UART_RX_PIN, WIFI_UART_TX_PIN); + uart_rx_interrupt(WIFI_UART_INDEX, 1); + system_delay_ms(100); + + if(wifi_uart_echo_set("0")) // رģд + { + zf_log(0, "exit echo failed"); + return_state = 1; + break; + } + + if(wifi_uart_auto_connect_wifi("0")) // رԶ + { + zf_log(0, "close auto connect failed"); + return_state = 1; + break; + } + + if(wifi_uart_set_model(wifi_mode)) // ģʽ + { + zf_log(0, "set run mode failed"); + return_state = 1; + break; + } + + if(wifi_uart_set_wifi((char *)wifi_ssid, (char *)pass_word)) // wifi ߿ȵ + { + zf_log(0, "wifi set failed"); + return_state = 1; + break; + } + + if(wifi_uart_get_information()) // ģȡ + { + zf_log(0, "get module information failed"); + return_state = 1; + break; + } + // zf_log(0, "seekfree wifi uart init succeed"); +#if WIFI_UART_AUTO_CONNECT == 1 + if(wifi_uart_connect_tcp_servers(WIFI_UART_TARGET_IP, WIFI_UART_TARGET_PORT,WIFI_UART_COMMAND)) // TCP + { + zf_log(0, "connect TCP server failed"); + return_state = 1; + break; + } + // zf_log(0, "connect TCP client succeed"); +#endif +#if WIFI_UART_AUTO_CONNECT == 2 + if(wifi_uart_connect_udp_transfer(WIFI_UART_TARGET_IP, WIFI_UART_TARGET_PORT, WIFI_UART_LOCAL_PORT, WIFI_UART_SERIANET))// UDP + { + zf_log(0, "connect UDP server failed"); + return_state = 1; + break; + } + // zf_log(0, "connect UDP server succeed"); +#endif +#if WIFI_UART_AUTO_CONNECT == 3 + if(wifi_uart_entry_tcp_servers(WIFI_UART_LOCAL_PORT)) // TCP + { + zf_log(0, "build TCP server failed"); + return_state = 1; + break; + } + // zf_log(0, "build TCP server succeed"); +#endif + }while(0); + + wifi_uart_clear_receive_buffer(); // WiFiջ + + return return_state; +} diff --git a/libraries/zf_device/zf_device_wifi_uart.h b/libraries/zf_device/zf_device_wifi_uart.h new file mode 100644 index 0000000..ed81770 --- /dev/null +++ b/libraries/zf_device/zf_device_wifi_uart.h @@ -0,0 +1,147 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_wifi_uart +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* RX 鿴 zf_device_wifi_uart.h WIFI_UART_RX_PIN 궨 +* TX 鿴 zf_device_wifi_uart.h WIFI_UART_TX_PIN 궨 +* RTS 鿴 zf_device_wifi_uart.h WIFI_UART_RTS_PIN 궨 +* RST 鿴 zf_device_wifi_uart.h WIFI_UART_RST_PIN 궨 +* VCC 5V Դ +* GND Դ +* +* ------------------------------------ +*********************************************************************************************************************/ +#ifndef _zf_device_wifi_uart_h_ +#define _zf_device_wifi_uart_h_ + +#include "zf_common_typedef.h" + +#define WIFI_UART_INDEX (UART_7) // WIFI ģ ʹõĴ +#define WIFI_UART_RX_PIN (UART7_MAP3_TX_E12) // WIFI ģ RX +#define WIFI_UART_TX_PIN (UART7_MAP3_RX_E13) // WIFI ģ TX +#define WIFI_UART_BAUD (115200) // ģ鹤 + +#define WIFI_UART_RTS_PIN (E8) // λ ָʾǰģǷԽ 0-Լ 1-Լ +#define WIFI_UART_HARDWARE_RST (0) // ǷʹӲλ 0-ʹλ 1-ʹӲ RST +#if WIFI_UART_HARDWARE_RST // ʹӲλ ׳ֵƬλ޷ʼģ +#define WIFI_UART_RST_PIN (D10) // Ӳλ +#endif + +#define WIFI_UART_BUFFER_SIZE (256) // ջС + +#define WIFI_UART_AUTO_CONNECT (0) // ǷʼʱTCPUDP 0- 1-ԶTCP 2-ԶUDP 3ԶTCP + +#if (WIFI_UART_AUTO_CONNECT > 3) +#error "WIFI_UART_AUTO_CONNECT ֵֻΪ [0,1,2,3]" +#else +#define WIFI_UART_TARGET_IP "192.168.2.32" // Ŀ IP +#define WIFI_UART_TARGET_PORT "8080" // ĿĶ˿ +#define WIFI_UART_LOCAL_PORT "8080" // ˿ +#endif + +typedef enum +{ + WIFI_UART_STATION, // 豸ģʽ + WIFI_UART_SOFTAP, // APģʽ +}wifi_uart_mode_enum; + +typedef enum +{ + WIFI_UART_COMMAND, // ʹķʽ + WIFI_UART_SERIANET, // ʹ͸ķʽ +}wifi_uart_transfer_mode_enum; + +typedef enum +{ + WIFI_UART_TCP_CLIENT, // ģTCP + WIFI_UART_TCP_SERVER, // ģΪTCP + WIFI_UART_UDP_CLIENT, // ģUDP +}wifi_uart_connect_mode_enum; + +typedef enum +{ + WIFI_UART_SERVER_OFF, // ģδӷ + WIFI_UART_SERVER_ON, // ģѾӷ +}wifi_uart_connect_state_enum; + +typedef enum +{ + WIFI_UART_LINK_0, // ģ鵱ǰ 0 + WIFI_UART_LINK_1, // ģ鵱ǰ 1 + WIFI_UART_LINK_2, // ģ鵱ǰ 2 + WIFI_UART_LINK_3, // ģ鵱ǰ 3 + WIFI_UART_LINK_4, // ģ鵱ǰ 4 +}wifi_uart_link_id_enum; + +typedef struct +{ + uint8 wifi_uart_version[12]; // ̼汾 ַʽ + uint8 wifi_uart_mac[20]; // MAC ַ ַʽ + uint8 wifi_uart_local_ip[17]; // IP ַ ַʽ + uint8 wifi_uart_local_port[10]; // ˿ں ַʽ + uint8 wifi_uart_remote_ip[5][15]; // Զ IP ַ ַʽ + wifi_uart_mode_enum wifi_uart_mode; // WIFI ģʽ + wifi_uart_transfer_mode_enum wifi_uart_transfer_mode; // ǰģʽ + wifi_uart_connect_mode_enum wifi_uart_connect_mode; // ģʽ + wifi_uart_connect_state_enum wifi_uart_connect_state; // +}wifi_uart_information_struct; + +extern wifi_uart_information_struct wifi_uart_information; + + +uint8 wifi_uart_disconnected_wifi (void); // Ͽ WIFI +uint8 wifi_uart_entry_serianet (void); // ͸ģʽ +uint8 wifi_uart_exit_serianet (void); // ر͸ģʽ + +uint8 wifi_uart_connect_tcp_servers (char *ip, char *port, wifi_uart_transfer_mode_enum mode); // TCP +uint8 wifi_uart_connect_udp_client (char *ip, char *port, char *local_port, wifi_uart_transfer_mode_enum mode); // UDP +uint8 wifi_uart_disconnect_link (void); // Ͽ TCP Server ʹñӿڽϿ +uint8 wifi_uart_disconnect_link_with_id (wifi_uart_link_id_enum link_id); // TCP Server Ͽָ TCP/UDP Client зӦ + +uint8 wifi_uart_entry_tcp_servers (char *port); // TCP +uint8 wifi_uart_exit_tcp_servers (void); // ر TCP +uint8 wifi_uart_tcp_servers_check_link (void); // TCP Server ģʽ¼鵱ǰ ȡ IP + +uint32 wifi_uart_send_buffer (const uint8 *buffer, uint32 len); // WIFI ģݷͺ +uint32 wifi_uart_tcp_servers_send_buffer (uint8 *buff, uint32 len, wifi_uart_link_id_enum id); // WIFI ģΪ TCP Server ָĿ豸ͺ +uint32 wifi_uart_read_buffer (uint8 *buffer, uint32 len); // WIFI ģݽպ + +void wifi_uart_callback (void); // WIFI ģ鴮ڻص +uint8 wifi_uart_init (char *wifi_ssid, char *pass_word, wifi_uart_mode_enum wifi_mode); // WIFI ģʼ + + +#endif diff --git a/libraries/zf_device/zf_device_wireless_ch573.c b/libraries/zf_device/zf_device_wireless_ch573.c new file mode 100644 index 0000000..dfcaf01 --- /dev/null +++ b/libraries/zf_device/zf_device_wireless_ch573.c @@ -0,0 +1,181 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_wireless_ch573 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* RX 鿴 zf_device_wireless_ch573.h WIRELESS_CH573_RX_PIN 궨 +* TX 鿴 zf_device_wireless_ch573.h WIRELESS_CH573_TX_PIN 궨 +* RTS 鿴 zf_device_wireless_ch573.h WIRELESS_CH573_RTS_PIN 궨 +* VCC 5V Դ +* GND Դ +* +* ------------------------------------ +*********************************************************************************************************************/ + +#include "zf_common_fifo.h" +#include "zf_device_type.h" +#include "zf_device_wireless_ch573.h" + +static fifo_struct wireless_ch573_fifo; +static uint8 wireless_ch573_buffer[WIRELESS_CH573_BUFFER_SIZE]; // Ӧһ ߴ ݴ + +static uint8 wireless_ch573_data; + +//------------------------------------------------------------------------------------------------------------------- +// CH573ģжϻص +// ˵ void +// ز void +// Sample usage: +// @note +//------------------------------------------------------------------------------------------------------------------- +void wireless_ch573_callback (void) +{ + uart_query_byte(WIRELESS_CH573_INDEX, &wireless_ch573_data); + fifo_write_buffer(&wireless_ch573_fifo, &wireless_ch573_data, 1); + +} + + +//------------------------------------------------------------------------------------------------------------------- +// תģ +// ˵ data 8bit +// ز uint32 ʣ෢ͳ +// Sample usage: +//------------------------------------------------------------------------------------------------------------------- +uint32 wireless_ch573_send_byte (const uint8 data) +{ + uint16 time_count = 0; + while(gpio_get_level(WIRELESS_CH573_RTS_PIN)) // RTSΪ͵ƽ + { + if(time_count++ > WIRELESS_CH573_TIMEOUT_COUNT) + return 1; // ģæ,ǰʹwhileȴ ʹúע͵whileȴ滻if + system_delay_ms(1); + } + uart_write_byte(WIRELESS_CH573_INDEX, data); // + + return 0; +} + +//------------------------------------------------------------------------------------------------------------------- +// CH573ģ ڷ +// ˵ buff ݵַ +// ˵ len ݳ +// ز uint32 ʾϢ +// Sample usage: +// @note +//------------------------------------------------------------------------------------------------------------------- +uint32 wireless_ch573_send_buff (const uint8 *buff, uint32 len) +{ + uint16 time_count = 0; + uint8 pack_len = 62; + while(len > pack_len) + { + time_count = 0; + while(gpio_get_level(WIRELESS_CH573_RTS_PIN) && time_count++ < WIRELESS_CH573_TIMEOUT_COUNT) // RTSΪ͵ƽ + system_delay_ms(1); + if(time_count >= WIRELESS_CH573_TIMEOUT_COUNT) + return len; // ģæ,ǰʹwhileȴ ʹúע͵whileȴ滻if + uart_write_buffer(WIRELESS_CH573_INDEX, buff, 30); + + buff += pack_len; // ַƫ + len -= pack_len; // + } + + time_count = 0; + while(gpio_get_level(WIRELESS_CH573_RTS_PIN) && time_count++ < WIRELESS_CH573_TIMEOUT_COUNT) // RTSΪ͵ƽ + system_delay_ms(1); + if(time_count >= WIRELESS_CH573_TIMEOUT_COUNT) + return len; // ģæ,ǰʹwhileȴ ʹúע͵whileȴ滻if + uart_write_buffer(WIRELESS_CH573_INDEX, buff, len); // + + return 0; +} + +//------------------------------------------------------------------------------------------------------------------- +// CH573ģ ڽ +// ˵ buff ݵַ +// ˵ len ݳ +// ز void +// Sample usage: +// @note +//------------------------------------------------------------------------------------------------------------------- +uint32 wireless_ch573_read_buff (uint8 *buff, uint32 len) +{ + uint32 data_len = len; + fifo_read_buffer(&wireless_ch573_fifo, buff, &data_len, FIFO_READ_AND_CLEAN); + return data_len; +} + + +//------------------------------------------------------------------------------------------------------------------- +// תģ ͷͼλ鿴ͼ +// ˵ *image_addr Ҫ͵ͼַ +// ˵ image_size ͼĴС +// ز void +// ʹʾ wireless_uart_send_image(&mt9v03x_image[0][0], MT9V03X_IMAGE_SIZE); +//------------------------------------------------------------------------------------------------------------------- +void wireless_ch573_send_image (const uint8 *image_addr, uint32 image_size) +{ + extern uint8 camera_send_image_frame_header[4]; + wireless_ch573_send_buff(camera_send_image_frame_header, 4); + wireless_ch573_send_buff((uint8 *)image_addr, image_size); +} + +//------------------------------------------------------------------------------------------------------------------- +// CH573ģʼ +// ˵ void +// ز void +// Sample usage: +// @note +//------------------------------------------------------------------------------------------------------------------- +uint8 wireless_ch573_init (void) +{ + + set_wireless_type(WIRELESS_CH573, wireless_ch573_callback); + + + + fifo_init(&wireless_ch573_fifo, FIFO_DATA_8BIT, wireless_ch573_buffer, WIRELESS_CH573_BUFFER_SIZE); + gpio_init(WIRELESS_CH573_RTS_PIN, GPI, GPIO_HIGH, GPI_PULL_UP); + + uart_init (WIRELESS_CH573_INDEX, WIRELESS_CH573_BUAD_RATE, WIRELESS_CH573_RX_PIN, WIRELESS_CH573_TX_PIN); + uart_rx_interrupt(WIRELESS_CH573_INDEX, 1); + + return 0; +} + + + diff --git a/libraries/zf_device/zf_device_wireless_ch573.h b/libraries/zf_device/zf_device_wireless_ch573.h new file mode 100644 index 0000000..206d97b --- /dev/null +++ b/libraries/zf_device/zf_device_wireless_ch573.h @@ -0,0 +1,80 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_wireless_ch573 +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* RX 鿴 zf_device_wireless_ch573.h WIRELESS_CH573_RX_PIN 궨 +* TX 鿴 zf_device_wireless_ch573.h WIRELESS_CH573_TX_PIN 궨 +* RTS 鿴 zf_device_wireless_ch573.h WIRELESS_CH573_RTS_PIN 궨 +* VCC 5V Դ +* GND Դ +* +* ------------------------------------ +*********************************************************************************************************************/ + + +#ifndef _zf_device_wireless_ch573_h_ +#define _zf_device_wireless_ch573_ + + +#include "zf_driver_gpio.h" +#include "zf_driver_uart.h" +#include "zf_driver_delay.h" + + + +#define WIRELESS_CH573_NUMBER 1 // CH573ģ Ĭ +#define WIRELESS_CH573_INDEX UART_2 // CH573ģ1 ӦʹõĴں +#define WIRELESS_CH573_BUAD_RATE 115200 // CH573ģ1 ӦʹõĴڲ +#define WIRELESS_CH573_TX_PIN UART2_MAP1_RX_D6 // CH573ģ1 Ӧģ TX ҪӵƬ RX +#define WIRELESS_CH573_RX_PIN UART2_MAP1_TX_D5 // CH573ģ1 Ӧģ RX ҪӵƬ TX +#define WIRELESS_CH573_RTS_PIN E10 // CH573ģ1 Ӧģ RTS + + +#define WIRELESS_CH573_BUFFER_SIZE 64 +#define WIRELESS_CH573_TIMEOUT_COUNT 0x64 + + + +void wireless_ch573_callback (void); +uint32 wireless_ch573_send_byte (const uint8 data); +uint32 wireless_ch573_send_buff (const uint8 *buff, uint32 len); +uint32 wireless_ch573_send_string (const uint8 *str); +void wireless_ch573_send_image (const uint8 *image_addr, uint32 image_size); +uint32 wireless_ch573_read_buff (uint8 *buff, uint32 len); +uint8 wireless_ch573_init (void); + +#endif diff --git a/libraries/zf_device/zf_device_wireless_uart.c b/libraries/zf_device/zf_device_wireless_uart.c new file mode 100644 index 0000000..7bd9406 --- /dev/null +++ b/libraries/zf_device/zf_device_wireless_uart.c @@ -0,0 +1,295 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_wireless_uart +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* RX 鿴 zf_device_wireless_uart.h WIRELESS_UART_RX_PIN 궨 +* TX 鿴 zf_device_wireless_uart.h WIRELESS_UART_TX_PIN 궨 +* RTS 鿴 zf_device_wireless_uart.h WIRELESS_UART_RTS_PIN 궨 +* VCC 3.3VԴ +* GND Դ +* +* ------------------------------------ +*********************************************************************************************************************/ + +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_common_fifo.h" +#include "zf_driver_delay.h" +#include "zf_driver_gpio.h" +#include "zf_driver_uart.h" +#include "zf_device_type.h" +#include "zf_device_wireless_uart.h" + +static fifo_struct wireless_uart_fifo; +static uint8 wireless_uart_buffer[WIRELESS_UART_BUFFER_SIZE]; + +static uint8 wireless_uart_data = 0; +#if (1 == WIRELESS_UART_AUTO_BAUD_RATE) +static volatile wireless_uart_auto_baudrate_state_enum wireless_auto_baud_flag = WIRELESS_UART_AUTO_BAUD_RATE_INIT; +static volatile uint8 wireless_auto_baud_data[3] = {0x00, 0x01, 0x03}; +#endif + +//------------------------------------------------------------------------------------------------------------------- +// תģ +// ˵ data 8bit +// ز uint32 ʣ෢ͳ 0- 1-δ +// ʹʾ wireless_uart_send_byte(data); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 wireless_uart_send_byte (const uint8 data) +{ + uint16 time_count = WIRELESS_UART_TIMEOUT_COUNT; + while(time_count) + { + if(!gpio_get_level(WIRELESS_UART_RTS_PIN)) + { + uart_write_byte(WIRELESS_UART_INDEX, data); // + break; + } + time_count --; + system_delay_ms(1); + } + return (0 == time_count); +} + +//------------------------------------------------------------------------------------------------------------------- +// תģ ݿ +// ˵ *buff ͻ +// ˵ len ݳ +// ز uint32 ʣ෢ͳ +// ʹʾ wireless_uart_send_buffer(buff, 64); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 wireless_uart_send_buffer (const uint8 *buff, uint32 len) +{ + zf_assert(NULL != buff); + uint16 time_count = 0; + while(0 != len) + { + if(!gpio_get_level(WIRELESS_UART_RTS_PIN)) // RTSΪ͵ƽ + { + if(30 <= len) // ݷ 30byte ÿ + { + uart_write_buffer(WIRELESS_UART_INDEX, buff, 30); // + buff += 30; // ַƫ + len -= 30; // + time_count = 0; + } + else // 30byte һԷ + { + uart_write_buffer(WIRELESS_UART_INDEX, buff, len); // + len = 0; + break; + } + } + else // RTSΪߵƽ ģæ + { + if(WIRELESS_UART_TIMEOUT_COUNT <= (++ time_count)) // ȴʱ + { + break; // ˳ + } + system_delay_ms(1); + } + } + return len; +} + +//------------------------------------------------------------------------------------------------------------------- +// תģ ַ +// ˵ *str Ҫ͵ַַ +// ز uint32 ʣ෢ͳ +// ʹʾ wireless_uart_send_string("Believe in yourself."); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 wireless_uart_send_string (const char *str) +{ + zf_assert(NULL != str); + uint16 time_count = 0; + uint32 len = strlen(str); + while(0 != len) + { + if(!gpio_get_level(WIRELESS_UART_RTS_PIN)) // RTSΪ͵ƽ + { + if(30 <= len) // ݷ 30byte ÿ + { + uart_write_buffer(WIRELESS_UART_INDEX, (const uint8 *)str, 30); // + str += 30; // ַƫ + len -= 30; // + time_count = 0; + } + else // 30byte һԷ + { + uart_write_buffer(WIRELESS_UART_INDEX, (const uint8 *)str, len);// + len = 0; + break; + } + } + else // RTSΪߵƽ ģæ + { + if(WIRELESS_UART_TIMEOUT_COUNT <= (++ time_count)) // ȴʱ + { + break; // ˳ + } + system_delay_ms(1); + } + } + return len; +} + +//------------------------------------------------------------------------------------------------------------------- +// תģ ͷͼλ鿴ͼ +// ˵ *image_addr Ҫ͵ͼַ +// ˵ image_size ͼĴС +// ز void +// ʹʾ wireless_uart_send_image(&mt9v03x_image[0][0], MT9V03X_IMAGE_SIZE); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void wireless_uart_send_image (const uint8 *image_addr, uint32 image_size) +{ + zf_assert(NULL != image_addr); + extern uint8 camera_send_image_frame_header[4]; + wireless_uart_send_buffer(camera_send_image_frame_header, 4); + wireless_uart_send_buffer((uint8 *)image_addr, image_size); +} + +//------------------------------------------------------------------------------------------------------------------- +// תģ ȡ +// ˵ *buff ջ +// ˵ len ȡݳ +// ز uint32 ʵʶȡݳ +// ʹʾ wireless_uart_read_buffer(buff, 32); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint32 wireless_uart_read_buffer (uint8 *buff, uint32 len) +{ + zf_assert(NULL != buff); + uint32 data_len = len; + fifo_read_buffer(&wireless_uart_fifo, buff, &data_len, FIFO_READ_AND_CLEAN); + return data_len; +} + +//------------------------------------------------------------------------------------------------------------------- +// תģ жϻص +// ˵ void +// ز void +// ʹʾ wireless_uart_callback(); +// עϢ ú ISR ļ жϳ򱻵 +// ɴжϷ wireless_module_uart_handler() +// wireless_module_uart_handler() ñ +//------------------------------------------------------------------------------------------------------------------- +void wireless_uart_callback (void) +{ + uart_query_byte(WIRELESS_UART_INDEX, &wireless_uart_data); + fifo_write_buffer(&wireless_uart_fifo, &wireless_uart_data, 1); +#if WIRELESS_UART_AUTO_BAUD_RATE // Զ + if(WIRELESS_UART_AUTO_BAUD_RATE_START == wireless_auto_baud_flag && 3 == fifo_used(&wireless_uart_fifo)) + { + uint32 wireless_auto_baud_count = 3; + wireless_auto_baud_flag = WIRELESS_UART_AUTO_BAUD_RATE_GET_ACK; + fifo_read_buffer(&wireless_uart_fifo, (uint8 *)wireless_auto_baud_data, (uint32 *)&wireless_auto_baud_count, FIFO_READ_AND_CLEAN); + } +#endif +} + +//------------------------------------------------------------------------------------------------------------------- +// תģ ʼ +// ˵ void +// ز void +// ʹʾ wireless_uart_init(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 wireless_uart_init (void) +{ + uint8 return_state = 0; + set_wireless_type(WIRELESS_UART, wireless_uart_callback); + + fifo_init(&wireless_uart_fifo, FIFO_DATA_8BIT, wireless_uart_buffer, WIRELESS_UART_BUFFER_SIZE); + gpio_init(WIRELESS_UART_RTS_PIN, GPI, GPIO_HIGH, GPI_PULL_UP); +#if(0 == WIRELESS_UART_AUTO_BAUD_RATE) // رԶ + // ʹõIJΪ115200 ΪתģĬϲ ģ鲢޸ĴڵIJ + uart_init (WIRELESS_UART_INDEX, WIRELESS_UART_BUAD_RATE, WIRELESS_UART_RX_PIN, WIRELESS_UART_TX_PIN); // ʼ + uart_rx_interrupt(WIRELESS_UART_INDEX, 1); +#elif(1 == WIRELESS_UART_AUTO_BAUD_RATE) // Զ + uint8 rts_init_status = 0; + uint16 time_count = 0; + + wireless_auto_baud_flag = WIRELESS_UART_AUTO_BAUD_RATE_INIT; + wireless_auto_baud_data[0] = 0; + wireless_auto_baud_data[1] = 1; + wireless_auto_baud_data[2] = 3; + + rts_init_status = gpio_get_level(WIRELESS_UART_RTS_PIN); + gpio_init(WIRELESS_UART_RTS_PIN, GPO, rts_init_status, GPO_PUSH_PULL); // ʼ + + uart_init (WIRELESS_UART_INDEX, WIRELESS_UART_BUAD_RATE, WIRELESS_UART_RX_PIN, WIRELESS_UART_TX_PIN); // ʼ + uart_rx_interrupt(WIRELESS_UART_INDEX, 1); + + system_delay_ms(5); // ģϵ֮Ҫʱȴ + gpio_set_level(WIRELESS_UART_RTS_PIN, !rts_init_status); // RTSߣԶģʽ + system_delay_ms(100); // RTS֮ʱ20ms + gpio_toggle_level(WIRELESS_UART_RTS_PIN); // RTSȡ + + do + { + wireless_auto_baud_flag = WIRELESS_UART_AUTO_BAUD_RATE_START; + uart_write_byte(WIRELESS_UART_INDEX, wireless_auto_baud_data[0]); // ض ģԶжϲ + uart_write_byte(WIRELESS_UART_INDEX, wireless_auto_baud_data[1]); // ض ģԶжϲ + uart_write_byte(WIRELESS_UART_INDEX, wireless_auto_baud_data[2]); // ض ģԶжϲ + system_delay_ms(20); + + if(WIRELESS_UART_AUTO_BAUD_RATE_GET_ACK != wireless_auto_baud_flag) // ԶǷ + { + return_state = 1; // 뵽 ˵Զʧ + break; + } + + time_count = 0; + if( 0xa5 != wireless_auto_baud_data[0] && // ԶǷȷ + 0xff != wireless_auto_baud_data[1] && // ԶǷȷ + 0xff != wireless_auto_baud_data[2] ) // ԶǷȷ + { + return_state = 1; // 뵽 ˵Զʧ + break; + } + wireless_auto_baud_flag = WIRELESS_UART_AUTO_BAUD_RATE_SUCCESS; + + gpio_init(WIRELESS_UART_RTS_PIN, GPI, 0, GPI_PULL_UP); // ʼ + system_delay_ms(10); // ʱȴ ģ׼ + }while(0); +#endif + return return_state; +} diff --git a/libraries/zf_device/zf_device_wireless_uart.h b/libraries/zf_device/zf_device_wireless_uart.h new file mode 100644 index 0000000..1be51a4 --- /dev/null +++ b/libraries/zf_device/zf_device_wireless_uart.h @@ -0,0 +1,100 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_device_wireless_uart.h +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +/********************************************************************************************************************* +* ߶壺 +* ------------------------------------ +* ģܽ Ƭܽ +* RX 鿴 zf_device_wireless_uart.h WIRELESS_UART_RX_PIN 궨 +* TX 鿴 zf_device_wireless_uart.h WIRELESS_UART_TX_PIN 궨 +* RTS 鿴 zf_device_wireless_uart.h WIRELESS_UART_RTS_PIN 궨 +* VCC 3.3VԴ +* GND Դ +* +* ------------------------------------ +*********************************************************************************************************************/ + + +#ifndef _zf_device_wireless_uart_h_ +#define _zf_device_wireless_uart_h_ + +#include "zf_common_typedef.h" + +#define WIRELESS_UART_INDEX UART_7 // ߴڶӦʹõĴں +#define WIRELESS_UART_BUAD_RATE 115200 // ߴڶӦʹõĴڲ +#define WIRELESS_UART_TX_PIN UART7_MAP3_RX_E13 // ߴڶӦģ TX ҪӵƬ RX +#define WIRELESS_UART_RX_PIN UART7_MAP3_TX_E12 // ߴڶӦģ RX ҪӵƬ TX +#define WIRELESS_UART_RTS_PIN E8 // ߴڶӦģ RTS + + +// ------------------------------------ Զ ------------------------------------ +// ע1תģ汾V2.0µ޷Զʵġ +// ע2ԶRTS Ὺʧܡ +// ע3ģԶʧܵĻ ԳԶϵ + +// ԶĶ ע +// ԶĶ ע +// ԶĶ ע + +// 0رԶ +// 1Զ Զʵ޸ WIRELESS_UART_BAUD ֮Ҫģ ģԶΪӦIJ + +#define WIRELESS_UART_AUTO_BAUD_RATE ( 0 ) + +#if (1 == WIRELESS_UART_AUTO_BAUD_RATE) +typedef enum +{ + WIRELESS_UART_AUTO_BAUD_RATE_SUCCESS, + WIRELESS_UART_AUTO_BAUD_RATE_INIT, + WIRELESS_UART_AUTO_BAUD_RATE_START, + WIRELESS_UART_AUTO_BAUD_RATE_GET_ACK, +}wireless_uart_auto_baudrate_state_enum; +#endif +// ------------------------------------ Զ ------------------------------------ + +#define WIRELESS_UART_BUFFER_SIZE ( 64 ) +#define WIRELESS_UART_TIMEOUT_COUNT ( 0x64 ) + +uint32 wireless_uart_send_byte (const uint8 data); +uint32 wireless_uart_send_buffer (const uint8 *buff, uint32 len); +uint32 wireless_uart_send_string (const char *str); +void wireless_uart_send_image (const uint8 *image_addr, uint32 image_size); + +uint32 wireless_uart_read_buffer (uint8 *buff, uint32 len); + +void wireless_uart_callback (void); + +uint8 wireless_uart_init (void); + +#endif diff --git a/libraries/zf_driver/zf_driver_adc.c b/libraries/zf_driver/zf_driver_adc.c new file mode 100644 index 0000000..3c8f0d5 --- /dev/null +++ b/libraries/zf_driver/zf_driver_adc.c @@ -0,0 +1,139 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_adc +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "ch32v30x.h" +#include "ch32v30x_adc.h" + +#include "zf_driver_adc.h" +#include "zf_driver_gpio.h" + +#include "zf_common_debug.h" + + +static ADC_TypeDef *adc_index[2] = {ADC1, ADC2}; +static uint8 adc_resolution[2] = {ADC_12BIT, ADC_12BIT}; + + +//------------------------------------------------------------------------------------------------------------------- +// ADCתһ +// ˵ ch ѡADCͨ +// ˵ resolution ֱ(8λ 10λ 12λ) +// ز void +// ʹʾ adc_convert(ADC_IN0_A0, ADC_8BIT); //ɼA0˿ڷ8λֱʵADֵ +//------------------------------------------------------------------------------------------------------------------- +uint16 adc_convert (adc_channel_enum ch) +{ + uint8 adc = ((ch & 0xF000) >> 12); + uint8 adc_ch = (uint8)(ch >> 8) & 0xF; + + ADC_RegularChannelConfig(adc_index[adc], adc_ch, 1, ADC_SampleTime_41Cycles5); // ʹܶӦͨ + ADC_SoftwareStartConvCmd(adc_index[adc], ENABLE); // ʼת + while(!ADC_GetFlagStatus(adc_index[adc], ADC_FLAG_EOC )); // ȴת + return ((adc_index[adc]->RDATAR) >> adc_resolution[adc]); // ȡ +} + +//------------------------------------------------------------------------------------------------------------------- +// ADCתNΣƽֵ˲ +// ˵ ch ѡADCͨ +// ˵ resolution ֱ(8λ 10λ 12λ) +// ˵ count ת +// ز void +// ʹʾ adc_mean_filter(ADC_IN0_A0, ADC_8BIT,5); //ɼA0˿ڷ8λֱʵADֵɼȡƽֵ +//------------------------------------------------------------------------------------------------------------------- +uint16 adc_mean_filter_convert (adc_channel_enum ch, const uint8 count) +{ + uint8 i; + uint32 sum; + + zf_assert(count);//ԴΪ0 + + sum = 0; + for(i=0; i> 12); + gpio_init(ch&0xFF, GPI, 0, GPI_ANAOG_IN); // GPIOʼ + + if(adc == 0) + { + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 , ENABLE ); // ʹADC1ͨʱ + } + else if(adc == 1) + { + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2 , ENABLE ); // ʹADC2ͨʱ + } + + RCC_ADCCLKConfig(RCC_PCLK2_Div8); + + +// if(system_clock > 84000000) RCC_ADCCLKConfig(RCC_PCLK2_Div8); // ADCƵӣADCʲܳ14M +// else RCC_ADCCLKConfig(RCC_PCLK2_Div6); + + ADC_DeInit(adc_index[adc]); + ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; // ADCģʽ:ADC1ڶģʽ + ADC_InitStructure.ADC_ScanConvMode = DISABLE; // ģתڵͨģʽ + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; // ģתڵתģʽ + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; // תⲿ + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; // ADCҶ + ADC_InitStructure.ADC_NbrOfChannel = 1; // ˳йתADCͨĿ + ADC_Init(adc_index[adc], &ADC_InitStructure); // ADC_InitStructָIJʼADCxļĴ + + ADC_Cmd(adc_index[adc], ENABLE); // ʹָADC1 + ADC_BufferCmd(adc_index[adc], DISABLE); // disable buffer + + ADC_ResetCalibration(adc_index[adc]); // ʹܸλУ׼ + while(ADC_GetResetCalibrationStatus(adc_index[adc])); // ȴλУ׼ + ADC_StartCalibration(adc_index[adc]); // ADУ׼ + while(ADC_GetCalibrationStatus(adc_index[adc])); // ȴУ׼ + //ADC_BufferCmd(ADC1, ENABLE); // enable buffer + + adc_resolution[adc] = resolution; // ¼ADC ڲɼʱʹ +} diff --git a/libraries/zf_driver/zf_driver_adc.h b/libraries/zf_driver/zf_driver_adc.h new file mode 100644 index 0000000..b565751 --- /dev/null +++ b/libraries/zf_driver/zf_driver_adc.h @@ -0,0 +1,102 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_adc +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_adc_h +#define _zf_driver_adc_h + +#include "zf_driver_gpio.h" +#include "zf_common_typedef.h" +//CH32V307ֻһADCԷʱںܶͨ + + +//öٶ岻û޸ +typedef enum // öADCͨ +{ + ADC1_IN0_A0 = 0x0000, // 0x 0[ADC1] 0[CH00] 00[A0] + ADC1_IN1_A1 = 0x0101, // 0x 0[ADC1] 1[CH00] 01[A1] + ADC1_IN2_A2 = 0x0202, // 0x 0[ADC1] 2[CH00] 02[A2] + ADC1_IN3_A3 = 0x0303, // 0x 0[ADC1] 3[CH00] 03[A3] + ADC1_IN4_A4 = 0x0404, // 0x 0[ADC1] 4[CH00] 04[A4] + ADC1_IN5_A5 = 0x0505, // 0x 0[ADC1] 5[CH00] 05[A5] + ADC1_IN6_A6 = 0x0606, // 0x 0[ADC1] 6[CH00] 06[A6] + ADC1_IN7_A7 = 0x0707, // 0x 0[ADC1] 7[CH00] 07[A7] + ADC1_IN8_B0 = 0x0820, // 0x 0[ADC1] 8[CH00] 20[B0] + ADC1_IN9_B1 = 0x0921, // 0x 0[ADC1] 9[CH00] 21[B1] + ADC1_IN10_C0 = 0x0A40, // 0x 0[ADC1] A[CH00] 40[C0] + ADC1_IN11_C1 = 0x0B41, // 0x 0[ADC1] B[CH00] 41[C1] + ADC1_IN12_C2 = 0x0C42, // 0x 0[ADC1] C[CH00] 42[C2] + ADC1_IN13_C3 = 0x0D43, // 0x 0[ADC1] D[CH00] 43[C3] + ADC1_IN14_C4 = 0x0E44, // 0x 0[ADC1] E[CH00] 44[C4] + ADC1_IN15_C5 = 0x0F45, // 0x 0[ADC1] F[CH00] 45[C5] + + + ADC2_IN0_A0 = 0x1000, // 0x 1[ADC2] 0[CH00] 00[A0] + ADC2_IN1_A1 = 0x1101, // 0x 1[ADC2] 1[CH00] 01[A1] + ADC2_IN2_A2 = 0x1202, // 0x 1[ADC2] 2[CH00] 02[A2] + ADC2_IN3_A3 = 0x1303, // 0x 1[ADC2] 3[CH00] 03[A3] + ADC2_IN4_A4 = 0x1404, // 0x 1[ADC2] 4[CH00] 04[A4] + ADC2_IN5_A5 = 0x1505, // 0x 1[ADC2] 5[CH00] 05[A5] + ADC2_IN6_A6 = 0x1606, // 0x 1[ADC2] 6[CH00] 06[A6] + ADC2_IN7_A7 = 0x1707, // 0x 1[ADC2] 7[CH00] 07[A7] + ADC2_IN8_B0 = 0x1820, // 0x 1[ADC2] 8[CH00] 20[B0] + ADC2_IN9_B1 = 0x1921, // 0x 1[ADC2] 9[CH00] 21[B1] + ADC2_IN10_C0 = 0x1A40, // 0x 1[ADC2] A[CH00] 40[C0] + ADC2_IN11_C1 = 0x1B41, // 0x 1[ADC2] B[CH00] 41[C1] + ADC2_IN12_C2 = 0x1C42, // 0x 1[ADC2] C[CH00] 42[C2] + ADC2_IN13_C3 = 0x1D43, // 0x 1[ADC2] D[CH00] 43[C3] + ADC2_IN14_C4 = 0x1E44, // 0x 1[ADC2] E[CH00] 44[C4] + ADC2_IN15_C5 = 0x1F45, // 0x 1[ADC2] F[CH00] 45[C5] +}adc_channel_enum; + + +//öٶ岻û޸ +typedef enum // öADCͨ +{ + ADC_8BIT = 4, //8λֱ + ADC_9BIT = 3, //9λֱ + ADC_10BIT = 2, //10λֱ + ADC_11BIT = 1, //11λֱ + ADC_12BIT = 0, //12λֱ +}adc_resolution_enum; + + + + +uint16 adc_convert (adc_channel_enum ch); +uint16 adc_mean_filter_convert (adc_channel_enum ch, const uint8 count); +void adc_init (adc_channel_enum ch, adc_resolution_enum resolution); + + +#endif diff --git a/libraries/zf_driver/zf_driver_delay.c b/libraries/zf_driver/zf_driver_delay.c new file mode 100644 index 0000000..6cb3568 --- /dev/null +++ b/libraries/zf_driver/zf_driver_delay.c @@ -0,0 +1,85 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_delay +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "ch32v30x.h" + +#include "zf_common_clock.h" + +#include "zf_driver_delay.h" + +//------------------------------------------------------------------------------------------------------------------- +// system ʱ ms +// ˵ time Ҫʱʱ ms +// ز void +// ʹʾ system_delay_ms(100); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void system_delay_ms (uint32 num) +{ + SysTick->SR &= ~(1 << 0); + + + SysTick->CMP = (uint64_t)(system_clock/8000) * num; + SysTick->CTLR |= (1 << 4); + SysTick->CTLR |= (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + + SysTick->CTLR &= ~(1 << 0); +} + + +//------------------------------------------------------------------------------------------------------------------- +// system ʱ us +// ˵ time Ҫʱʱ us +// ز void +// ʹʾ system_delay_us(100); +// עϢ ڳת ʱֵ߳һЩ +//------------------------------------------------------------------------------------------------------------------- +void system_delay_us (uint32 num) +{ + SysTick->SR &= ~(1 << 0); + + + SysTick->CMP = (uint64_t)(system_clock/8000000) * num; + SysTick->CTLR |= (1 << 4); + SysTick->CTLR |= (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + + SysTick->CTLR &= ~(1 << 0); +} + + diff --git a/libraries/zf_driver/zf_driver_delay.h b/libraries/zf_driver/zf_driver_delay.h new file mode 100644 index 0000000..aee667f --- /dev/null +++ b/libraries/zf_driver/zf_driver_delay.h @@ -0,0 +1,45 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_delay +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_delay_h +#define _zf_driver_delay_h + +#include "zf_common_clock.h" +#include "zf_common_typedef.h" + +void system_delay_ms (uint32 time); +void system_delay_us (uint32 time); + +#endif diff --git a/libraries/zf_driver/zf_driver_dvp.c b/libraries/zf_driver/zf_driver_dvp.c new file mode 100644 index 0000000..f6965e9 --- /dev/null +++ b/libraries/zf_driver/zf_driver_dvp.c @@ -0,0 +1,106 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_dvp +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "zf_driver_delay.h" +#include "zf_driver_gpio.h" +#include "zf_driver_dvp.h" + +//vuint32 frame_cnt = 0; +//vuint32 addr_cnt = 0; +//vuint32 href_cnt = 0; + +//------------------------------------------------------------------------------------------------------------------- +// dvpӿųʼ +// ˵ dvp_d0dvp_d0 ͷD0-D7 +// ˵ dvp_pclk ͷPCLK +// ˵ dvp_vsync ͷvysnc +// ˵ dvp_herf ͷherf +// ز void +// ʹʾ ڲʹãû +//------------------------------------------------------------------------------------------------------------------- +void dvp_gpio_init( + uint8 dvp_d0,uint8 dvp_d1,uint8 dvp_d2,uint8 dvp_d3, + uint8 dvp_d4,uint8 dvp_d5,uint8 dvp_d6,uint8 dvp_d7, + uint8 dvp_pclk,uint8 dvp_vsync,uint8 dvp_hsync) +{ + //DVP_D0 DVP_ D7 + gpio_init(dvp_d0, GPI, 0, GPI_PULL_UP); + gpio_init(dvp_d1, GPI, 0, GPI_PULL_UP); + gpio_init(dvp_d2, GPI, 0, GPI_PULL_UP); + gpio_init(dvp_d3, GPI, 0, GPI_PULL_UP); + gpio_init(dvp_d4, GPI, 0, GPI_PULL_UP); + gpio_init(dvp_d5, GPI, 0, GPI_PULL_UP); + gpio_init(dvp_d6, GPI, 0, GPI_PULL_UP); + gpio_init(dvp_d7, GPI, 0, GPI_PULL_UP); + //DVP_VSYNC + gpio_init(dvp_vsync, GPI, 0, GPI_PULL_UP); + //DVP_PCLK + gpio_init(dvp_pclk, GPI, 0, GPI_PULL_UP); + //DVP_HSYNC + gpio_init(dvp_hsync, GPI, 0, GPI_PULL_UP); +} + +//------------------------------------------------------------------------------------------------------------------- +// dvpӿڳʼ +// ˵ *image0 buff0ĵַ +// ˵ *image1 buff1ĵַ +// ˵ col_len г +// ˵ row_len г +// ز void +// ʹʾ ڲʹãû +//------------------------------------------------------------------------------------------------------------------- +void dvp_camera_init(uint32 *image0_addr, uint32 *image1_addr, uint16 col_len, uint16 row_len) +{ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DVP, ENABLE); + + // ʹ8λɼģʽPCLKزݣHSYNCߵƽЧVSYNCߵƽЧʹDVP + DVP->CR0 = RB_DVP_D8_MOD | RB_DVP_V_POLAR | RB_DVP_ENABLE; + // ֡ͼģʽʹDMA + DVP->CR1 = DVP_RATE_100P | RB_DVP_DMA_EN; + + DVP->ROW_NUM = row_len; // rows + DVP->COL_NUM = col_len; // cols + + DVP->DMA_BUF0 = (uint32)image0_addr; // DMA addr0 + DVP->DMA_BUF1 = (uint32)image1_addr; // DMA addr1 + + // ʹж + DVP->IER = RB_DVP_IE_FRM_DONE; // ֡ж + + interrupt_set_priority(DVP_IRQn, 0x0); + interrupt_enable(DVP_IRQn); + +} + diff --git a/libraries/zf_driver/zf_driver_dvp.h b/libraries/zf_driver/zf_driver_dvp.h new file mode 100644 index 0000000..a2d3996 --- /dev/null +++ b/libraries/zf_driver/zf_driver_dvp.h @@ -0,0 +1,54 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_dvp +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_dvp_h +#define _zf_driver_dvp_h + +#include "ch32v30x.h" +#include "stdio.h" + +#include "ch32v30x_rcc.h" +#include "ch32v30x_gpio.h" + +#include "zf_common_interrupt.h" +#include "zf_common_typedef.h" + + +void dvp_camera_init(uint32 *image0_addr, uint32 *image1_addr, uint16 col_len, uint16 row_len); +void dvp_gpio_init( + uint8 dvp_d0,uint8 dvp_d1,uint8 dvp_d2,uint8 dvp_d3, + uint8 dvp_d4,uint8 dvp_d5,uint8 dvp_d6,uint8 dvp_d7, + uint8 dvp_pclk,uint8 dvp_vsync,uint8 dvp_hsync); +#endif diff --git a/libraries/zf_driver/zf_driver_encoder.c b/libraries/zf_driver/zf_driver_encoder.c new file mode 100644 index 0000000..c36d173 --- /dev/null +++ b/libraries/zf_driver/zf_driver_encoder.c @@ -0,0 +1,261 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_encoder +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "zf_driver_gpio.h" +#include "zf_driver_timer.h" +#include "zf_driver_encoder.h" + + +static volatile uint8 encoder_dir_pin[10] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + +//------------------------------------------------------------------------------------------------------------------- +// ʱȡֵ +// ˵ timer_ch ʱö +// ز void +// עϢ +// ʹʾ encoder_get_count(TIM2_ENCOEDER) // ȡʱ2IJɼı +//------------------------------------------------------------------------------------------------------------------- +int16 encoder_get_count(encoder_index_enum encoder_n) +{ + int16 result = 0; + int16 return_value = 0; + switch(encoder_n) + { + case TIM1_ENCOEDER: result = TIM1->CNT; break; + case TIM2_ENCOEDER: result = TIM2->CNT; break; + case TIM3_ENCOEDER: result = TIM3->CNT; break; + case TIM4_ENCOEDER: result = TIM4->CNT; break; + case TIM5_ENCOEDER: result = TIM5->CNT; break; + case TIM8_ENCOEDER: result = TIM8->CNT; break; + case TIM9_ENCOEDER: result = TIM9->CNT; break; + case TIM10_ENCOEDER: result = TIM10->CNT; break; + default: result = 0; break; + } + if(0xFF == encoder_dir_pin[encoder_n]) + { + return_value = result; + } + else + { + if(!gpio_get_level((gpio_pin_enum)encoder_dir_pin[encoder_n])) + { + return_value = -result; + } + else + { + return_value = result; + } + } + + return return_value; +} + +//------------------------------------------------------------------------------------------------------------------- +// ʱļ +// ˵ timer_ch ʱö +// ز void +// עϢ +// ʹʾ encoder_clear_count(TIM1_ENCOEDER) //ʱ1ɼı +//------------------------------------------------------------------------------------------------------------------- +void encoder_clear_count(encoder_index_enum encoder_n) +{ + switch(encoder_n) + { + case TIM1_ENCOEDER: TIM1->CNT = 0; break; + case TIM2_ENCOEDER: TIM2->CNT = 0; break; + case TIM3_ENCOEDER: TIM3->CNT = 0; break; + case TIM4_ENCOEDER: TIM4->CNT = 0; break; + case TIM5_ENCOEDER: TIM5->CNT = 0; break; + case TIM8_ENCOEDER: TIM8->CNT = 0; break; + case TIM9_ENCOEDER: TIM9->CNT = 0; break; + case TIM10_ENCOEDER: TIM10->CNT = 0; break; + default: break; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// ʼ +// ˵ timer_ch ʱö +// ˵ phaseA ͨAԼ +// ˵ phaseB ͨBԼ +// ز void +// עϢ Ƽʹ +// ʹʾ encoder_init_quad(TIM1_ENCOEDER, TIM1_CH1_ENCOEDER_E9, TIM1_CH2_ENCOEDER_E11) +// // ʹöʱ1 룬 ͨ1źE9ͨ2źE11 +//------------------------------------------------------------------------------------------------------------------- +void encoder_quad_init(encoder_index_enum encoder_n, encoder_channel_enum ch1_pin, encoder_channel_enum ch2_pin) +{ + uint32 register_temp = 0; + TIM_TypeDef *tim_index; + + // ˶Ϣ ʾλ + // ȥ鿴ʲôط Ĵ + // ǼǷظʹöʱ + // ʼ TIM1_PWM Ȼֳʼ TIM1_ENCODER ÷Dz + zf_assert(timer_funciton_check((timer_index_enum)encoder_n, TIMER_FUNCTION_ENCODER)); + zf_assert((ch1_pin >> 12) == (encoder_n)); // ch1_pin ch2_pin encoder_n ƥ + zf_assert((ch2_pin >> 12) == (encoder_n)); // ch1_pin ch2_pin encoder_n ƥ + + timer_clock_enable(encoder_n); // ʱʱʹ + + gpio_init((gpio_pin_enum)(ch1_pin & 0xFF), GPI, 0, GPI_PULL_UP); // ʼ + gpio_init((gpio_pin_enum)(ch2_pin & 0xFF), GPI, 0, GPI_PULL_UP); // ʼ + + //encoder_dir_pin[encoder_n] = (ch1_pin &0xFF); // źŴ + + switch(encoder_n) + { + case TIM1_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM1_BASE); break; + case TIM2_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM2_BASE); break; + case TIM3_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM3_BASE); break; + case TIM4_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM4_BASE); break; + case TIM5_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM5_BASE); break; + case TIM8_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM8_BASE); break; + case TIM9_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM9_BASE); break; + case TIM10_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM10_BASE); break; + default: register_temp = 1; + } + + // ù + if((ch1_pin >> 8) == 0x03) GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE); + else if((ch1_pin >> 8) == 0x11) GPIO_PinRemapConfig(GPIO_PartialRemap1_TIM2, ENABLE); + else if((ch1_pin >> 8) == 0x22) GPIO_PinRemapConfig(GPIO_PartialRemap_TIM3, ENABLE); + else if((ch1_pin >> 8) == 0x23) GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE); + else if((ch1_pin >> 8) == 0x31) GPIO_PinRemapConfig(GPIO_Remap_TIM4, ENABLE); + else if((ch1_pin >> 8) == 0x71) GPIO_PinRemapConfig(GPIO_Remap_TIM8, ENABLE); + else if((ch1_pin >> 8) == 0x83) GPIO_PinRemapConfig(GPIO_FullRemap_TIM9, ENABLE); + else if((ch1_pin >> 8) == 0x91) GPIO_PinRemapConfig(GPIO_PartialRemap_TIM10, ENABLE); + else if((ch1_pin >> 8) == 0x93) GPIO_PinRemapConfig(GPIO_FullRemap_TIM10, ENABLE); + + if(!register_temp) + { + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); // ʹAFIOùģʱ + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure = {0}; + TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); + TIM_TimeBaseStructure.TIM_Prescaler = 0; // ԤƵ + TIM_TimeBaseStructure.TIM_Period = 0xFFFF; // 趨Զװֵ + TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1; // ѡʱӷƵƵ + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; // TIMϼ + TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; // ظ + TIM_TimeBaseInit(tim_index, &TIM_TimeBaseStructure); // ʼṹ + TIM_ITRxExternalClockConfig(tim_index, TIM_TS_TI2FP2); // ⲿ򲻻 + TIM_Cmd(tim_index, ENABLE); // ʱʹ + + TIM_EncoderInterfaceConfig( + tim_index, + TIM_EncoderMode_TI2 , + TIM_ICPolarity_Rising, + TIM_ICPolarity_Rising); // ʹñģʽ, T2 ,T1жϷ, ؼ + + TIM_Cmd(tim_index, ENABLE); // ʱʹ + + } + +} + + +//------------------------------------------------------------------------------------------------------------------- +// ʼ +// ˵ timer_ch ʱö +// ˵ phaseA ͨAԼ +// ˵ phaseB ͨBԼ +// ز void +// Ƽʹ +// ʹʾ encoder_init_dir(TIM1_ENCOEDER, TIM1_CH1_ENCOEDER_E9, TIM1_CH2_ENCOEDER_E11) +// // ʹöʱ1 ı룬 ͨ1źE9ͨ2źE11 +//------------------------------------------------------------------------------------------------------------------- +void encoder_dir_init(encoder_index_enum encoder_n, encoder_channel_enum ch1_pin, encoder_channel_enum ch2_pin) +{ + uint32 register_temp = 0; + TIM_TypeDef *tim_index; + + // ˶Ϣ ʾλ + // ȥ鿴ʲôط Ĵ + // ǼǷظʹöʱ + // ʼ TIM1_PWM Ȼֳʼ TIM1_ENCODER ÷Dz + zf_assert(timer_funciton_check((timer_index_enum)encoder_n, TIMER_FUNCTION_ENCODER)); + zf_assert((ch1_pin & (encoder_n << 12)) == (encoder_n << 12)); // ch1_pin ch2_pin encoder_n ƥ + zf_assert((ch2_pin & (encoder_n << 12)) == (encoder_n << 12)); // ch1_pin ch2_pin encoder_n ƥ + + timer_clock_enable(encoder_n); // ʱʱʹ + + gpio_init((gpio_pin_enum)(ch1_pin & 0xFF), GPI, 0, GPI_PULL_UP); // ʼ + gpio_init((gpio_pin_enum)(ch2_pin & 0xFF), GPI, 0, GPI_PULL_UP); // ʼ + + encoder_dir_pin[encoder_n] = (ch1_pin &0xFF); // źŴ + + switch(encoder_n) + { + case TIM1_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM1_BASE); break; + case TIM2_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM2_BASE); break; + case TIM3_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM3_BASE); break; + case TIM4_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM4_BASE); break; + case TIM5_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM5_BASE); break; + case TIM8_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM8_BASE); break; + case TIM9_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM9_BASE); break; + case TIM10_ENCOEDER: tim_index = ((TIM_TypeDef *)TIM10_BASE); break; + default: register_temp = 1; + } + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); // ʹAFIOùģʱ + + // ù + if((ch1_pin >> 8) == 0x03) GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE); + else if((ch1_pin >> 8) == 0x11) GPIO_PinRemapConfig(GPIO_PartialRemap1_TIM2, ENABLE); + else if((ch1_pin >> 8) == 0x22) GPIO_PinRemapConfig(GPIO_PartialRemap_TIM3, ENABLE); + else if((ch1_pin >> 8) == 0x23) GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE); + else if((ch1_pin >> 8) == 0x31) GPIO_PinRemapConfig(GPIO_Remap_TIM4, ENABLE); + else if((ch1_pin >> 8) == 0x71) GPIO_PinRemapConfig(GPIO_Remap_TIM8, ENABLE); + else if((ch1_pin >> 8) == 0x83) GPIO_PinRemapConfig(GPIO_FullRemap_TIM9, ENABLE); + else if((ch1_pin >> 8) == 0x91) GPIO_PinRemapConfig(GPIO_PartialRemap_TIM10, ENABLE); + else if((ch1_pin >> 8) == 0x93) GPIO_PinRemapConfig(GPIO_FullRemap_TIM10, ENABLE); + + if(!register_temp) + { + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure = {0}; + TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); + TIM_TimeBaseStructure.TIM_Prescaler = 0; // ԤƵ + TIM_TimeBaseStructure.TIM_Period = 0xFFFF; // 趨Զװֵ + TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1; // ѡʱӷƵƵ + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; // TIMϼ + TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; // ظ + TIM_TimeBaseInit(tim_index, &TIM_TimeBaseStructure); // ʼṹ + TIM_ITRxExternalClockConfig(tim_index, TIM_TS_TI2FP2); // ⲿ򲻻 + TIM_ETRConfig(tim_index, TIM_ExtTRGPSC_OFF, TIM_ExtTRGPolarity_NonInverted, 15); // ƵFsampling=Fdts/32N=8 + TIM_Cmd(tim_index, ENABLE); // ʱʹ + } +} + diff --git a/libraries/zf_driver/zf_driver_encoder.h b/libraries/zf_driver/zf_driver_encoder.h new file mode 100644 index 0000000..e96a38b --- /dev/null +++ b/libraries/zf_driver/zf_driver_encoder.h @@ -0,0 +1,176 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_encoder +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_encoder_h +#define _zf_driver_encoder_h + +#include "ch32v30x_rcc.h" +#include "ch32v30x_gpio.h" +#include "ch32v30x_tim.h" + +#include "zf_common_debug.h" +#include "zf_common_typedef.h" + +typedef enum // TIMERö +{ + // MAP0 Ĭӳ + // MAP1 ӳ + // MAP2 ӳ + // MAP3 ȫӳ + + //----------ʱ1---------- + // ΪTIM1һͨӳŻá + // 磺TIM1_ENCOEDER_MAP_CH1_A8TIM1_ENCOEDER_MAP_CH2_E11һʹá + // ֻTIM1_ENCOEDER_MAP_CH1_A8TIM1_ENCOEDER_MAP_CH2_A9 ͬӳһʹã + // TIM1_ENCOEDER_MAP_CH1_E9TIM1_ENCOEDER_MAP_CH2_E11 ͬӳһʹ + // Ĭӳ + TIM1_ENCOEDER_MAP0_CH1_A8 = 0x0000 | A8, // 0x 0[TIM1] 0[MAP0] 08[A8 ] + TIM1_ENCOEDER_MAP0_CH2_A9 = 0x0000 | A9, // 0x 0[TIM1] 0[MAP0] 09[A9 ] + + // ΪTIM1һͨӳŻá + // ȫӳ + TIM1_ENCOEDER_MAP3_CH1_E9 = 0x0300 | E9, // 0x 0[TIM1] 3[MAP3] 89[E9 ] + TIM1_ENCOEDER_MAP3_CH2_E11 = 0x0300 | E11, // 0x 0[TIM1] 3[MAP3] 8B[E11] + + //----------ʱ2---------- + + // ΪTIM2һͨӳŻá + // Ĭӳ + TIM2_ENCOEDER_MAP0_CH1_A0 = 0x1000 | A0, // 0x 1[TIM2] 0[MAP0] 00[A0 ] + TIM2_ENCOEDER_MAP0_CH2_A1 = 0x1000 | A1, // 0x 1[TIM2] 0[MAP0] 01[A1 ] + + // ΪTIM2һͨӳŻá + // ӳ + TIM2_ENCOEDER_MAP1_CH1_A15 = 0x1100 | A15, // 0x 1[TIM2] 1[MAP1] 0F[A15] + TIM2_ENCOEDER_MAP1_CH2_B3 = 0x1100 | B3, // 0x 1[TIM2] 1[MAP1] 23[B3 ] + + //----------ʱ3---------- + + // ΪTIM3һͨӳŻá + // Ĭӳ + TIM3_ENCOEDER_MAP0_CH1_A6 = 0x2000 | A6, // 0x 2[TIM3] 0[MAP0] 06[A6 ] + TIM3_ENCOEDER_MAP0_CH2_A7 = 0x2000 | A7, // 0x 2[TIM3] 0[MAP0] 07[A7 ] + + // ΪTIM3һͨӳŻá + // ӳ + TIM3_ENCOEDER_MAP2_CH1_B4 = 0x2200 | B4, // 0x 2[TIM3] 2[MAP2] 24[B4 ] + TIM3_ENCOEDER_MAP2_CH2_B5 = 0x2200 | B5, // 0x 2[TIM3] 2[MAP2] 25[B5 ] + + // ΪTIM3һͨӳŻá + // ȫӳ + TIM3_ENCOEDER_MAP3_CH1_C6 = 0x2300 | C6, // 0x 2[TIM3] 3[MAP3] 46[C6 ] + TIM3_ENCOEDER_MAP3_CH2_C7 = 0x2300 | C7, // 0x 2[TIM3] 3[MAP3] 47[C7 ] + + //----------ʱ4---------- + + // ΪTIM4һͨӳŻá + // Ĭӳ + TIM4_ENCOEDER_MAP0_CH1_B6 = 0x3000 | B6, // 0x 3[TIM4] 0[MAP0] 26[B6 ] + TIM4_ENCOEDER_MAP0_CH2_B7 = 0x3000 | B7, // 0x 3[TIM4] 0[MAP0] 27[B7 ] + + // ΪTIM4һͨӳŻá + // ض + TIM4_ENCOEDER_MAP1_CH1_D12 = 0x3100 | D12, // 0x 3[TIM4] 1[MAP1] 6C[D12] + TIM4_ENCOEDER_MAP1_CH2_D13 = 0x3100 | D13, // 0x 3[TIM4] 1[MAP1] 6D[D13] + + //----------ʱ5---------- + + // ΪTIM5һͨӳŻá + // Ĭӳ + TIM5_ENCOEDER_MAP0_CH1_A0 = 0x4000 | A0, // 0x 4[TIM5] 0[MAP0] 00[A0 ] + TIM5_ENCOEDER_MAP0_CH2_A1 = 0x4000 | A1, // 0x 4[TIM5] 0[MAP0] 01[A1 ] + + //----------ʱ8---------- + + // ΪTIM8һͨӳŻá + // Ĭӳ + TIM8_ENCOEDER_MAP0_CH1_C6 = 0x7000 | C6, // 0x 7[TIM8] 0[MAP0] 46[C6 ] + TIM8_ENCOEDER_MAP0_CH2_C7 = 0x7000 | C7, // 0x 7[TIM8] 0[MAP0] 47[C7 ] + + // ΪTIM8һͨӳŻá + // ӳ + TIM8_ENCOEDER_MAP1_CH1_B6 = 0x7100 | B6, // 0x 7[TIM8] 1[MAP1] 26[B6 ] + TIM8_ENCOEDER_MAP1_CH2_B7 = 0x7100 | B7, // 0x 7[TIM8] 1[MAP1] 27[B7 ] + + //----------ʱ9---------- + + // ΪTIM9һͨӳŻá + // Ĭӳ + TIM9_ENCOEDER_MAP0_CH1_A2 = 0x8000 | A2, // 0x 8[TIM9] 0[MAP0] 02[A2 ] + TIM9_ENCOEDER_MAP0_CH2_A3 = 0x8000 | A3, // 0x 8[TIM9] 0[MAP0] 03[A3 ] + + // ΪTIM9һͨӳŻá + // ȫӳ + TIM9_ENCOEDER_MAP3_CH1_D9 = 0x8300 | D9, // 0x 8[TIM9] 3[MAP3] 69[D9 ] + TIM9_ENCOEDER_MAP3_CH2_D11 = 0x8300 | D11, // 0x 8[TIM9] 3[MAP3] 6B[D11] + + //----------ʱ10---------- + + // ΪTIM10һͨӳŻá + // Ĭӳ + TIM10_ENCOEDER_MAP0_CH1_B8 = 0x9000 | B8, // 0x 9[TIM10] 0[MAP0] 28[B8] + TIM10_ENCOEDER_MAP0_CH2_B9 = 0x9000 | B9, // 0x 9[TIM10] 0[MAP0] 29[B9] + + // ΪTIM10һͨӳŻá + // ӳ + TIM10_ENCOEDER_MAP1_CH1_B3 = 0x9100 | B3, // 0x 9[TIM10] 1[MAP1] 23[B3] + TIM10_ENCOEDER_MAP1_CH2_B4 = 0x9100 | B4, // 0x 9[TIM10] 1[MAP1] 24[B4] + + // ΪTIM10һͨӳŻá + // ȫӳ + TIM10_ENCOEDER_MAP3_CH1_D1 = 0x9300 | D1, // 0x 9[TIM10] 3[MAP3] 41[D1] + TIM10_ENCOEDER_MAP3_CH2_D3 = 0x9300 | D3, // 0x 9[TIM10] 3[MAP3] 43[D3] + +}encoder_channel_enum; + + +typedef enum +{ + TIM1_ENCOEDER = 0, + TIM2_ENCOEDER, + TIM3_ENCOEDER, + TIM4_ENCOEDER, + TIM5_ENCOEDER, + TIM8_ENCOEDER = 7, + TIM9_ENCOEDER, + TIM10_ENCOEDER, +}encoder_index_enum; + +int16 encoder_get_count (encoder_index_enum encoder_n); +void encoder_clear_count (encoder_index_enum encoder_n); +void encoder_quad_init (encoder_index_enum encoder_n, encoder_channel_enum ch1_pin, encoder_channel_enum ch2_pin); +void encoder_dir_init (encoder_index_enum encoder_n, encoder_channel_enum ch1_pin, encoder_channel_enum ch2_pin); + +#endif diff --git a/libraries/zf_driver/zf_driver_exti.c b/libraries/zf_driver/zf_driver_exti.c new file mode 100644 index 0000000..ccbd39d --- /dev/null +++ b/libraries/zf_driver/zf_driver_exti.c @@ -0,0 +1,99 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_exti +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "zf_common_interrupt.h" + +#include "zf_driver_exti.h" +#include "zf_driver_gpio.h" + +//------------------------------------------------------------------------------------------------------------------- +// EXTI жʹ +// ˵ pin ѡ EXTI (ѡΧ zf_driver_gpio.h gpio_pin_enum öֵȷ) +// ز void +// ʹʾ exti_enable(A0); +//------------------------------------------------------------------------------------------------------------------- +void exti_enable (gpio_pin_enum pin) +{ + EXTI->INTENR |= (0x00000001 << (pin&0x1F)); +} + +//------------------------------------------------------------------------------------------------------------------- +// EXTI жʧ +// ˵ pin ѡ EXTI (ѡΧ zf_driver_gpio.h gpio_pin_enum öֵȷ) +// ز void +// ʹʾ exti_disable(A0); +//------------------------------------------------------------------------------------------------------------------- +void exti_disable (gpio_pin_enum pin) +{ + EXTI->INTENR &= ~(0x00000001 << (pin&0x1F)); +} + + +//------------------------------------------------------------------------------------------------------------------- +// EXTI жϳʼ <ͬһ±ŲͬʱʼΪⲿж A0 B0 ͬʱʼΪⲿж> +// ˵ pin ѡ EXTI (ѡΧ zf_driver_gpio.h gpio_pin_enum öֵȷ) +// ˵ trigger ѡ񴥷źŷʽ [EXTI_TRIGGER_RISING/EXTI_TRIGGER_FALLING/EXTI_TRIGGER_BOTH] +// ز void +// ʹʾ exti_init(A0, EXTI_TRIGGER_RISING); +//------------------------------------------------------------------------------------------------------------------- +void exti_init (gpio_pin_enum pin, exti_trigger_enum trigger) +{ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO,ENABLE); // ʱʹ + gpio_init(pin, GPI, GPIO_HIGH, GPI_PULL_UP); // ʼѡе + GPIO_EXTILineConfig(pin >> 5, pin & 0x1F); // ѡһGPIOж + + EXTI_InitTypeDef EXTI_InitStructure = {0}; + EXTI_InitStructure.EXTI_Line = 1 << (pin & 0x1F); // ź + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; // ģʽ + EXTI_InitStructure.EXTI_Trigger = trigger; // ʽ + EXTI_InitStructure.EXTI_LineCmd = ENABLE; // ʹܻʧ + EXTI_Init(&EXTI_InitStructure); + + if((pin&0x1F) < 1) + interrupt_enable(EXTI0_IRQn); // ʹ Line0 жӦ + else if((pin&0x1F) < 2) + interrupt_enable(EXTI1_IRQn); // ʹ Line1 жӦ + else if((pin&0x1F) < 3) + interrupt_enable(EXTI2_IRQn); // ʹ Line2 жӦ + else if((pin&0x1F) < 4) + interrupt_enable(EXTI3_IRQn); // ʹ Line3 жӦ + else if((pin&0x1F) < 5) + interrupt_enable(EXTI4_IRQn); // ʹ Line4 жӦ + else if((pin&0x1F) < 10) + interrupt_enable(EXTI9_5_IRQn); // ʹ Line5-9 жӦ + else + interrupt_enable(EXTI15_10_IRQn); // ʹ Line10-15 жӦ +} + diff --git a/libraries/zf_driver/zf_driver_exti.h b/libraries/zf_driver/zf_driver_exti.h new file mode 100644 index 0000000..3b77287 --- /dev/null +++ b/libraries/zf_driver/zf_driver_exti.h @@ -0,0 +1,53 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_exti +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_exti_h_ +#define _zf_driver_exti_h_ + +#include "zf_common_typedef.h" + +#include "zf_driver_gpio.h" + +typedef enum{ // ö EXTI ź öٶ岻û޸ + EXTI_TRIGGER_RISING = 0x08, // شģʽ + EXTI_TRIGGER_FALLING = 0x0C, // ½شģʽ + EXTI_TRIGGER_BOTH = 0x10, // ˫شģʽ +}exti_trigger_enum; + +void exti_enable (gpio_pin_enum pin); +void exti_disable (gpio_pin_enum pin); +void exti_init (gpio_pin_enum pin, exti_trigger_enum trigger); + +#endif diff --git a/libraries/zf_driver/zf_driver_flash.c b/libraries/zf_driver/zf_driver_flash.c new file mode 100644 index 0000000..5fd2dbe --- /dev/null +++ b/libraries/zf_driver/zf_driver_flash.c @@ -0,0 +1,291 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_flash +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + + + +#include "zf_common_debug.h" +#include "zf_common_interrupt.h" +#include "zf_common_clock.h" + +#include "zf_driver_flash.h" + +flash_data_union flash_union_buffer[FLASH_DATA_BUFFER_SIZE]; // FLASH ݻ + +//------------------------------------------------------------------------------------------------------------------- +// У FLASH Ƿ +// ˵ sector_num Ҫд Χ <0 - 63> +// ˵ page_num ǰҳı Χ <0 - 3> +// ز uint8 1- 0-û ҪݵдµӦöв +// ʹʾ flash_check(63, 3); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 flash_check (uint32 sector_num, uint32 page_num) +{ + zf_assert(sector_num <= FLASH_MAX_SECTION_INDEX); // Χ 0-63 + zf_assert(page_num <= FLASH_MAX_PAGE_INDEX); // Χ 0-3 + + uint8 return_state = 0; + uint16 temp_loop; + uint32 flash_addr = ((FLASH_BASE_ADDR+FLASH_SECTION_SIZE*sector_num+FLASH_PAGE_SIZE*page_num)); // ȡǰ Flash ַ + + uint32 primask = interrupt_global_disable(); + + //clock_reset(); // λʱ + //clock_set_freq(SYSTEM_CLOCK_120M); // ϵͳƵΪ120Mhz + + for(temp_loop = 0; temp_loop < FLASH_PAGE_SIZE; temp_loop+=4) // ѭȡ Flash ֵ + { + if( (*(__IO u32*) (flash_addr+temp_loop)) != 0xE339E339 ) // õƬ 0xE339E339 Ǿֵ + { + return_state = 1; + break; + } + } + + //clock_reset(); // λʱ + //clock_set_freq(system_clock); // ûԭϵͳƵ + interrupt_global_enable(primask); + + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// һ(4KB) +// ˵ sector_num Ҫд Χ <0 - 63> +// ˵ page_num ǰҳı Χ <0 - 3> +// ز uint8 1-ʾʧ 0-ʾɹ +// ʹʾ flash_erase_page(63, 3); +// עϢ +// ׼ֻDzһݣ4KBֽڳ +//------------------------------------------------------------------------------------------------------------------- +uint8 flash_erase_sector (uint32 sector_num, uint32 page_num) +{ + zf_assert(sector_num <= FLASH_MAX_SECTION_INDEX); // Χ 0-63 + zf_assert(page_num <= FLASH_MAX_PAGE_INDEX); // Χ 0-3 + + uint8 return_state = 0; + + static volatile FLASH_Status gFlashStatus = FLASH_COMPLETE; + uint32 flash_addr = ((FLASH_BASE_ADDR+FLASH_SECTION_SIZE*sector_num+FLASH_PAGE_SIZE*page_num)); // ȡǰ Flash ַ + + uint32 primask = interrupt_global_disable(); + //clock_reset(); // λʱ + //clock_set_freq(SYSTEM_CLOCK_120M); // ϵͳƵΪ120Mhz + + FLASH_Unlock(); // Flash + FLASH_ClearFlag(FLASH_FLAG_EOP | FLASH_FLAG_PGERR | FLASH_FLAG_WRPRTERR); // ־ + gFlashStatus = FLASH_ErasePage(flash_addr); // + FLASH_ClearFlag(FLASH_FLAG_EOP ); // ־ + FLASH_Lock(); // Flash + if(gFlashStatus != FLASH_COMPLETE) // жϲǷɹ + { + return_state = 1; + } + + //clock_reset(); // λʱ + //clock_set_freq(system_clock); // ûԭϵͳƵ + interrupt_global_enable(primask); + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// ȡһҳ +// ˵ sector_num Ҫд Χ <0 - 63> +// ˵ page_num ǰҳı Χ <0 - 3> +// ˵ buf Ҫȡݵַ ͱΪuint32 +// ˵ len Ҫдݳ Χ 1-256 +// ز void +// ʹʾ flash_read_page(63, 3, data_buffer, 256); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void flash_read_page (uint32 sector_num, uint32 page_num, uint32 *buf, uint16 len) +{ + zf_assert(sector_num <= FLASH_MAX_SECTION_INDEX); // Χ 0-63 + zf_assert(page_num <= FLASH_MAX_PAGE_INDEX); // Χ 0-3 + zf_assert(len <= FLASH_DATA_BUFFER_SIZE); + + uint16 temp_loop = 0; + uint32 flash_addr = 0; + flash_addr = ((FLASH_BASE_ADDR+FLASH_SECTION_SIZE*sector_num+FLASH_PAGE_SIZE*page_num)); // ȡǰ Flash ַ + + uint32 primask = interrupt_global_disable(); + //clock_reset(); // λʱ + //clock_set_freq(SYSTEM_CLOCK_120M); // ϵͳƵΪ120Mhz + + + for(temp_loop = 0; temp_loop < len; temp_loop++) // ָȶȡ + { + *buf++ = *(__IO uint32*)(flash_addr+temp_loop*4); // ѭȡ Flash ֵ + } + // Flash + //clock_reset(); // λʱ + //clock_set_freq(system_clock); // ûԭϵͳƵ + interrupt_global_enable(primask); +} + +//------------------------------------------------------------------------------------------------------------------- +// һҳ +// ˵ sector_num Ҫд Χ <0 - 63> +// ˵ page_num ǰҳı Χ <0 - 3> +// ˵ buf Ҫдݵַ ͱΪ uint32 +// ˵ len Ҫдݳ Χ 1-256 +// ز uint8 1-ʾʧ 0-ʾɹ +// ʹʾ flash_write_page(63, 3, data_buffer, 256); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 flash_write_page (uint32 sector_num, uint32 page_num, const uint32 *buf, uint16 len) +{ + zf_assert(sector_num <= FLASH_MAX_SECTION_INDEX); // Χ 0-63 + zf_assert(page_num <= FLASH_MAX_PAGE_INDEX); // Χ 0-3 + zf_assert(len <= FLASH_DATA_BUFFER_SIZE); + uint8 return_state = 0; + static volatile FLASH_Status gFlashStatus = FLASH_COMPLETE; + uint32 flash_addr = 0; + flash_addr = ((FLASH_BASE_ADDR+FLASH_SECTION_SIZE*sector_num+FLASH_PAGE_SIZE*page_num)); // ȡǰ Flash ַ + + if(flash_check(sector_num, page_num)) // жǷ ı ֹûд + { + flash_erase_sector(sector_num, page_num); // һ + } + + uint32 primask = interrupt_global_disable(); + //clock_reset(); // λʱ + //clock_set_freq(SYSTEM_CLOCK_120M); // ϵͳƵΪ120Mhz + FLASH_Unlock(); // Flash + while(len--) // ݳ + { + gFlashStatus = FLASH_ProgramWord(flash_addr, *buf++); // 32bit д + if(gFlashStatus != FLASH_COMPLETE) // ȷϲǷɹ + { + return_state = 1; + break; + } + flash_addr += 4; // ַ + } + FLASH_Lock(); // Flash + //clock_reset(); // λʱ + //clock_set_freq(system_clock); // ûԭϵͳƵ + interrupt_global_enable(primask); + + return return_state; +} + + +//------------------------------------------------------------------------------------------------------------------- +// ָ FLASH ָҳȡݵ +// ˵ sector_num Ҫд Χ <0 - 63> +// ˵ page_num ǰҳı Χ <0 - 3> +// ز void +// ʹʾ flash_read_page_to_buffer(63, 3); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void flash_read_page_to_buffer (uint32 sector_num, uint32 page_num) +{ + zf_assert(sector_num <= FLASH_MAX_SECTION_INDEX); // Χ 0-63 + zf_assert(page_num <= FLASH_MAX_PAGE_INDEX); // Χ 0-3 + uint16 temp_loop; + uint32 flash_addr = ((FLASH_BASE_ADDR + FLASH_SECTION_SIZE*sector_num + FLASH_PAGE_SIZE*page_num)); // ȡǰ Flash ַ + + + + for(temp_loop = 0; temp_loop < FLASH_DATA_BUFFER_SIZE; temp_loop++) // ָȶȡ + { + flash_union_buffer[temp_loop].uint32_type = *(__IO uint32*)(flash_addr+temp_loop*4); // ѭȡ Flash ֵ + } + + +} + +//------------------------------------------------------------------------------------------------------------------- +// ָ FLASH ָҳд뻺 +// ˵ sector_num Ҫд Χ <0 - 63> +// ˵ page_num ǰҳı Χ <0 - 3> +// ز uint8 1-ʾʧ 0-ʾɹ +// ʹʾ flash_write_page_from_buffer(63, 3); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 flash_write_page_from_buffer (uint32 sector_num, uint32 page_num) +{ + zf_assert(sector_num <= FLASH_MAX_SECTION_INDEX); // Χ 0-63 + zf_assert(page_num <= FLASH_MAX_PAGE_INDEX); // Χ 0-3 + uint8 return_state = 0; + + static volatile FLASH_Status gFlashStatus = FLASH_COMPLETE; + uint32 flash_addr = 0; + uint16 len = 0; + flash_addr = ((FLASH_BASE_ADDR+FLASH_SECTION_SIZE*sector_num+FLASH_PAGE_SIZE*page_num)); // ȡǰ Flash ַ + + if(flash_check(sector_num, page_num)) // жǷ ı ֹûд + flash_erase_sector(sector_num, page_num); // һҳ + + uint32 primask = interrupt_global_disable(); + //clock_reset(); // λʱ + //clock_set_freq(SYSTEM_CLOCK_120M); // ϵͳƵΪ120Mhz + + FLASH_Unlock(); // Flash + while(len < FLASH_DATA_BUFFER_SIZE) // ݳ + { + gFlashStatus = FLASH_ProgramWord(flash_addr, flash_union_buffer[len].uint32_type); // 32bit д + if(gFlashStatus != FLASH_COMPLETE) // ȷϲǷɹ + { + return_state = 1; + break; + } + + len++; // + flash_addr += 4; // ַ + } + FLASH_Lock(); // Flash + + //clock_reset(); // λʱ + //clock_set_freq(system_clock); // ûԭϵͳƵ + interrupt_global_enable(primask); + + return return_state; +} + + +//------------------------------------------------------------------------------------------------------------------- +// ݻ +// ˵ void +// ز void +// ʹʾ flash_buffer_clear(); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void flash_buffer_clear (void) +{ + memset(flash_union_buffer, 0xFF, FLASH_PAGE_SIZE); +} + diff --git a/libraries/zf_driver/zf_driver_flash.h b/libraries/zf_driver/zf_driver_flash.h new file mode 100644 index 0000000..b1dc4fd --- /dev/null +++ b/libraries/zf_driver/zf_driver_flash.h @@ -0,0 +1,81 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_delay +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_flash_h +#define _zf_driver_flash_h + +#include "ch32v30x.h" +#include "ch32v30x_flash.h" +#include "zf_common_typedef.h" + +#define FLASH_BASE_ADDR (0x08000000) // FALSH׵ַ +#define FLASH_MAX_PAGE_INDEX (3) +#define FLASH_MAX_SECTION_INDEX (63) +#define FLASH_PAGE_SIZE (0x00000400) // 1K byte +#define FLASH_SECTION_SIZE (FLASH_PAGE_SIZE*4) // 4K byte +#define FLASH_OPERATION_TIME_OUT 0x0FFF + +#define FLASH_DATA_BUFFER_SIZE (FLASH_PAGE_SIZE/sizeof(flash_data_union)) // Զÿҳܹ¶ٸ + +typedef union // ̶ݻ嵥Ԫʽ +{ + float float_type; // float + uint32 uint32_type; // uint32 + int32 int32_type; // int32 + uint16 uint16_type; // uint16 + int16 int16_type; // int16 + uint8 uint8_type; // uint8 + int8 int8_type; // int8 +}flash_data_union; // ݹͬһ 32bit ַ + + +/* + Դʹõ64K RAM+ 256KFLASH + flash һ64һ4K +*/ + + +extern flash_data_union flash_union_buffer[FLASH_DATA_BUFFER_SIZE]; + +uint8 flash_check (uint32 sector_num, uint32 page_num); +uint8 flash_erase_sector (uint32 sector_num, uint32 page_num); +void flash_read_page (uint32 sector_num, uint32 page_num, uint32 *buf, uint16 len); +uint8 flash_write_page (uint32 sector_num, uint32 page_num, const uint32 *buf, uint16 len); + +void flash_read_page_to_buffer (uint32 sector_num, uint32 page_num); +uint8 flash_write_page_from_buffer (uint32 sector_num, uint32 page_num); +void flash_buffer_clear (void); + +#endif diff --git a/libraries/zf_driver/zf_driver_gpio.c b/libraries/zf_driver/zf_driver_gpio.c new file mode 100644 index 0000000..5e89d98 --- /dev/null +++ b/libraries/zf_driver/zf_driver_gpio.c @@ -0,0 +1,158 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_gpio +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + + +#include "zf_driver_gpio.h" + + +GPIO_TypeDef *gpio_group[5] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE}; + +//------------------------------------------------------------------------------------------------------------------- +// GPIO +// ˵ pin źѡ (ѡΧ common.h GPIO_PIN_enumöֵȷ) +// ˵ dat ŵĵƽ״̬ʱЧ 0͵ƽ 1ߵƽ +// ز void +// ʹʾ gpio_set_level(D0, 0);//D0͵ƽ +//------------------------------------------------------------------------------------------------------------------- +void gpio_set_level(gpio_pin_enum pin, uint8 dat) +{ + if(dat) + { + gpio_high(pin); // ߵƽ + } + else + { + gpio_low(pin); // ͵ƽ + } +} + +//------------------------------------------------------------------------------------------------------------------- +// GPIO״̬ȡ +// ˵ pin ѡ (ѡΧ common.h GPIO_PIN_enumöֵȷ) +// ز uint8 0͵ƽ 1ߵƽ +// ʹʾ uint8 status = gpio_get_level(D0);//ȡD0ŵƽ +//------------------------------------------------------------------------------------------------------------------- +uint8 gpio_get_level(gpio_pin_enum pin) +{ + return ((gpio_group[(pin & 0xE0) >> 5]->INDR & (((uint16)0x0001) << (pin & 0x1F))) ? 1 : 0); +} + +//------------------------------------------------------------------------------------------------------------------- +// GPIO ת +// ˵ pin ѡ (ѡΧ common.h GPIO_PIN_enumöֵȷ) +// ز void +// ʹʾ gpio_toggle_level(D5);//D5ŵƽת +//------------------------------------------------------------------------------------------------------------------- +void gpio_toggle_level(gpio_pin_enum pin) +{ + uint8 io_group = (pin & 0xE0) >> 5; + uint8 io_pin = pin & 0x1F; + + ((gpio_group[io_group]))->OUTDR ^= (uint16)(1 << io_pin); +} + +//------------------------------------------------------------------------------------------------------------------- +// gpio +// ˵ pin ѡ (ѡΧ zf_driver_gpio.h gpio_pin_enum öֵȷ) +// ˵ dir ŵķ GPO 룺GPI +// ˵ mode ŵģʽ (ѡΧ zf_driver_gpio.h gpio_mode_enum öֵȷ) +// ز void +// ʹʾ gpio_set_dir(D5, GPI, GPI_PULL_UP); // D5 Ϊ +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void gpio_set_dir (gpio_pin_enum pin, gpio_dir_enum dir, gpio_mode_enum mode) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint8 io_group = (pin & 0xE0) >> 5; + uint8 io_pin = pin & 0x1F; + + // ź + GPIO_InitStructure.GPIO_Pin = (uint16)(1 << io_pin); + + // ֻҪٶ + if(GPO == dir) + { + if((uint16)mode >> 8 == 0) GPIO_InitStructure.GPIO_Speed = (GPIOSpeed_TypeDef)(GPIO_Speed_50MHz); // ֹûд,Ĭ50Mhz + else GPIO_InitStructure.GPIO_Speed = (gpio_speed_enum)((uint16)mode >> 8); // Ѿд˸òֵ + } + + // ģʽ + GPIO_InitStructure.GPIO_Mode = (GPIOMode_TypeDef)((uint16)mode & 0xFF); + GPIO_Init(gpio_group[io_group], &GPIO_InitStructure); +} + +//------------------------------------------------------------------------------------------------------------------- +// GPIOʼ +// ˵ pin ѡ (ѡΧ common.h GPIO_PIN_enumöֵȷ) +// ˵ dir ŵķ GPO 룺GPI +// ˵ dat ųʼʱõĵƽ״̬ʱЧ 0͵ƽ 1ߵƽ +// ˵ pinconf ãòzf_gpio.hļGPIOSPEED_enumGPIOMODE_enumöֵȷʹ | +// ز void +// ʹʾ gpio_init(D0, GPO, 1, GPIO_PIN_CONFIG);//D0ʼΪGPIOܡģʽߵƽٶ100MHZ +//------------------------------------------------------------------------------------------------------------------- +void gpio_init (gpio_pin_enum pin, gpio_dir_enum dir, const uint8 dat, gpio_mode_enum mode) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint8 io_group = (pin & 0xE0) >> 5; + uint8 io_pin = pin & 0x1F; + + // GPIOʹ + if(0 == io_group) RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + else if(1 == io_group) RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + else if(2 == io_group) RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); + else if(3 == io_group) RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE); + else if(4 == io_group) RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE); + + // ź + GPIO_InitStructure.GPIO_Pin = (uint16)(1 << io_pin); + + // ֻҪٶ + if(GPO == dir) + { + if((uint16)mode >> 8 == 0) GPIO_InitStructure.GPIO_Speed = (GPIOSpeed_TypeDef)(GPIO_Speed_50MHz); // ֹûд,Ĭ50Mhz + else GPIO_InitStructure.GPIO_Speed = (gpio_speed_enum)((uint16)mode >> 8); // Ѿд˸òֵ + } + + // ģʽ + GPIO_InitStructure.GPIO_Mode = (GPIOMode_TypeDef)((uint16)mode & 0xFF); + GPIO_Init(gpio_group[io_group], &GPIO_InitStructure); + + // ֻҪ״̬ + if(GPO == dir) + { + GPIO_WriteBit(gpio_group[io_group], (uint16)(1 << io_pin), dat); + } +} + diff --git a/libraries/zf_driver/zf_driver_gpio.h b/libraries/zf_driver/zf_driver_gpio.h new file mode 100644 index 0000000..b95b65d --- /dev/null +++ b/libraries/zf_driver/zf_driver_gpio.h @@ -0,0 +1,177 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_gpio +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + + +#ifndef _zf_driver_gpio_h +#define _zf_driver_gpio_h + +#include "ch32v30x_rcc.h" +#include "ch32v30x_gpio.h" +#include "ch32v30x_exti.h" +#include "zf_common_typedef.h" + +typedef enum // ö GPIO öٶ岻û޸ +{ + A0 = 0x00, A1 , A2 , A3 , A4 , A5 , A6 , A7 , + A8 , A9 , A10, A11, A12, A13, A14, A15, + + B0 = 0x20, B1 , B2 , B3 , B4 , B5 , B6 , B7 , + B8 , B9 , B10, B11, B12, B13, B14, B15, + + C0 = 0x40, C1 , C2 , C3 , C4 , C5 , C6 , C7 , + C8 , C9 , C10, C11, C12, C13, C14, C15, + + D0 = 0x60, D1 , D2 , D3 , D4 , D5 , D6 , D7 , + D8 , D9 , D10, D11, D12, D13, D14, D15, + + E0 = 0x80, E1 , E2 , E3 , E4 , E5 , E6 , E7 , + E8 , E9 , E10, E11, E12, E13, E14, E15, + + PIN_NULL = 0xFF +}gpio_pin_enum; + +typedef enum +{ + GPI = 0, // ܽ뷽 + GPO = 1, // ܽ +}gpio_dir_enum; + +typedef enum +{ + // + GPI_ANAOG_IN = 0x00, // ģģʽ + GPI_FLOATING_IN = 0x04, // ģʽ + GPI_PULL_DOWN = 0x28, // + GPI_PULL_UP = 0x48, // + + // + GPO_PUSH_PULL = 0x10, // ͨģʽ + GPO_OPEN_DTAIN = 0x14, // ͨÿ©ģʽ + GPO_AF_PUSH_PULL = 0x18, // ùģʽ + GPO_AF_OPEN_DTAIN = 0x1C, // ùܿ©ģʽ +}gpio_mode_enum; + +// 궨GPIOŵĬãڳʼGPIOʱдҪ޸ +#define GPIO_PIN_CONFIG (SPEED_50MHZ | GPO_PUSH_PULL) +// 궨GPIOжϺŵĬãڳʼGPIOжʱдҪ޸ +#define GPIO_INT_CONFIG (GPI_PULL_UP) + +typedef enum +{ + SPEED_10MHZ = (0x01 << 8), + SPEED_2MHZ = (0x02 << 8), + SPEED_50MHZ = (0x03 << 8) +}gpio_speed_enum; + +typedef enum +{ + GPIO_LOW = 0, // ͵ƽ + GPIO_HIGH = 1, // ߵƽ +}gpio_level_enum; + +extern GPIO_TypeDef *gpio_group[5]; + + + +//------------------------------------------------------------------------------------------------------------------- +// ȡӦ IO ݵַ +// ˵ x ѡ (ѡΧ zf_driver_gpio.h gpio_pin_enum öֵȷ) +// ز uint32 32bit ַ +// ʹʾ gpio_idr_addr(D5); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +#define gpio_idr_addr(x) (0x40040008 + (((x) & 0xFE0) >> 5) * 0x400 + (((x) & 0x1F) / 8)) + +//------------------------------------------------------------------------------------------------------------------- +// ȡӦ IO ݵַ +// ˵ x ѡ (ѡΧ zf_driver_gpio.h gpio_pin_enum öֵȷ) +// ز uint32 32bit ַ +// ʹʾ gpio_odr_addr(D5); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +#define gpio_odr_addr(x) (0x4004000C + (((x) & 0xFE0) >> 5) * 0x400 + (((x) & 0x1F) / 8)) + +//------------------------------------------------------------------------------------------------------------------- +// ȡӦ IO λĴַ +// ˵ x ѡ (ѡΧ zf_driver_gpio.h gpio_pin_enum öֵȷ) +// ز uint32 32bit ַ +// ʹʾ gpio_bsrr_addr(D5); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +#define gpio_bsrr_addr(x) (0x40040010 + (((x) & 0xFE0) >> 5) * 0x400 + (((x) & 0x1F) / 8)) + +//------------------------------------------------------------------------------------------------------------------- +// ȡӦ IO ĸλĴַ +// ˵ x ѡ (ѡΧ zf_driver_gpio.h gpio_pin_enum öֵȷ) +// ز uint32 32bit ַ +// ʹʾ gpio_brr_addr(D5); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +#define gpio_brr_addr(x) (0x40040014 + (((x) & 0xFE0) >> 5) * 0x400 + (((x) & 0x1F) / 8)) + +//------------------------------------------------------------------------------------------------------------------- +// Ӧ IO λΪ͵ƽ +// ˵ x ѡ (ѡΧ zf_driver_gpio.h gpio_pin_enum öֵȷ) +// ز void +// ʹʾ gpio_low(D5); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +#define gpio_low(x) ((GPIO_TypeDef*)gpio_group[(x>>5)])->BCR = (uint16)(1 << (x & 0x0F)) + +//------------------------------------------------------------------------------------------------------------------- +// Ӧ IO λΪߵƽ +// ˵ x ѡ (ѡΧ zf_driver_gpio.h gpio_pin_enum öֵȷ) +// ز void +// ʹʾ gpio_high(D5); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +#define gpio_high(x) ((GPIO_TypeDef*)gpio_group[(x>>5)])->BSHR = (uint16)(1 << (x & 0x0F)) + +void gpio_set_level (gpio_pin_enum pin, uint8 dat); +uint8 gpio_get_level (gpio_pin_enum pin); +void gpio_toggle_level (gpio_pin_enum pin); +void gpio_init (gpio_pin_enum pin, gpio_dir_enum dir, const uint8 dat, gpio_mode_enum mode); + + +#ifdef COMPATIBLE_WITH_OLDER_VERSIONS // ݾɰ汾Դӿ +#define gpio_set(pin, dat) (gpio_set_level((pin), (dat))) +#define gpio_get(pin) (gpio_get_level((pin))) +#define gpio_dir(pin, dir, mode) (gpio_set_dir((pin), (dir), (mode))) +#define gpio_toggle(pin) (gpio_toggle_level((pin))) +#endif + + + +#endif diff --git a/libraries/zf_driver/zf_driver_iic.c b/libraries/zf_driver/zf_driver_iic.c new file mode 100644 index 0000000..3c6a796 --- /dev/null +++ b/libraries/zf_driver/zf_driver_iic.c @@ -0,0 +1,45 @@ +/********************************************************************************************************************* +* MM32F327X-G9P Opensourec Library 即（MM32F327X-G9P 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是 MM32F327X-G9P 开源库的一部分 +* +* MM32F327X-G9P 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_driver_iic +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 IAR 8.32.4 or MDK 5.37 +* 适用平台 MM32F327X_G9P +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-08-10 Teternal first version +********************************************************************************************************************/ + + +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_driver_gpio.h" + +#include "zf_driver_iic.h" + + +// 等待后续更新 +uint8 temp_update; diff --git a/libraries/zf_driver/zf_driver_iic.h b/libraries/zf_driver/zf_driver_iic.h new file mode 100644 index 0000000..7b22091 --- /dev/null +++ b/libraries/zf_driver/zf_driver_iic.h @@ -0,0 +1,42 @@ +/********************************************************************************************************************* +* MM32F327X-G9P Opensourec Library 即（MM32F327X-G9P 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是 MM32F327X-G9P 开源库的一部分 +* +* MM32F327X-G9P 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_driver_iic +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 IAR 8.32.4 or MDK 5.37 +* 适用平台 MM32F327X_G9P +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-08-10 Teternal first version +********************************************************************************************************************/ + +#ifndef _zf_driver_iic_h_ +#define _zf_driver_iic_h_ + +#include "zf_common_typedef.h" + + +#endif diff --git a/libraries/zf_driver/zf_driver_pit.c b/libraries/zf_driver/zf_driver_pit.c new file mode 100644 index 0000000..a1e0f60 --- /dev/null +++ b/libraries/zf_driver/zf_driver_pit.c @@ -0,0 +1,163 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_pit +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + + +#include "ch32v30x_rcc.h" +#include "zf_common_clock.h" +#include "zf_common_debug.h" +#include "zf_common_interrupt.h" +#include "zf_driver_timer.h" + +#include "zf_driver_pit.h" + +//------------------------------------------------------------------------------------------------------------------- +// PIT жʹ +// ˵ pit_n PIT ģ +// ز void +// ʹʾ pit_enable(TIM1_PIT); +//------------------------------------------------------------------------------------------------------------------- +void pit_enable (pit_index_enum pit_n) +{ + const uint32 irq_index[] = + { + TIM1_UP_IRQn, + TIM2_IRQn, + TIM3_IRQn, + TIM4_IRQn, + TIM5_IRQn, + TIM6_IRQn, + TIM7_IRQn, + TIM8_UP_IRQn, + TIM9_UP_IRQn, + TIM10_UP_IRQn + }; + interrupt_enable(irq_index[pit_n]); // ʹж +} + +//------------------------------------------------------------------------------------------------------------------- +// PIT жϽֹ +// ˵ pit_n PIT ģ +// ز void +// ʹʾ pit_disable(TIM1_PIT); +//------------------------------------------------------------------------------------------------------------------- +void pit_disable (pit_index_enum pit_n) +{ + const uint32 irq_index[] = + { + TIM1_UP_IRQn, + TIM2_IRQn, + TIM3_IRQn, + TIM4_IRQn, + TIM5_IRQn, + TIM6_IRQn, + TIM7_IRQn, + TIM8_UP_IRQn, + TIM9_UP_IRQn, + TIM10_UP_IRQn + }; + + interrupt_disable(irq_index[pit_n]); // ʧж + +} + +//------------------------------------------------------------------------------------------------------------------- +// ʱж +// ˵ timer_ch ʱͨ +// ˵ us ʱ(1-65535) +// ز void +// עϢ pit_init(TIMER_1, 5); ʹöʱ1Ϊ5msһεж +//------------------------------------------------------------------------------------------------------------------- +void pit_init (pit_index_enum pit_n, uint32 period) +{ + + // ˶Ϣ ʾλ + // ȥ鿴ʲôط Ĵ + // ǼǷظʹöʱ + // ʼ TIM1_PWM Ȼֳʼ TIM1_PIT ÷Dz + zf_assert(timer_funciton_check((timer_index_enum)pit_n, TIMER_FUNCTION_TIMER)); + // һб Ҿ͵Ϊʲôд 0 + zf_assert(period!=0); + + uint16 freq_div = (period >> 15); // ԤƵ + uint16 period_temp = (period / (freq_div+1)); // Զװֵ + + timer_clock_enable(pit_n); // ʹʱ + + + TIM_TypeDef *tim_index = TIM1; + switch(pit_n) + { + case TIM_1: tim_index = ((TIM_TypeDef *)TIM1_BASE); break; + case TIM_2: tim_index = ((TIM_TypeDef *)TIM2_BASE); break; + case TIM_3: tim_index = ((TIM_TypeDef *)TIM3_BASE); break; + case TIM_4: tim_index = ((TIM_TypeDef *)TIM4_BASE); break; + case TIM_5: tim_index = ((TIM_TypeDef *)TIM5_BASE); break; + case TIM_6: tim_index = ((TIM_TypeDef *)TIM6_BASE); break; + case TIM_7: tim_index = ((TIM_TypeDef *)TIM7_BASE); break; + case TIM_8: tim_index = ((TIM_TypeDef *)TIM8_BASE); break; + case TIM_9: tim_index = ((TIM_TypeDef *)TIM9_BASE); break; + case TIM_10: tim_index = ((TIM_TypeDef *)TIM10_BASE); break; + } + + + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure = {0}; + TIM_TimeBaseStructure.TIM_Period = period_temp; + TIM_TimeBaseStructure.TIM_Prescaler = freq_div; // Ƶֵ + TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1; // ʱӷָ:TDTS = Tck_tim + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; // TIMϼģʽ + TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; // ظΪ0 + TIM_TimeBaseInit(tim_index, &TIM_TimeBaseStructure); // ָIJʼTIMxʱλ + TIM_ITConfig(tim_index,TIM_IT_Update,ENABLE ); // ʹָTIMж,ж + TIM_ClearITPendingBit(tim_index, TIM_IT_Update); + + const uint32 irq_index[10] = + { + TIM1_UP_IRQn, + TIM2_IRQn, + TIM3_IRQn, + TIM4_IRQn, + TIM5_IRQn, + TIM6_IRQn, + TIM7_IRQn, + TIM8_UP_IRQn, + TIM9_UP_IRQn, + TIM10_UP_IRQn + }; + + interrupt_set_priority((IRQn_Type)irq_index[(uint8)pit_n], 0x03); // жȼ + interrupt_enable((IRQn_Type)irq_index[pit_n]); // ʹж + + TIM_Cmd(tim_index, ENABLE); // ʹܶʱ +} diff --git a/libraries/zf_driver/zf_driver_pit.h b/libraries/zf_driver/zf_driver_pit.h new file mode 100644 index 0000000..a2d1b67 --- /dev/null +++ b/libraries/zf_driver/zf_driver_pit.h @@ -0,0 +1,87 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_pit +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_pit_h +#define _zf_driver_pit_h + + +#include "zf_common_interrupt.h" + + +typedef enum // ö TIMͨ +{ + TIM1_PIT, + TIM2_PIT, + TIM3_PIT, + TIM4_PIT, + TIM5_PIT, + TIM6_PIT, + TIM7_PIT, + TIM8_PIT, + TIM9_PIT, + TIM10_PIT +}pit_index_enum; + + + +void pit_enable (pit_index_enum pit_n); +void pit_disable (pit_index_enum pit_n); + +void pit_init (pit_index_enum pit_n, uint32 period); + +//====================================================궨庯==================================================== +//------------------------------------------------------------------------------------------------------------------- +// TIM PIT жϳʼ ms +// ˵ pit_n ʹõ PIT +// ˵ ms PIT ms +// ز void +// ʹʾ pit_ms_init(TIM6_PIT, 1); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +#define pit_ms_init(pit_n, ms) (pit_init((pit_n), (ms) * (system_clock / 1000))) + +//------------------------------------------------------------------------------------------------------------------- +// TIM PIT жϳʼ us +// ˵ pit_n ʹõ PIT +// ˵ us PIT us +// ز void +// ʹʾ pit_us_init(TIM6_PIT, 100); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +#define pit_us_init(pit_n, us) (pit_init((pit_n), (us) * (system_clock / 1000000))) + +//====================================================궨庯==================================================== + +#endif diff --git a/libraries/zf_driver/zf_driver_pwm.c b/libraries/zf_driver/zf_driver_pwm.c new file mode 100644 index 0000000..fd03ed7 --- /dev/null +++ b/libraries/zf_driver/zf_driver_pwm.c @@ -0,0 +1,266 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_pwm +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + + +#include "zf_driver_gpio.h" +#include "zf_driver_timer.h" +#include "zf_driver_pwm.h" + + +//------------------------------------------------------------------------------------------------------------------- +// PWMռձ趨 +// ˵ pwmch PWMͨż +// ˵ duty PWMռձ +// ز void +// ʹʾ pwm_set_duty(TIM10_PWM_CH4_C15, 5000); //ʱ10 ͨ4 ʹC15 ռձΪٷ֮ 5000/PWM_DUTY_MAX*100 +// PWM_DUTY_MAXzf_pwm.hļ ĬΪ10000 +//------------------------------------------------------------------------------------------------------------------- +void pwm_set_duty(pwm_channel_enum pin, uint32 duty) +{ + // һб ȥռձ޶Ķ ռձд + zf_assert(PWM_DUTY_MAX >= duty); // ռձд + + + + TIM_TypeDef *tim_index = TIM1; + switch((pin & 0xF0000) >> 16) // ȡTIM + { + case 0: tim_index = TIM1; break; + case 1: tim_index = TIM2; break; + case 2: tim_index = TIM3; break; + case 3: tim_index = TIM4; break; + case 4: tim_index = TIM5; break; + case 7: tim_index = TIM8; break; + case 8: tim_index = TIM9; break; + case 9: tim_index = TIM10; break; + } + + + uint16 match_temp; + uint16 period_temp; + + period_temp = tim_index->ATRLR; // ȡʱֵ + match_temp = period_temp * duty / PWM_DUTY_MAX; // ռձ + + + + if(((pin>>8) & 0x03) == 0x00) // ͨѡ + { + tim_index->CH1CVR = match_temp; + } + else if(((pin>>8) & 0x03) == 0x01) // ͨѡ + { + tim_index->CH2CVR = match_temp; + } + else if(((pin>>8) & 0x03) == 0x02) // ͨѡ + { + tim_index->CH3CVR = match_temp; + } + else if(((pin>>8) & 0x03) == 0x03) // ͨѡ + { + tim_index->CH4CVR = match_temp; + } + +} + +//------------------------------------------------------------------------------------------------------------------- +// PWMƵ趨 +// ˵ pwmch PWMͨż +// ˵ freq PWMƵ +// ˵ duty PWMռձ +// ز void +// ʹʾ pwm_set_freq(PWM1_CH1_A8, 60, 5000); //ʹA8 PWMƵ60HZ ռձΪٷ֮ 5000/PWM_DUTY_MAX*100 +// PWM_DUTY_MAXzf_pwm.hļ ĬΪ10000 +//------------------------------------------------------------------------------------------------------------------- +void pwm_set_freq(pwm_channel_enum pin, uint32 freq, uint32 duty) +{ + uint16 period_temp = 0; // ֵ + uint16 freq_div = 0; // Ƶֵ + uint16 match_temp; + + freq_div = (uint16)((system_clock / freq) >> 16); // ٷƵ + period_temp = (uint16)(system_clock/(freq*(freq_div + 1))); // + + // ȡTIM + TIM_TypeDef *tim_index = TIM1; + switch((pin & 0xF0000) >> 16) + { + case 0: tim_index = TIM1; break; + case 1: tim_index = TIM2; break; + case 2: tim_index = TIM3; break; + case 3: tim_index = TIM4; break; + case 4: tim_index = TIM5; break; + case 7: tim_index = TIM8; break; + case 8: tim_index = TIM9; break; + case 9: tim_index = TIM10; break; + } + + + + tim_index->ATRLR = period_temp - 1 ; + tim_index->PSC = freq_div; + match_temp = period_temp * duty / PWM_DUTY_MAX; // ռձ + + + if(((pin>>8) & 0x03) == 0x00) // ͨѡ + { + tim_index->CH1CVR = match_temp; + } + else if(((pin>>8) & 0x03) == 0x01) // ͨѡ + { + tim_index->CH2CVR = match_temp; + } + else if(((pin>>8) & 0x03) == 0x02) // ͨѡ + { + tim_index->CH3CVR = match_temp; + } + else if(((pin>>8) & 0x03) == 0x03) // ͨѡ + { + tim_index->CH4CVR = match_temp; + } + +} + + +//------------------------------------------------------------------------------------------------------------------- +// PWMʼ +// ˵ pwmch PWMͨż +// ˵ freq PWMƵ +// ˵ duty PWMռձ +// ز void +// ʹʾ pwm_init(PWM1_CH1_A8, 50, 5000); //ʼPWM1 ͨ1 ʹA8 PWMƵ50HZ ռձΪٷ֮ 5000/PWM_DUTY_MAX*100 +// PWM_DUTY_MAXzf_pwm.hļ ĬΪ10000 +//------------------------------------------------------------------------------------------------------------------- +void pwm_init(pwm_channel_enum pin, uint32 freq, uint32 duty) +{ + + // ˶Ϣ ʾλ + // ȥ鿴ʲôط Ĵ + // ǼǷظʹöʱ + // ʼ TIM1_PIT Ȼֳʼ TIM1_PWM ÷Dz + zf_assert(timer_funciton_check((timer_index_enum)(pin>>16), TIMER_FUNCTION_PWM)); + // һб ȥռձ޶Ķ ռձд + zf_assert(PWM_DUTY_MAX >= duty); + + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure = {0}; + TIM_OCInitTypeDef TIM_OCInitStructure = {0}; + uint16 match_temp; // ռձֵ + uint16 period_temp; // ֵ + uint16 freq_div = 0; // Ƶֵ + + timer_clock_enable((pin & 0xF0000) >> 16); // ʱʱʹ + + gpio_init((gpio_pin_enum)(pin & 0xFF), GPO, 0, GPO_AF_PUSH_PULL | SPEED_50MHZ); // ʼ + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); // ʹAFIOùģʱ + + // ȡTIM + TIM_TypeDef *tim_index = TIM1; + switch((pin & 0xF0000) >> 16) + { + case 0: tim_index = TIM1; break; + case 1: tim_index = TIM2; break; + case 2: tim_index = TIM3; break; + case 3: tim_index = TIM4; break; + case 4: tim_index = TIM5; break; + case 7: tim_index = TIM8; break; + case 8: tim_index = TIM9; break; + case 9: tim_index = TIM10; break; + } + + // ù + if((pin >> 12) == 0x03) GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE); + + else if((pin >> 12) == 0x11) GPIO_PinRemapConfig(GPIO_PartialRemap1_TIM2, ENABLE); + else if((pin >> 12) == 0x12) GPIO_PinRemapConfig(GPIO_PartialRemap2_TIM2, ENABLE); + else if((pin >> 12) == 0x13) GPIO_PinRemapConfig(GPIO_FullRemap_TIM2, ENABLE); + + else if((pin >> 12) == 0x22) GPIO_PinRemapConfig(GPIO_PartialRemap_TIM3, ENABLE); + else if((pin >> 12) == 0x23) GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE); + else if((pin >> 12) == 0x31) GPIO_PinRemapConfig(GPIO_Remap_TIM4, ENABLE); + else if((pin >> 12) == 0x71) GPIO_PinRemapConfig(GPIO_Remap_TIM8, ENABLE); + else if((pin >> 12) == 0x83) GPIO_PinRemapConfig(GPIO_FullRemap_TIM9, ENABLE); + else if((pin >> 12) == 0x91) GPIO_PinRemapConfig(GPIO_PartialRemap_TIM10, ENABLE); + else if((pin >> 12) == 0x93) GPIO_PinRemapConfig(GPIO_FullRemap_TIM10, ENABLE); + + freq_div = (uint16)((system_clock / freq) >> 16); // ٷƵ + period_temp = (uint16)(system_clock/(freq*(freq_div + 1))); // + match_temp = period_temp * duty / PWM_DUTY_MAX; // ռձ + + TIM_TimeBaseStructure.TIM_Period = period_temp - 1; // һ¼װԶװؼĴڵֵ + TIM_TimeBaseStructure.TIM_Prescaler = freq_div; // ΪTIMxʱƵʳԤƵֵ + TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1; // ʱӷָ:TDTS = Tck_tim + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; // TIMϼģʽ + TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; + TIM_TimeBaseInit(tim_index, &TIM_TimeBaseStructure); // TIM_TimeBaseInitStructָIJʼTIMxʱλ + + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2; // ѡʱģʽ:TIMȵģʽ2 + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; // Ƚʹ + TIM_OCInitStructure.TIM_OutputNState = TIM_OutputState_Disable; + TIM_OCInitStructure.TIM_Pulse = match_temp; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; // :TIMȽϼԵ + TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCPolarity_Low; // :TIMȽϼԵ + TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset; + + if(((pin>>8) & 0x03) == 0x00) // ͨѡ + { + TIM_OC1Init(tim_index, &TIM_OCInitStructure ); // ʱͨ1ʼ + TIM_OC1PreloadConfig(tim_index, TIM_OCPreload_Enable); // ʱԤװ + TIM_OC1FastConfig(tim_index, TIM_OC1FE); // Ƚϲͨʹ + } + else if(((pin>>8) & 0x03) == 0x01) + { + TIM_OC2Init(tim_index, &TIM_OCInitStructure ); + TIM_OC2PreloadConfig(tim_index, TIM_OCPreload_Enable); + TIM_OC2FastConfig(tim_index, TIM_OC2FE); + } + else if(((pin>>8) & 0x03) == 0x02) + { + TIM_OC3Init(tim_index, &TIM_OCInitStructure ); + TIM_OC3PreloadConfig(tim_index, TIM_OCPreload_Enable); + TIM_OC3FastConfig(tim_index, TIM_OC3FE); + } + else if(((pin>>8) & 0x03) == 0x03) + { + TIM_OC4Init(tim_index, &TIM_OCInitStructure ); + TIM_OC4PreloadConfig(tim_index, TIM_OCPreload_Enable); + TIM_OC4FastConfig(tim_index, TIM_OC4FE); + } + TIM_CtrlPWMOutputs(tim_index, ENABLE ); // ͨPWMʹ + TIM_Cmd(tim_index, ENABLE); // ʱʹ + //TIM_ARRPreloadConfig( TIM1, ENABLE ); +} + diff --git a/libraries/zf_driver/zf_driver_pwm.h b/libraries/zf_driver/zf_driver_pwm.h new file mode 100644 index 0000000..21c2173 --- /dev/null +++ b/libraries/zf_driver/zf_driver_pwm.h @@ -0,0 +1,213 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_PWM_MAP +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_PWM_MAP_h +#define _zf_driver_PWM_MAP_h + +#include "ch32v30x_rcc.h" +#include "ch32v30x_gpio.h" +#include "ch32v30x_tim.h" +#include "zf_common_debug.h" + +typedef enum +{ + // MAP0 Ĭӳ + // MAP1 ӳ + // MAP2 ӳ + // MAP3 ȫӳ + + // ͬһPWMPģ鲻ֻͬͨͬƵʵPWMռձȿòͬ + // PWM1_PWM_MAP_CH1_PA8PWM1_PWM_MAP_CH3_PA10ͬһģ飬ƵֻһռձȿԲһ + + //----------------ʱ1---------------- + // 磺PWM1_PWM_MAP_CH2_PA9PWM1_PWM_MAP_CH1N_PB13һʹá + // ֻTIM1_PWM_MAP0_CH1_A8 TIM1_PWM_MAP0_CH2_A9 TIM1_PWM_MAP0_CH3_A10 TIM1_PWM_MAP0_CH4_A11 ͬӳһʹ + + // ΪTIM1PWMһӳţӳŻá + // Ĭӳ + TIM1_PWM_MAP0_CH1_A8 = 0x00000 | A8 , // 0x 0[TIM1] 0[MAP0] 0[CH1] 08[A8 ] + TIM1_PWM_MAP0_CH2_A9 = 0x00100 | A9 , // 0x 0[TIM1] 0[MAP0] 1[CH2] 09[A9 ] + TIM1_PWM_MAP0_CH3_A10 = 0x00200 | A10, // 0x 0[TIM1] 0[MAP0] 2[CH3] 0A[A10] + TIM1_PWM_MAP0_CH4_A11 = 0x00300 | A11, // 0x 0[TIM1] 0[MAP0] 3[CH4] 0B[A11] + + // ΪTIM1PWMһӳţӳŻá + // ȫӳ + TIM1_PWM_MAP3_CH1_E9 = 0x03000 | E9 , // 0x 0[TIM1] 3[MAP3] 0[CH1] 69[E9 ] + TIM1_PWM_MAP3_CH2_E11 = 0x03100 | E11, // 0x 0[TIM1] 3[MAP3] 1[CH2] 6B[E11] + TIM1_PWM_MAP3_CH3_E13 = 0x03200 | E13, // 0x 0[TIM1] 3[MAP3] 2[CH3] 6D[E13] + TIM1_PWM_MAP3_CH4_E14 = 0x03300 | E14, // 0x 0[TIM1] 3[MAP3] 3[CH4] 6E[E14] + + //----------------ʱ2---------------- + + // ΪTIM2PWMһӳţӳŻá + // Ĭӳ + TIM2_PWM_MAP0_CH1_A0 = 0x10000 | A0, + TIM2_PWM_MAP0_CH2_A1 = 0x10100 | A1, + TIM2_PWM_MAP0_CH3_A2 = 0x10200 | A2, + TIM2_PWM_MAP0_CH4_A3 = 0x10300 | A3, + + // ΪTIM2PWMһӳţӳŻá + // ӳ + TIM2_PWM_MAP1_CH1_A15 = 0x11000 | A15, + TIM2_PWM_MAP1_CH2_B3 = 0x11100 | B3 , + TIM2_PWM_MAP1_CH3_A2 = 0x11200 | A2 , + TIM2_PWM_MAP1_CH4_A3 = 0x11300 | A3 , + + // ΪTIM2PWMһӳţӳŻá + // ӳ + TIM2_PWM_MAP2_CH1_A0 = 0x12000 | A0 , + TIM2_PWM_MAP2_CH2_A1 = 0x12100 | A1 , + TIM2_PWM_MAP2_CH3_B10 = 0x12200 | B10, // ĬϴڣҪʹãҪĬϴڳʼ + TIM2_PWM_MAP2_CH4_B11 = 0x12300 | B11, // ĬϴڣҪʹãҪĬϴڳʼ + + // ΪTIM2PWMһӳţӳŻá + // ȫӳ + TIM2_PWM_MAP3_CH1_A15 = 0x13000 | A15, + TIM2_PWM_MAP3_CH2_B3 = 0x13100 | B3 , + TIM2_PWM_MAP3_CH3_B10 = 0x13200 | B10, // ĬϴڣҪʹãҪĬϴڳʼ + TIM2_PWM_MAP3_CH4_B11 = 0x13300 | B11, // ĬϴڣҪʹãҪĬϴڳʼ + + //----------------ʱ3---------------- + + // ΪTIM3PWMһӳţӳŻá + // Ĭӳ + TIM3_PWM_MAP0_CH1_A6 = 0x20000 | A6, + TIM3_PWM_MAP0_CH2_A7 = 0x20100 | A7, + TIM3_PWM_MAP0_CH3_B0 = 0x20200 | B0, + TIM3_PWM_MAP0_CH4_B1 = 0x20300 | B1, + + // ΪTIM3PWMһӳţӳŻá + // ӳ + TIM3_PWM_MAP2_CH1_B4 = 0x22000 | B4, + TIM3_PWM_MAP2_CH2_B5 = 0x22100 | B5, + TIM3_PWM_MAP2_CH3_B0 = 0x22200 | B0, + TIM3_PWM_MAP2_CH4_B1 = 0x22300 | B1, + + // ΪTIM3PWMһӳţӳŻá + // ȫӳ + TIM3_PWM_MAP3_CH1_C6 = 0x23000 | C6, + TIM3_PWM_MAP3_CH2_C7 = 0x23100 | C7, + TIM3_PWM_MAP3_CH3_C8 = 0x23200 | C8, + TIM3_PWM_MAP3_CH4_C9 = 0x23300 | C9, + + //----------------ʱ4---------------- + + // ΪTIM4PWMһӳţӳŻá + // Ĭӳ + TIM4_PWM_MAP0_CH1_B6 = 0x30000 | B6, + TIM4_PWM_MAP0_CH2_B7 = 0x30100 | B7, + TIM4_PWM_MAP0_CH3_B8 = 0x30200 | B8, + TIM4_PWM_MAP0_CH4_B9 = 0x30300 | B9, + + // ΪTIM4PWMһӳţӳŻá + //ӳ + TIM4_PWM_MAP1_CH1_D12 = 0x31000 | D12, + TIM4_PWM_MAP1_CH2_D13 = 0x31100 | D13, + TIM4_PWM_MAP1_CH3_D14 = 0x31200 | D14, + TIM4_PWM_MAP1_CH4_D15 = 0x31300 | D15, + + //----------------ʱ5---------------- + + // ΪTIM5PWMһӳţӳŻá + // Ĭӳ + TIM5_PWM_MAP0_CH1_A0 = 0x40000 | A0, + TIM5_PWM_MAP0_CH2_A1 = 0x40100 | A1, + TIM5_PWM_MAP0_CH3_A2 = 0x40200 | A2, + TIM5_PWM_MAP0_CH4_A3 = 0x40300 | A3, + + //----------------ʱ8---------------- + + // ΪTIM8PWMһӳţӳŻá + // Ĭӳ + TIM8_PWM_MAP0_CH1_C6 = 0x70000 | C6, + TIM8_PWM_MAP0_CH2_C7 = 0x70100 | C7, + TIM8_PWM_MAP0_CH3_C8 = 0x70200 | C8, + TIM8_PWM_MAP0_CH4_C9 = 0x70300 | C9, + + // ΪTIM8PWMһӳţӳŻá + //ӳ + TIM8_PWM_MAP1_CH1_B6 = 0x71000 | B6 , + TIM8_PWM_MAP1_CH2_B7 = 0x71100 | B7 , + TIM8_PWM_MAP1_CH3_B8 = 0x71200 | B8 , + TIM8_PWM_MAP1_CH4_C13 = 0x71300 | C13, + + //----------------ʱ9---------------- + + // ΪTIM9PWMһӳţӳŻá + // Ĭӳ + TIM9_PWM_MAP0_CH1_A2 = 0x80000 | A2, + TIM9_PWM_MAP0_CH2_A3 = 0x80100 | A3, + TIM9_PWM_MAP0_CH3_A4 = 0x80200 | A4, + TIM9_PWM_MAP0_CH4_C4 = 0x80300 | C4, + + // ΪTIM9PWMһӳţӳŻá + // ȫӳ + TIM9_PWM_MAP3_CH1_D9 = 0x83000 | D9 , + TIM9_PWM_MAP3_CH2_D11 = 0x83100 | D11, + TIM9_PWM_MAP3_CH3_D13 = 0x83200 | D13, + TIM9_PWM_MAP3_CH4_D15 = 0x83300 | D15, + + //----------------ʱ10---------------- + + // ΪTIM10PWMһӳţӳŻá + // Ĭӳ + TIM10_PWM_MAP0_CH1_B8 = 0x90000 | B8 , + TIM10_PWM_MAP0_CH2_B9 = 0x90100 | B9 , + TIM10_PWM_MAP0_CH3_C3 = 0x90200 | C3 , + TIM10_PWM_MAP0_CH4_C11= 0x90300 | C11, + + // ΪTIM10PWMһӳţӳŻá + //ӳ + TIM10_PWM_MAP1_CH1_B3 = 0x91000 | B3 , + TIM10_PWM_MAP1_CH2_B4 = 0x91100 | B4 , + TIM10_PWM_MAP1_CH3_B5 = 0x91200 | B5 , + TIM10_PWM_MAP1_CH4_C15= 0x91300 | C15, + + // ΪTIM10PWMһӳţӳŻá + //ȫӳ + TIM10_PWM_MAP3_CH1_D1 = 0x93000 | D1, + TIM10_PWM_MAP3_CH2_D3 = 0x93100 | D3, + TIM10_PWM_MAP3_CH3_D5 = 0x93200 | D5, + TIM10_PWM_MAP3_CH4_D7 = 0x93300 | D7, + +}pwm_channel_enum; + +#define PWM_DUTY_MAX 10000 + +void pwm_set_duty (pwm_channel_enum pin, uint32 duty); +void pwm_set_freq (pwm_channel_enum pin, uint32 freq, uint32 duty); +void pwm_init (pwm_channel_enum pin, uint32 freq, uint32 duty); + +#endif diff --git a/libraries/zf_driver/zf_driver_soft_iic.c b/libraries/zf_driver/zf_driver_soft_iic.c new file mode 100644 index 0000000..61094df --- /dev/null +++ b/libraries/zf_driver/zf_driver_soft_iic.c @@ -0,0 +1,711 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_soft_iic +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "zf_common_debug.h" + +#include "zf_driver_soft_iic.h" + +#define SOFT_IIC_SDA_IO_SWITCH (0) // ǷҪ SDA I/O л 0-Ҫ 1-Ҫ + +//------------------------------------------------------------------------------------------------------------------- +// IIC ʱ +// ˵ delay ʱ +// ز void +// ʹʾ soft_iic_delay(1); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +//static void soft_iic_delay (vuint32 delay) +//{ +// volatile uint32 count = delay; +// while(count --); +//} +#define soft_iic_delay(x) for(uint32 i = x; i--; ) + +//------------------------------------------------------------------------------------------------------------------- +// IIC START ź +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ز void +// ʹʾ soft_iic_start(soft_iic_obj); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static void soft_iic_start (soft_iic_info_struct *soft_iic_obj) +{ + zf_assert(soft_iic_obj != NULL); + gpio_high(soft_iic_obj->scl_pin); // SCL ߵƽ + gpio_high(soft_iic_obj->sda_pin); // SDA ߵƽ + + soft_iic_delay(soft_iic_obj->delay); + gpio_low(soft_iic_obj->sda_pin); // SDA + soft_iic_delay(soft_iic_obj->delay); + gpio_low(soft_iic_obj->scl_pin); // SCL +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC STOP ź +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ز void +// ʹʾ soft_iic_stop(soft_iic_obj); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static void soft_iic_stop (soft_iic_info_struct *soft_iic_obj) +{ + zf_assert(soft_iic_obj != NULL); + gpio_low(soft_iic_obj->sda_pin); // SDA ͵ƽ + gpio_low(soft_iic_obj->scl_pin); // SCL ͵ƽ + + soft_iic_delay(soft_iic_obj->delay); + gpio_high(soft_iic_obj->scl_pin); // SCL + soft_iic_delay(soft_iic_obj->delay); + gpio_high(soft_iic_obj->sda_pin); // SDA + soft_iic_delay(soft_iic_obj->delay); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ACK/NAKC ź ڲ +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ ack ACK ƽ +// ز void +// ʹʾ soft_iic_send_ack(soft_iic_obj, 1); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static void soft_iic_send_ack (soft_iic_info_struct *soft_iic_obj, uint8 ack) +{ + zf_assert(soft_iic_obj != NULL); + gpio_low(soft_iic_obj->scl_pin); // SCL ͵ƽ + + if(ack) + { + gpio_high(soft_iic_obj->sda_pin); // SDA + } + else + { + gpio_low(soft_iic_obj->sda_pin); // SDA + } + + soft_iic_delay(soft_iic_obj->delay); + gpio_high(soft_iic_obj->scl_pin); // SCL + soft_iic_delay(soft_iic_obj->delay); + gpio_low(soft_iic_obj->scl_pin); // SCL + gpio_high(soft_iic_obj->sda_pin); // SDA +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ȡ ACK/NAKC ź +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ز uint8 ACK ״̬ +// ʹʾ soft_iic_wait_ack(soft_iic_obj); +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static uint8 soft_iic_wait_ack (soft_iic_info_struct *soft_iic_obj) +{ + zf_assert(soft_iic_obj != NULL); + uint8 temp = 0; + gpio_low(soft_iic_obj->scl_pin); // SCL ͵ƽ + gpio_high(soft_iic_obj->sda_pin); // SDA ߵƽ ͷ SDA +#if SOFT_IIC_SDA_IO_SWITCH + gpio_set_dir(soft_iic_obj->sda_pin, GPI, GPI_FLOATING_IN); +#endif + soft_iic_delay(soft_iic_obj->delay); + + gpio_high(soft_iic_obj->scl_pin); // SCL ߵƽ + soft_iic_delay(soft_iic_obj->delay); + + if(gpio_get_level((gpio_pin_enum)soft_iic_obj->sda_pin)) + { + temp = 1; + } + gpio_low(soft_iic_obj->scl_pin); // SCL ͵ƽ +#if SOFT_IIC_SDA_IO_SWITCH + gpio_set_dir(soft_iic_obj->sda_pin, GPO, GPO_OPEN_DTAIN); +#endif + soft_iic_delay(soft_iic_obj->delay); + + return temp; +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC 8bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ data +// ز uint8 ACK ״̬ +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static uint8 soft_iic_send_data (soft_iic_info_struct *soft_iic_obj, const uint8 data) +{ + zf_assert(soft_iic_obj != NULL); + uint8 temp = 0x80; + while(temp) + { +// gpio_set_level(soft_iic_obj->sda_pin, data & temp); + ((data & temp) ? (gpio_high(soft_iic_obj->sda_pin)) : (gpio_low(soft_iic_obj->sda_pin))); + temp >>= 1; + + soft_iic_delay(soft_iic_obj->delay); + gpio_high(soft_iic_obj->scl_pin); // SCL + soft_iic_delay(soft_iic_obj->delay); + gpio_low(soft_iic_obj->scl_pin); // SCL + } + return ((soft_iic_wait_ack(soft_iic_obj) == 1) ? 0 : 1 ); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ȡ 8bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ ack ACK NACK +// ز uint8 +// עϢ ڲ +//------------------------------------------------------------------------------------------------------------------- +static uint8 soft_iic_read_data (soft_iic_info_struct *soft_iic_obj, uint8 ack) +{ + zf_assert(soft_iic_obj != NULL); + uint8 data = 0x00; + uint8 temp = 8; + gpio_low(soft_iic_obj->scl_pin); // SCL ͵ƽ + soft_iic_delay(soft_iic_obj->delay); + gpio_high(soft_iic_obj->sda_pin); // SDA ߵƽ ͷ SDA +#if SOFT_IIC_SDA_IO_SWITCH + gpio_set_dir(soft_iic_obj->sda_pin, GPI, GPI_FLOATING_IN); +#endif + + while(temp --) + { + gpio_low(soft_iic_obj->scl_pin); // SCL + soft_iic_delay(soft_iic_obj->delay); + gpio_high(soft_iic_obj->scl_pin); // SCL + soft_iic_delay(soft_iic_obj->delay); + data = ((data << 1) | gpio_get_level((gpio_pin_enum)soft_iic_obj->sda_pin)); + } + gpio_low(soft_iic_obj->scl_pin); // SCL ͵ƽ +#if SOFT_IIC_SDA_IO_SWITCH + gpio_set_dir(soft_iic_obj->sda_pin, GPO, GPO_OPEN_DTAIN); +#endif + soft_iic_delay(soft_iic_obj->delay); + soft_iic_send_ack(soft_iic_obj, ack); + return data; +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿд 8bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ data Ҫд +// ز void +// ʹʾ soft_iic_write_8bit_register(soft_iic_obj, 0x01); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_write_8bit (soft_iic_info_struct *soft_iic_obj, const uint8 data) +{ + zf_assert(soft_iic_obj != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + soft_iic_send_data(soft_iic_obj, data); + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿд 8bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ *data ݴŻ +// ˵ len +// ز void +// ʹʾ soft_iic_write_8bit_array(soft_iic_obj, data, 6); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_write_8bit_array (soft_iic_info_struct *soft_iic_obj, const uint8 *data, uint32 len) +{ + zf_assert(soft_iic_obj != NULL); + zf_assert(data != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + while(len --) + { + soft_iic_send_data(soft_iic_obj, *data ++); + } + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿд 16bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ data Ҫд +// ز void +// ʹʾ soft_iic_write_16bit(soft_iic_obj, 0x0101); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_write_16bit (soft_iic_info_struct *soft_iic_obj, const uint16 data) +{ + zf_assert(soft_iic_obj != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + soft_iic_send_data(soft_iic_obj, (uint8)((data & 0xFF00) >> 8)); + soft_iic_send_data(soft_iic_obj, (uint8)(data & 0x00FF)); + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿд 16bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ *data ݴŻ +// ˵ len +// ز void +// ʹʾ soft_iic_write_16bit_array(soft_iic_obj, data, 6); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_write_16bit_array (soft_iic_info_struct *soft_iic_obj, const uint16 *data, uint32 len) +{ + zf_assert(soft_iic_obj != NULL); + zf_assert(data != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + while(len --) + { + soft_iic_send_data(soft_iic_obj, (uint8)((*data & 0xFF00) >> 8)); + soft_iic_send_data(soft_iic_obj, (uint8)(*data ++ & 0x00FF)); + } + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿ򴫸Ĵд 8bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ register_name ļĴַ +// ˵ data Ҫд +// ز void +// ʹʾ soft_iic_write_8bit_register(soft_iic_obj, 0x01, 0x01); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_write_8bit_register (soft_iic_info_struct *soft_iic_obj, const uint8 register_name, const uint8 data) +{ + zf_assert(soft_iic_obj != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + soft_iic_send_data(soft_iic_obj, register_name); + soft_iic_send_data(soft_iic_obj, data); + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿ򴫸Ĵд 8bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ register_name ļĴַ +// ˵ *data ݴŻ +// ˵ len +// ز void +// ʹʾ soft_iic_write_8bit_registers(soft_iic_obj, 0x01, data, 6); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_write_8bit_registers (soft_iic_info_struct *soft_iic_obj, const uint8 register_name, const uint8 *data, uint32 len) +{ + zf_assert(soft_iic_obj != NULL); + zf_assert(data != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + soft_iic_send_data(soft_iic_obj, register_name); + while(len --) + { + soft_iic_send_data(soft_iic_obj, *data ++); + } + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿ򴫸Ĵд 16bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ register_name ļĴַ +// ˵ data Ҫд +// ز void +// ʹʾ soft_iic_write_16bit_register(soft_iic_obj, 0x0101, 0x0101); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_write_16bit_register (soft_iic_info_struct *soft_iic_obj, const uint16 register_name, const uint16 data) +{ + zf_assert(soft_iic_obj != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + soft_iic_send_data(soft_iic_obj, (uint8)((register_name & 0xFF00) >> 8)); + soft_iic_send_data(soft_iic_obj, (uint8)(register_name & 0x00FF)); + soft_iic_send_data(soft_iic_obj, (uint8)((data & 0xFF00) >> 8)); + soft_iic_send_data(soft_iic_obj, (uint8)(data & 0x00FF)); + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿ򴫸Ĵд 16bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ register_name ļĴַ +// ˵ *data ݴŻ +// ˵ len +// ز void +// ʹʾ soft_iic_write_16bit_registers(soft_iic_obj, 0x0101, data, 6); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_write_16bit_registers (soft_iic_info_struct *soft_iic_obj, const uint16 register_name, const uint16 *data, uint32 len) +{ + zf_assert(soft_iic_obj != NULL); + zf_assert(data != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + soft_iic_send_data(soft_iic_obj, (uint8)((register_name & 0xFF00) >> 8)); + soft_iic_send_data(soft_iic_obj, (uint8)(register_name & 0x00FF)); + while(len--) + { + soft_iic_send_data(soft_iic_obj, (uint8)((*data & 0xFF00) >> 8)); + soft_iic_send_data(soft_iic_obj, (uint8)(*data ++ & 0x00FF)); + } + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿڶȡ 8bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ز uint8 ضȡ 8bit +// ʹʾ soft_iic_read_8bit(soft_iic_obj); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 soft_iic_read_8bit (soft_iic_info_struct *soft_iic_obj) +{ + zf_assert(soft_iic_obj != NULL); + uint8 temp = 0; + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1 | 0x01); + temp = soft_iic_read_data(soft_iic_obj, 1); + soft_iic_stop(soft_iic_obj); + return temp; +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿڴӴĴȡ 8bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ register_name ļĴַ +// ˵ *data ҪȡݵĻָ +// ˵ len Ҫȡݳ +// ز void +// ʹʾ soft_iic_read_8bit_array(soft_iic_obj, data, 8); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_read_8bit_array (soft_iic_info_struct *soft_iic_obj, uint8 *data, uint32 len) +{ + zf_assert(soft_iic_obj != NULL); + zf_assert(data != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1 | 0x01); + while(len --) + { + *data ++ = soft_iic_read_data(soft_iic_obj, len == 0); + } + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿڶȡ 16bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ register_name ļĴַ +// ز uint16 ضȡ 16bit +// ʹʾ soft_iic_read_16bit(soft_iic_obj); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint16 soft_iic_read_16bit (soft_iic_info_struct *soft_iic_obj) +{ + zf_assert(soft_iic_obj != NULL); + uint16 temp = 0; + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1 | 0x01); + temp = soft_iic_read_data(soft_iic_obj, 0); + temp = ((temp << 8)| soft_iic_read_data(soft_iic_obj, 1)); + soft_iic_stop(soft_iic_obj); + return temp; +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿڶȡ 16bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ *data ҪȡݵĻָ +// ˵ len Ҫȡݳ +// ز void +// ʹʾ soft_iic_read_16bit_array(soft_iic_obj, data, 8); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_read_16bit_array (soft_iic_info_struct *soft_iic_obj, uint16 *data, uint32 len) +{ + zf_assert(soft_iic_obj != NULL); + zf_assert(data != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1 | 0x01); + while(len --) + { + *data = soft_iic_read_data(soft_iic_obj, 0); + *data = ((*data << 8)| soft_iic_read_data(soft_iic_obj, len == 0)); + data ++; + } + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿڴӴĴȡ 8bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ register_name ļĴַ +// ز uint8 ضȡ 8bit +// ʹʾ soft_iic_read_8bit_register(soft_iic_obj, 0x01); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 soft_iic_read_8bit_register (soft_iic_info_struct *soft_iic_obj, const uint8 register_name) +{ + zf_assert(soft_iic_obj != NULL); + uint8 temp = 0; + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + soft_iic_send_data(soft_iic_obj, register_name); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1 | 0x01); + temp = soft_iic_read_data(soft_iic_obj, 1); + soft_iic_stop(soft_iic_obj); + return temp; +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿڴӴĴȡ 8bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ register_name ļĴַ +// ˵ *data ҪȡݵĻָ +// ˵ len Ҫȡݳ +// ز void +// ʹʾ soft_iic_read_8bit_registers(soft_iic_obj, 0x01, data, 8); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_read_8bit_registers (soft_iic_info_struct *soft_iic_obj, const uint8 register_name, uint8 *data, uint32 len) +{ + zf_assert(soft_iic_obj != NULL); + zf_assert(data != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + soft_iic_send_data(soft_iic_obj, register_name); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1 | 0x01); + while(len --) + { + *data ++ = soft_iic_read_data(soft_iic_obj, len == 0); + } + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿڴӴĴȡ 16bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ register_name ļĴַ +// ز uint16 ضȡ 16bit +// ʹʾ soft_iic_read_16bit_register(soft_iic_obj, 0x0101); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint16 soft_iic_read_16bit_register (soft_iic_info_struct *soft_iic_obj, const uint16 register_name) +{ + zf_assert(soft_iic_obj != NULL); + uint16 temp = 0; + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + soft_iic_send_data(soft_iic_obj, (uint8)((register_name & 0xFF00) >> 8)); + soft_iic_send_data(soft_iic_obj, (uint8)(register_name & 0x00FF)); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1 | 0x01); + temp = soft_iic_read_data(soft_iic_obj, 0); + temp = ((temp << 8)| soft_iic_read_data(soft_iic_obj, 1)); + soft_iic_stop(soft_iic_obj); + return temp; +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿڴӴĴȡ 16bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ register_name ļĴַ +// ˵ *data ҪȡݵĻָ +// ˵ len Ҫȡݳ +// ز void +// ʹʾ soft_iic_read_16bit_registers(soft_iic_obj, 0x0101, data, 8); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_read_16bit_registers (soft_iic_info_struct *soft_iic_obj, const uint16 register_name, uint16 *data, uint32 len) +{ + zf_assert(soft_iic_obj != NULL); + zf_assert(data != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + soft_iic_send_data(soft_iic_obj, (uint8)((register_name & 0xFF00) >> 8)); + soft_iic_send_data(soft_iic_obj, (uint8)(register_name & 0x00FF)); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1 | 0x01); + while(len --) + { + *data = soft_iic_read_data(soft_iic_obj, 0); + *data = ((*data << 8)| soft_iic_read_data(soft_iic_obj, len == 0)); + data ++; + } + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿڴ 8bit дȡ +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ *write_data ݴŻ +// ˵ write_len ͻ +// ˵ *read_data ȡݴŻ +// ˵ read_len ȡ +// ز void +// ʹʾ iic_transfer_8bit_array(IIC_1, addr, data, 64, data, 64); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_transfer_8bit_array (soft_iic_info_struct *soft_iic_obj, const uint8 *write_data, uint32 write_len, uint8 *read_data, uint32 read_len) +{ + zf_assert(soft_iic_obj != NULL); + zf_assert(write_data != NULL); + zf_assert(read_data != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + while(write_len --) + { + soft_iic_send_data(soft_iic_obj, *write_data ++); + } + + if(read_len) + { + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1 | 0x01); + while(read_len --) + { + *read_data ++ = soft_iic_read_data(soft_iic_obj, read_len == 0); + } + } + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿڴ 16bit дȡ +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ *write_data ݴŻ +// ˵ write_len ͻ +// ˵ *read_data ȡݴŻ +// ˵ read_len ȡ +// ز void +// ʹʾ iic_transfer_16bit_array(IIC_1, addr, data, 64, data, 64); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_transfer_16bit_array (soft_iic_info_struct *soft_iic_obj, const uint16 *write_data, uint32 write_len, uint16 *read_data, uint32 read_len) +{ + zf_assert(soft_iic_obj != NULL); + zf_assert(write_data != NULL); + zf_assert(read_data != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + while(write_len--) + { + soft_iic_send_data(soft_iic_obj, (uint8)((*write_data & 0xFF00) >> 8)); + soft_iic_send_data(soft_iic_obj, (uint8)(*write_data ++ & 0x00FF)); + } + if(read_len) + { + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1 | 0x01); + while(read_len --) + { + *read_data = soft_iic_read_data(soft_iic_obj, 0); + *read_data = ((*read_data << 8)| soft_iic_read_data(soft_iic_obj, read_len == 0)); + read_data ++; + } + } + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿ SCCB ģʽ򴫸Ĵд 8bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ register_name ļĴַ +// ˵ data Ҫд +// ز void +// ʹʾ soft_iic_sccb_write_register(soft_iic_obj, 0x01, 0x01); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_sccb_write_register (soft_iic_info_struct *soft_iic_obj, const uint8 register_name, uint8 data) +{ + zf_assert(soft_iic_obj != NULL); + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + soft_iic_send_data(soft_iic_obj, register_name); + soft_iic_send_data(soft_iic_obj, data); + soft_iic_stop(soft_iic_obj); +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿ SCCB ģʽӴĴȡ 8bit +// ˵ *soft_iic_obj IIC ָϢ Բ zf_driver_soft_iic.h ĸʽ +// ˵ register_name ļĴַ +// ز uint8 ضȡ 8bit +// ʹʾ soft_iic_sccb_read_register(soft_iic_obj, 0x01); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +uint8 soft_iic_sccb_read_register (soft_iic_info_struct *soft_iic_obj, const uint8 register_name) +{ + zf_assert(soft_iic_obj != NULL); + uint8 temp = 0; + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1); + soft_iic_send_data(soft_iic_obj, register_name); + soft_iic_stop(soft_iic_obj); + + soft_iic_start(soft_iic_obj); + soft_iic_send_data(soft_iic_obj, soft_iic_obj->addr << 1 | 0x01); + temp = soft_iic_read_data(soft_iic_obj, 1); + soft_iic_stop(soft_iic_obj); + return temp; +} + +//------------------------------------------------------------------------------------------------------------------- +// IIC ӿڳʼ Ĭ MASTER ģʽ ṩ SLAVE ģʽ +// ˵ *soft_iic_obj IIC ָϢŽṹָ +// ˵ addr IIC ַ Ҫע ׼λַ λ дʱȷ +// ˵ delay IIC ʱ ʱӸߵƽʱ Խ IIC Խ +// ˵ scl_pin IIC ʱ zf_driver_gpio.h gpio_pin_enum ö嶨 +// ˵ sda_pin IIC zf_driver_gpio.h gpio_pin_enum ö嶨 +// ز void +// ʹʾ soft_iic_init(&soft_iic_obj, addr, 100, B6, B7); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void soft_iic_init (soft_iic_info_struct *soft_iic_obj, uint8 addr, uint32 delay, gpio_pin_enum scl_pin, gpio_pin_enum sda_pin) +{ + zf_assert(soft_iic_obj != NULL); + zf_assert(scl_pin != sda_pin); // ѣ scl_pin sda_pin ôͬһţ + soft_iic_obj->scl_pin = scl_pin; + soft_iic_obj->sda_pin = sda_pin; + soft_iic_obj->addr = addr; + soft_iic_obj->delay = delay; + gpio_init(scl_pin, GPO, GPIO_HIGH, GPO_PUSH_PULL); // ȡӦIO AFܱ + gpio_init(sda_pin, GPO, GPIO_HIGH, GPO_OPEN_DTAIN); // ȡӦIO AFܱ +} diff --git a/libraries/zf_driver/zf_driver_soft_iic.h b/libraries/zf_driver/zf_driver_soft_iic.h new file mode 100644 index 0000000..1323324 --- /dev/null +++ b/libraries/zf_driver/zf_driver_soft_iic.h @@ -0,0 +1,83 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_soft_iic +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_soft_iic_h_ +#define _zf_driver_soft_iic_h_ + + +#include "zf_driver_gpio.h" + +typedef struct +{ + gpio_pin_enum scl_pin; // ڼ¼Ӧű + gpio_pin_enum sda_pin; // ڼ¼Ӧű + uint8 addr; // ַ λַģʽ + uint32 delay; // ģ IIC ʱʱ +}soft_iic_info_struct; + +void soft_iic_write_8bit (soft_iic_info_struct *soft_iic_obj, const uint8 data); +void soft_iic_write_8bit_array (soft_iic_info_struct *soft_iic_obj, const uint8 *data, uint32 len); + +void soft_iic_write_16bit (soft_iic_info_struct *soft_iic_obj, const uint16 data); +void soft_iic_write_16bit_array (soft_iic_info_struct *soft_iic_obj, const uint16 *data, uint32 len); + +void soft_iic_write_8bit_register (soft_iic_info_struct *soft_iic_obj, const uint8 register_name, const uint8 data); +void soft_iic_write_8bit_registers (soft_iic_info_struct *soft_iic_obj, const uint8 register_name, const uint8 *data, uint32 len); + +void soft_iic_write_16bit_register (soft_iic_info_struct *soft_iic_obj, const uint16 register_name, const uint16 data); +void soft_iic_write_16bit_registers (soft_iic_info_struct *soft_iic_obj, const uint16 register_name, const uint16 *data, uint32 len); + +uint8 soft_iic_read_8bit (soft_iic_info_struct *soft_iic_obj); +void soft_iic_read_8bit_array (soft_iic_info_struct *soft_iic_obj, uint8 *data, uint32 len); + +uint16 soft_iic_read_16bit (soft_iic_info_struct *soft_iic_obj); +void soft_iic_read_16bit_array (soft_iic_info_struct *soft_iic_obj, uint16 *data, uint32 len); + +uint8 soft_iic_read_8bit_register (soft_iic_info_struct *soft_iic_obj, const uint8 register_name); +void soft_iic_read_8bit_registers (soft_iic_info_struct *soft_iic_obj, const uint8 register_name, uint8 *data, uint32 len); + +uint16 soft_iic_read_16bit_register (soft_iic_info_struct *soft_iic_obj, const uint16 register_name); +void soft_iic_read_16bit_registers (soft_iic_info_struct *soft_iic_obj, const uint16 register_name, uint16 *data, uint32 len); + +void soft_iic_transfer_8bit_array (soft_iic_info_struct *soft_iic_obj, const uint8 *write_data, uint32 write_len, uint8 *read_data, uint32 read_len); +void soft_iic_transfer_16bit_array (soft_iic_info_struct *soft_iic_obj, const uint16 *write_data, uint32 write_len, uint16 *read_data, uint32 read_len); + +void soft_iic_sccb_write_register (soft_iic_info_struct *soft_iic_obj, const uint8 register_name, uint8 data); +uint8 soft_iic_sccb_read_register (soft_iic_info_struct *soft_iic_obj, const uint8 register_name); + +void soft_iic_init (soft_iic_info_struct *soft_iic_obj, uint8 addr, uint32 delay, gpio_pin_enum scl_pin, gpio_pin_enum sda_pin); + +#endif + diff --git a/libraries/zf_driver/zf_driver_soft_spi.c b/libraries/zf_driver/zf_driver_soft_spi.c new file mode 100644 index 0000000..c21b3e4 --- /dev/null +++ b/libraries/zf_driver/zf_driver_soft_spi.c @@ -0,0 +1,621 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_driver_soft_spi +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ + +#include "zf_common_debug.h" + +#include "zf_driver_soft_spi.h" + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 延时 +// 参数说明 void +// 返回参数 void +// 使用示例 soft_spi_delay(1); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +//static void soft_spi_delay (uint32 delay) +//{ +// volatile uint32 count = delay; +// while(count --); +//} +#define soft_spi_delay(x) for(uint32 i = x; i--;) + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 8bit 数据读写 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 data 数据 +// 返回参数 uint8 读取的数据 +// 使用示例 soft_spi_8bit_data_handler(soft_spi_obj, 1); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static uint8 soft_spi_8bit_data_handler (soft_spi_info_struct *soft_spi_obj, const uint8 data) +{ + uint8 temp = 0; + uint8 write_data = data; + uint8 read_data = 0; + + if(soft_spi_obj->config.use_cs) + { + gpio_low(soft_spi_obj->cs_pin); + } + + if(0 == soft_spi_obj->config.mode || 1 == soft_spi_obj->config.mode) // CPOL = 0 SCK 空闲低电平 + { + gpio_low(soft_spi_obj->sck_pin); + } + else // CPOL = 1 SCK 空闲高电平 + { + gpio_high(soft_spi_obj->sck_pin); + } + + if(0 == soft_spi_obj->config.mode % 2) // CPHA = 0 第一个边沿采样 + { + for(temp = 8; temp > 0; temp --) + { + if(0x80 & write_data) + { + gpio_high(soft_spi_obj->mosi_pin); + } + else + { + gpio_low(soft_spi_obj->mosi_pin); + } + soft_spi_delay(soft_spi_obj->delay); + gpio_toggle_level(soft_spi_obj->sck_pin); + write_data = write_data << 1; + read_data = read_data << 1; + if(soft_spi_obj->config.use_miso) + { + read_data |= gpio_get_level(soft_spi_obj->miso_pin); + } + soft_spi_delay(soft_spi_obj->delay); + gpio_toggle_level(soft_spi_obj->sck_pin); + } + } + else // CPHA = 1 第二个边沿采样 + { + for(temp = 8; 0 < temp; temp --) + { + gpio_toggle_level(soft_spi_obj->sck_pin); + if(0x80 & write_data) + { + gpio_high(soft_spi_obj->mosi_pin); + } + else + { + gpio_low(soft_spi_obj->mosi_pin); + } + soft_spi_delay(soft_spi_obj->delay); + gpio_toggle_level(soft_spi_obj->sck_pin); + write_data = write_data << 1; + read_data = read_data << 1; + if(soft_spi_obj->config.use_miso) + { + read_data |= gpio_get_level(soft_spi_obj->miso_pin); + } + soft_spi_delay(soft_spi_obj->delay); + } + } + + if(soft_spi_obj->config.use_cs) + { + gpio_high(soft_spi_obj->cs_pin); + } + return read_data; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 16bit 数据读写 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 data 数据 +// 返回参数 uint16 读取的数据 +// 使用示例 soft_spi_16bit_data_handler(soft_spi_obj, 1); +// 备注信息 内部调用 +//------------------------------------------------------------------------------------------------------------------- +static uint16 soft_spi_16bit_data_handler (soft_spi_info_struct *soft_spi_obj, const uint16 data) +{ + uint8 temp = 0; + uint16 write_data = data; + uint16 read_data = 0; + + if(soft_spi_obj->config.use_cs) + { + gpio_low(soft_spi_obj->cs_pin); + } + + if(0 == soft_spi_obj->config.mode || 1 == soft_spi_obj->config.mode) // CPOL = 0 SCK 空闲低电平 + { + gpio_low(soft_spi_obj->sck_pin); + } + else // CPOL = 1 SCK 空闲高电平 + { + gpio_high(soft_spi_obj->sck_pin); + } + + if(0 == soft_spi_obj->config.mode % 2) // CPHA = 0 第一个边沿采样 + { + for(temp = 16; 0 < temp; temp --) + { + if(0x8000 & write_data) + { + gpio_high(soft_spi_obj->mosi_pin); + } + else + { + gpio_low(soft_spi_obj->mosi_pin); + } + soft_spi_delay(soft_spi_obj->delay); + gpio_toggle_level(soft_spi_obj->sck_pin); + write_data = write_data << 1; + read_data = read_data << 1; + if(soft_spi_obj->config.use_miso) + { + read_data |= gpio_get_level(soft_spi_obj->miso_pin); + } + soft_spi_delay(soft_spi_obj->delay); + gpio_toggle_level(soft_spi_obj->sck_pin); + } + } + else // CPHA = 1 第二个边沿采样 + { + for(temp = 16; 0 < temp; temp --) + { + gpio_toggle_level(soft_spi_obj->sck_pin); + if(write_data & 0x8000) + { + gpio_high(soft_spi_obj->mosi_pin); + } + else + { + gpio_low(soft_spi_obj->mosi_pin); + } + soft_spi_delay(soft_spi_obj->delay); + gpio_toggle_level(soft_spi_obj->sck_pin); + write_data = write_data << 1; + read_data = read_data << 1; + if(soft_spi_obj->config.use_miso) + { + read_data |= gpio_get_level(soft_spi_obj->miso_pin); + } + soft_spi_delay(soft_spi_obj->delay); + } + } + + if(soft_spi_obj->config.use_cs) + { + gpio_high(soft_spi_obj->cs_pin); + } + return read_data; +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口写 8bit 数据 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 data 发送的数据 +// 返回参数 void +// 使用示例 soft_spi_write_8bit(&soft_spi_obj, 1); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_write_8bit (soft_spi_info_struct *soft_spi_obj, const uint8 data) +{ + zf_assert(soft_spi_obj != NULL); + soft_spi_8bit_data_handler(soft_spi_obj, data); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口写 8bit 数组 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 *data 数据存放缓冲区 +// 参数说明 len 缓冲区长度 +// 返回参数 void +// 使用示例 soft_spi_write_8bit_array(&soft_spi_obj, buf, 16); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_write_8bit_array (soft_spi_info_struct *soft_spi_obj, const uint8 *data, uint32 len) +{ + zf_assert(soft_spi_obj != NULL); + zf_assert(data != NULL); + while(len --) + { + soft_spi_8bit_data_handler(soft_spi_obj, *data ++); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口写 16bit 数据 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 data 发送的数据 +// 返回参数 void +// 使用示例 soft_spi_write_16bit(&soft_spi_obj, 1); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_write_16bit (soft_spi_info_struct *soft_spi_obj, uint16 data) +{ + zf_assert(soft_spi_obj != NULL); + soft_spi_16bit_data_handler(soft_spi_obj, data); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口写 16bit 数组 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 *data 数据存放缓冲区 +// 参数说明 len 缓冲区长度 +// 返回参数 void +// 使用示例 soft_spi_write_16bit_array(&soft_spi_obj, buf, 16); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_write_16bit_array (soft_spi_info_struct *soft_spi_obj, const uint16 *data, uint32 len) +{ + zf_assert(soft_spi_obj != NULL); + zf_assert(data != NULL); + while(len --) + { + soft_spi_16bit_data_handler(soft_spi_obj, *data ++); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口向传感器的寄存器写 8bit 数据 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 register_name 寄存器地址 +// 参数说明 data 发送的数据 +// 返回参数 void +// 使用示例 soft_spi_write_8bit_register(&soft_spi_obj, 1, 1); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_write_8bit_register (soft_spi_info_struct *soft_spi_obj, const uint8 register_name, const uint8 data) +{ + zf_assert(soft_spi_obj != NULL); + soft_spi_8bit_data_handler(soft_spi_obj, register_name); + soft_spi_8bit_data_handler(soft_spi_obj, data); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口向传感器的寄存器写 8bit 数组 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 register_name 寄存器地址 +// 参数说明 *data 数据存放缓冲区 +// 参数说明 len 缓冲区长度 +// 返回参数 void +// 使用示例 soft_spi_write_8bit_registers(&soft_spi_obj, 1, buf, 16); +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_write_8bit_registers (soft_spi_info_struct *soft_spi_obj, const uint8 register_name, const uint8 *data, uint32 len) +{ + zf_assert(soft_spi_obj != NULL); + zf_assert(data != NULL); + soft_spi_8bit_data_handler(soft_spi_obj, register_name); + while(len --) + { + soft_spi_8bit_data_handler(soft_spi_obj, *data ++); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口向传感器的寄存器写 16bit 数据 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 register_name 寄存器地址 +// 参数说明 data 发送的数据 +// 返回参数 void +// 使用示例 soft_spi_write_16bit_register(&soft_spi_obj, 1, 1); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_write_16bit_register (soft_spi_info_struct *soft_spi_obj, const uint16 register_name, uint16 data) +{ + zf_assert(soft_spi_obj != NULL); + soft_spi_16bit_data_handler(soft_spi_obj, register_name); + soft_spi_16bit_data_handler(soft_spi_obj, data); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口向传感器的寄存器写 16bit 数组 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 register_name 寄存器地址 +// 参数说明 *data 数据存放缓冲区 +// 参数说明 len 缓冲区长度 +// 返回参数 void +// 使用示例 soft_spi_write_16bit_registers(&soft_spi_obj, 1, buf, 16); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_write_16bit_registers (soft_spi_info_struct *soft_spi_obj, const uint16 register_name, const uint16 *data, uint32 len) +{ + zf_assert(soft_spi_obj != NULL); + zf_assert(data != NULL); + soft_spi_16bit_data_handler(soft_spi_obj, register_name); + while(len --) + { + soft_spi_16bit_data_handler(soft_spi_obj, *data ++); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口读 8bit 数据 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 data 发送的数据 +// 返回参数 uint8 返回读取的 8bit 数据 +// 使用示例 soft_spi_read_8bit(&soft_spi_obj); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +uint8 soft_spi_read_8bit (soft_spi_info_struct *soft_spi_obj) +{ + zf_assert(soft_spi_obj != NULL); + return soft_spi_8bit_data_handler(soft_spi_obj, 0); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口读 8bit 数组 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 *data 数据存放缓冲区 +// 参数说明 len 缓冲区长度 +// 返回参数 void +// 使用示例 soft_spi_read_8bit_array(&soft_spi_obj, buf, 16); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_read_8bit_array (soft_spi_info_struct *soft_spi_obj, uint8 *data, uint32 len) +{ + zf_assert(soft_spi_obj != NULL); + zf_assert(data != NULL); + while(len --) + { + *data ++ = soft_spi_8bit_data_handler(soft_spi_obj, 0); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口读 16bit 数据 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 data 发送的数据 +// 返回参数 uint16 返回读取的 16bit 数据 +// 使用示例 soft_spi_read_16bit(&soft_spi_obj); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +uint16 soft_spi_read_16bit (soft_spi_info_struct *soft_spi_obj) +{ + zf_assert(soft_spi_obj != NULL); + return soft_spi_16bit_data_handler(soft_spi_obj, 0); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口读 16bit 数组 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 *data 数据存放缓冲区 +// 参数说明 len 缓冲区长度 +// 返回参数 void +// 使用示例 soft_spi_read_16bit_array(&soft_spi_obj, buf, 16); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_read_16bit_array (soft_spi_info_struct *soft_spi_obj, uint16 *data, uint32 len) +{ + zf_assert(soft_spi_obj != NULL); + zf_assert(data != NULL); + while(len --) + { + *data ++ = soft_spi_16bit_data_handler(soft_spi_obj, 0); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口从传感器的寄存器读 8bit 数据 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 register_name 寄存器地址 +// 参数说明 data 发送的数据 +// 返回参数 uint8 返回读取的 8bit 数据 +// 使用示例 soft_spi_read_8bit_register(&soft_spi_obj, 0x01, 0x01); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +uint8 soft_spi_read_8bit_register (soft_spi_info_struct *soft_spi_obj, const uint8 register_name) +{ + zf_assert(soft_spi_obj != NULL); + soft_spi_8bit_data_handler(soft_spi_obj, register_name); + return soft_spi_8bit_data_handler(soft_spi_obj, 0); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口从传感器的寄存器读 8bit 数组 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 register_name 寄存器地址 +// 参数说明 *data 数据存放缓冲区 +// 参数说明 len 缓冲区长度 +// 返回参数 void +// 使用示例 soft_spi_read_8bit_registers(&soft_spi_obj, 0x01, buf, 16); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_read_8bit_registers (soft_spi_info_struct *soft_spi_obj, const uint8 register_name, uint8 *data, uint32 len) +{ + zf_assert(soft_spi_obj != NULL); + zf_assert(data != NULL); + soft_spi_8bit_data_handler(soft_spi_obj, register_name); + while(len --) + { + *data ++ = soft_spi_8bit_data_handler(soft_spi_obj, 0); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口从传感器的寄存器读 16bit 数据 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 register_name 寄存器地址 +// 参数说明 data 发送的数据 +// 返回参数 uint16 返回读取的 16bit 数据 +// 使用示例 soft_spi_read_16bit_register(&soft_spi_obj, 0x0101); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +uint16 soft_spi_read_16bit_register (soft_spi_info_struct *soft_spi_obj, const uint16 register_name) +{ + zf_assert(soft_spi_obj != NULL); + soft_spi_16bit_data_handler(soft_spi_obj, register_name); + return soft_spi_16bit_data_handler(soft_spi_obj, 0); +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口从传感器的寄存器读 16bit 数组 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 register_name 寄存器地址 +// 参数说明 *data 数据存放缓冲区 +// 参数说明 len 缓冲区长度 +// 返回参数 void +// 使用示例 soft_spi_read_16bit_registers(&soft_spi_obj, 0x0101, buf, 16); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_read_16bit_registers (soft_spi_info_struct *soft_spi_obj, const uint16 register_name, uint16 *data, uint32 len) +{ + zf_assert(soft_spi_obj != NULL); + zf_assert(data != NULL); + soft_spi_16bit_data_handler(soft_spi_obj, register_name); + while(len --) + { + *data ++ = soft_spi_16bit_data_handler(soft_spi_obj, 0); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 8bit 数据传输 发送与接收数据是同时进行的 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 write_buffer 发送的数据缓冲区地址 +// 参数说明 read_buffer 发送数据时接收到的数据的存储地址(不需要接收则传 NULL) +// 参数说明 len 发送的字节数 +// 返回参数 void +// 使用示例 soft_spi_transfer_8bit(&soft_spi_obj, buf, buf, 1); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_transfer_8bit (soft_spi_info_struct *soft_spi_obj, const uint8 *write_buffer, uint8 *read_buffer, uint32 len) +{ + zf_assert(soft_spi_obj != NULL); + zf_assert(write_buffer != NULL); + while(len --) + { + if(read_buffer != NULL) + { + *read_buffer = soft_spi_8bit_data_handler(soft_spi_obj, *write_buffer); + write_buffer ++; + read_buffer ++; + } + else + { + soft_spi_8bit_data_handler(soft_spi_obj, *write_buffer); + write_buffer ++; + } + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 16bit 数据传输 发送与接收数据是同时进行的 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 write_buffer 发送的数据缓冲区地址 +// 参数说明 read_buffer 发送数据时接收到的数据的存储地址(不需要接收则传 NULL) +// 参数说明 len 发送的字节数 +// 返回参数 void +// 使用示例 soft_spi_transfer_16bit(&soft_spi_obj, buf, buf, 1); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_transfer_16bit (soft_spi_info_struct *soft_spi_obj, const uint16 *write_buffer, uint16 *read_buffer, uint32 len) +{ + zf_assert(soft_spi_obj != NULL); + zf_assert(write_buffer != NULL); + while(len --) + { + if(read_buffer != NULL) + { + *read_buffer = soft_spi_16bit_data_handler(soft_spi_obj, *write_buffer); + write_buffer ++; + read_buffer ++; + } + else + { + soft_spi_16bit_data_handler(soft_spi_obj, *write_buffer); + write_buffer ++; + } + } +} + +//------------------------------------------------------------------------------------------------------------------- +// 函数简介 软件 SPI 接口初始化 +// 参数说明 *soft_spi_obj 软件 SPI 指定信息存放结构体的指针 +// 参数说明 mode SPI 模式 参照 zf_driver_spi.h 内 spi_mode_enum 枚举体定义 +// 参数说明 delay 软件 SPI 延时 就是时钟高电平时间 越短 SPI 速率越高 +// 参数说明 sck_pin 选择 SCK 引脚 参照 zf_driver_gpio.h 内 gpio_pin_enum 枚举体定义 +// 参数说明 mosi_pin 选择 MOSI 引脚 参照 zf_driver_gpio.h 内 gpio_pin_enum 枚举体定义 +// 参数说明 miso_pin 选择 MISO 引脚 如果不需要这个引脚 就填 SOFT_SPI_PIN_NULL +// 参数说明 cs_pin 选择 CS 引脚 如果不需要这个引脚 就填 SOFT_SPI_PIN_NULL +// 返回参数 void +// 使用示例 spi_init(SPI_1, 0, 1*1000*1000, A5, A7, A6, A4); +// 备注信息 +//------------------------------------------------------------------------------------------------------------------- +void soft_spi_init (soft_spi_info_struct *soft_spi_obj, uint8 mode, uint32 delay, gpio_pin_enum sck_pin, gpio_pin_enum mosi_pin, uint32 miso_pin, uint32 cs_pin) +{ + zf_assert(soft_spi_obj != NULL); + zf_assert(sck_pin != mosi_pin); // sck_pin 与 mosi_pin 怎么能填同一个引脚？ + zf_assert(sck_pin != miso_pin); // sck_pin 与 miso_pin 怎么能填同一个引脚？ + zf_assert(sck_pin != cs_pin); // sck_pin 与 cs_pin 怎么能填同一个引脚？ + zf_assert(mosi_pin != miso_pin); // mosi_pin 与 miso_pin 怎么能填同一个引脚？ + zf_assert(mosi_pin != cs_pin); // mosi_pin 与 cs_pin 怎么能填同一个引脚？ + zf_assert((miso_pin != cs_pin) || (cs_pin == SOFT_SPI_PIN_NULL)); // miso_pin 与 cs_pin 怎么能填同一个引脚？ + + zf_assert(4 > mode); // 参照 zf_driver_spi.h 内 spi_mode_enum 枚举体定义 + + soft_spi_obj->config.mode = mode; + soft_spi_obj->delay = delay; + + soft_spi_obj->sck_pin = sck_pin; + soft_spi_obj->mosi_pin = mosi_pin; + if(0 == mode || 1 == mode) + { + gpio_init(sck_pin, GPO, GPIO_LOW, GPO_PUSH_PULL); // IO 初始化 + } + else + { + gpio_init(sck_pin, GPO, GPIO_HIGH, GPO_PUSH_PULL); // IO 初始化 + } + gpio_init(mosi_pin, GPO, GPIO_HIGH, GPO_PUSH_PULL); // IO 初始化 + + if(SOFT_SPI_PIN_NULL == miso_pin) + { + soft_spi_obj->config.use_miso = 0; + } + else + { + soft_spi_obj->config.use_miso = 1; + soft_spi_obj->miso_pin = (gpio_pin_enum)miso_pin; + gpio_init(soft_spi_obj->miso_pin, GPI, GPIO_HIGH, GPI_FLOATING_IN); // IO 初始化 + } + if(SOFT_SPI_PIN_NULL == cs_pin) + { + soft_spi_obj->config.use_cs = 0; + } + else + { + soft_spi_obj->config.use_cs = 1; + soft_spi_obj->cs_pin = (gpio_pin_enum)cs_pin; + gpio_init(soft_spi_obj->cs_pin, GPO, GPIO_HIGH, GPO_PUSH_PULL); // IO 初始化 + } +} diff --git a/libraries/zf_driver/zf_driver_soft_spi.h b/libraries/zf_driver/zf_driver_soft_spi.h new file mode 100644 index 0000000..4454c71 --- /dev/null +++ b/libraries/zf_driver/zf_driver_soft_spi.h @@ -0,0 +1,91 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库 +* Copyright (c) 2022 SEEKFREE 逐飞科技 +* +* 本文件是CH32V307VCT6 开源库的一部分 +* +* CH32V307VCT6 开源库 是免费软件 +* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款 +* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它 +* +* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证 +* 甚至没有隐含的适销性或适合特定用途的保证 +* 更多细节请参见 GPL +* +* 您应该在收到本开源库的同时收到一份 GPL 的副本 +* 如果没有，请参阅 +* +* 额外注明： +* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本 +* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中 +* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件 +* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明） +* +* 文件名称 zf_driver_soft_spi +* 公司名称 成都逐飞科技有限公司 +* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明 +* 开发环境 MounRiver Studio V1.8.1 +* 适用平台 CH32V307VCT6 +* 店铺链接 https://seekfree.taobao.com/ +* +* 修改记录 +* 日期 作者 备注 +* 2022-09-15 大W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_soft_spi_h_ +#define _zf_driver_soft_spi_h_ + +#include "zf_driver_gpio.h" + +#define SOFT_SPI_PIN_NULL (0xFFFF) // 用于区分是否分配引脚 + +typedef struct +{ + union + { + uint8 config_info; // 配置整体数据 + struct + { + uint8 mode :6; // SPI 模式 + uint8 use_miso :1; // 是否使用 MISO 引脚 + uint8 use_cs :1; // 是否使用 CS 引脚 + }; + }config; + gpio_pin_enum sck_pin; // 用于记录对应的引脚编号 + gpio_pin_enum mosi_pin; // 用于记录对应的引脚编号 + gpio_pin_enum miso_pin; // 用于记录对应的引脚编号 + gpio_pin_enum cs_pin; // 用于记录对应的引脚编号 + uint32 delay; // 模拟 SPI 软延时时长 +}soft_spi_info_struct; + +void soft_spi_write_8bit (soft_spi_info_struct *soft_spi_obj, const uint8 data); +void soft_spi_write_8bit_array (soft_spi_info_struct *soft_spi_obj, const uint8 *data, uint32 len); + +void soft_spi_write_16bit (soft_spi_info_struct *soft_spi_obj, const uint16 data); +void soft_spi_write_16bit_array (soft_spi_info_struct *soft_spi_obj, const uint16 *data, uint32 len); + +void soft_spi_write_8bit_register (soft_spi_info_struct *soft_spi_obj, const uint8 register_name, const uint8 data); +void soft_spi_write_8bit_registers (soft_spi_info_struct *soft_spi_obj, const uint8 register_name, const uint8 *data, uint32 len); + +void soft_spi_write_16bit_register (soft_spi_info_struct *soft_spi_obj, const uint16 register_name, const uint16 data); +void soft_spi_write_16bit_registers (soft_spi_info_struct *soft_spi_obj, const uint16 register_name, const uint16 *data, uint32 len); + +uint8 soft_spi_read_8bit (soft_spi_info_struct *soft_spi_obj); +void soft_spi_read_8bit_array (soft_spi_info_struct *soft_spi_obj, uint8 *data, uint32 len); + +uint16 soft_spi_read_16bit (soft_spi_info_struct *soft_spi_obj); +void soft_spi_read_16bit_array (soft_spi_info_struct *soft_spi_obj, uint16 *data, uint32 len); + +uint8 soft_spi_read_8bit_register (soft_spi_info_struct *soft_spi_obj, const uint8 register_name); +void soft_spi_read_8bit_registers (soft_spi_info_struct *soft_spi_obj, const uint8 register_name, uint8 *data, uint32 len); + +uint16 soft_spi_read_16bit_register (soft_spi_info_struct *soft_spi_obj, const uint16 register_name); +void soft_spi_read_16bit_registers (soft_spi_info_struct *soft_spi_obj, const uint16 register_name, uint16 *data, uint32 len); + +void soft_spi_transfer_8bit (soft_spi_info_struct *soft_spi_obj, const uint8 *write_buffer, uint8 *read_buffer, uint32 len); +void soft_spi_transfer_16bit (soft_spi_info_struct *soft_spi_obj, const uint16 *write_buffer, uint16 *read_buffer, uint32 len); + +void soft_spi_init (soft_spi_info_struct *soft_spi_obj, uint8 mode, uint32 delay, gpio_pin_enum sck_pin, gpio_pin_enum mosi_pin, uint32 miso_pin, uint32 cs_pin); + +#endif diff --git a/libraries/zf_driver/zf_driver_spi.c b/libraries/zf_driver/zf_driver_spi.c new file mode 100644 index 0000000..74373b5 --- /dev/null +++ b/libraries/zf_driver/zf_driver_spi.c @@ -0,0 +1,544 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_spi +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "zf_driver_gpio.h" +#include "zf_driver_spi.h" + +const uint32 spi_index[3] = {SPI1_BASE, SPI2_BASE, SPI3_BASE}; + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿд 8bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ data +// ز void +// ʹʾ spi_write_8bit(SPI_1,0x11); +//------------------------------------------------------------------------------------------------------------------- +void spi_write_8bit (spi_index_enum spi_n, const uint8 dat) +{ + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = dat; // + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); // Ϊ + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿд 8bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ *data ݴŻ +// ˵ len +// ز void +// ʹʾ spi_write_8bit_array(SPI_1,data,64); +//------------------------------------------------------------------------------------------------------------------- +void spi_write_8bit_array (spi_index_enum spi_n, const uint8 *dat, uint32 len) +{ + while(len--) + { + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = *(dat++); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿд 16bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ data +// ز void +// ʹʾ spi_write_16bit(SPI_1,0x1101); +//------------------------------------------------------------------------------------------------------------------- +void spi_write_16bit (spi_index_enum spi_n, const uint16 dat) +{ + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)((dat & 0xFF00)>>8); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)(dat & 0x00FF); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿд 16bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ *data ݴŻ +// ˵ len +// ز void +// ʹʾ spi_write_16bit_array(SPI_1,data,64); +//------------------------------------------------------------------------------------------------------------------- +void spi_write_16bit_array (spi_index_enum spi_n, const uint16 *dat, uint32 len) +{ + while(len--) + { + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)((*dat & 0xFF00)>>8); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)(*dat++ & 0x00FF); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿ򴫸ļĴд 8bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ register_name Ĵַ +// ˵ data +// ز void +// ʹʾ spi_write_8bit_register(SPI_1,0x11,0x01); +//------------------------------------------------------------------------------------------------------------------- +void spi_write_8bit_register (spi_index_enum spi_n, const uint8 register_name, const uint8 dat) +{ + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = register_name; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY)); + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = dat; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY)); + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿ򴫸ļĴд 8bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ register_name Ĵַ +// ˵ *data ݴŻ +// ˵ len +// ز void +// ʹʾ spi_write_8bit_registers(SPI_1,0x11,data,32); +//------------------------------------------------------------------------------------------------------------------- +void spi_write_8bit_registers (spi_index_enum spi_n, const uint8 register_name, const uint8 *dat, uint32 len) +{ + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = register_name; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + + while(len--) + { + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = *dat++; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + } +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿ򴫸ļĴд 16bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ register_name Ĵַ +// ˵ data +// ز void +// ʹʾ spi_write_16bit_register(SPI_1,0x1011,0x0101); +//------------------------------------------------------------------------------------------------------------------- +void spi_write_16bit_register (spi_index_enum spi_n, const uint16 register_name, const uint16 dat) +{ + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)((register_name & 0xFF00)>>8); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)(register_name & 0x00FF); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)((dat & 0xFF00)>>8); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)(dat & 0x00FF); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿ򴫸ļĴд 16bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ register_name Ĵַ +// ˵ *data ݴŻ +// ˵ len +// ز void +// ʹʾ spi_write_16bit_registers(SPI_1,0x1011,data,32); +//------------------------------------------------------------------------------------------------------------------- +void spi_write_16bit_registers (spi_index_enum spi_n, const uint16 register_name, const uint16 *dat, uint32 len) +{ + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)((register_name & 0xFF00)>>8); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)(register_name & 0x00FF); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + + while(len--) + { + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)((*dat & 0xFF00)>>8); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)(*dat++ & 0x00FF); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + } + +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿڶ 8bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ register_name Ĵַ +// ز uint8 +// ʹʾ spi_read_8bit(SPI_1); +//------------------------------------------------------------------------------------------------------------------- +uint8 spi_read_8bit (spi_index_enum spi_n) +{ + uint8 dat = 0; + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = 0; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + + //while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_RXNE) == RESET); + dat = ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + + return dat; +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿڶ 8bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ *data ݴŻ +// ˵ len ͻ +// ز void +// ʹʾ spi_read_8bit_array(SPI_1,data,64); +//------------------------------------------------------------------------------------------------------------------- +void spi_read_8bit_array (spi_index_enum spi_n, uint8 *dat, uint32 len) +{ + while(len--) + { + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = 0; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + //while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_RXNE) == RESET); + *dat++ = ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿڶ 16bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ register_name Ĵַ +// ز uint16 +// ʹʾ spi_read_16bit(SPI_1); +//------------------------------------------------------------------------------------------------------------------- +uint16 spi_read_16bit (spi_index_enum spi_n) +{ + uint16 dat = 0; + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = 0; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + dat = ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = 0; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + dat = ((dat << 8)| ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR); + + return dat; +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿڶ 16bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ *data ݴŻ +// ˵ len ͻ +// ز void +// ʹʾ spi_read_16bit_array(SPI_1,data,64); +//------------------------------------------------------------------------------------------------------------------- +void spi_read_16bit_array (spi_index_enum spi_n, uint16 *dat, uint32 len) +{ + while(len--) + { + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = 0; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + //while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_RXNE) == RESET); + *dat = ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = 0; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + //while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_RXNE) == RESET); + *dat = ((*dat << 8)| ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR); + dat++; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿڴӴļĴ 8bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ register_name Ĵַ +// ز uint8 +// ʹʾ spi_read_8bit_register(SPI_1,0x11); + //------------------------------------------------------------------------------------------------------------------- +uint8 spi_read_8bit_register (spi_index_enum spi_n, const uint8 register_name) +{ + uint8 dat; + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = register_name; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY)); + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = 2; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY)); + dat = ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + + + return dat; +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿڴӴļĴ 8bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ register_name Ĵַ +// ˵ *data ݴŻ +// ˵ len ͻ +// ز void +// ʹʾ spi_read_8bit_registers(SPI_1,0x11,data,32); +//------------------------------------------------------------------------------------------------------------------- +void spi_read_8bit_registers (spi_index_enum spi_n, const uint8 register_name, uint8 *dat, uint32 len) +{ + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = register_name; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY)); + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + + while(len--) + { + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = 0; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY)); + *dat++ = ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿڴӴļĴ 16bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ register_name Ĵַ +// ز uint16 +// ʹʾ spi_read_16bit_register(SPI_1,0x1011); +//------------------------------------------------------------------------------------------------------------------- +uint16 spi_read_16bit_register (spi_index_enum spi_n, const uint16 register_name) +{ + + uint16 dat = 0; + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)((register_name & 0xFF00)>>8); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)(register_name & 0x00FF); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = 0; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + //while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_RXNE) == RESET); + dat = ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = 0; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + //while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_RXNE) == RESET); + dat = ((dat << 8)| ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR); + + return dat; +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿڴӴļĴ 16bit +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ register_name Ĵַ +// ˵ *data ݴŻ +// ˵ len ͻ +// ز void +// ʹʾ spi_read_16bit_registers(SPI_1,0x1101,data,32); +//------------------------------------------------------------------------------------------------------------------- +void spi_read_16bit_registers (spi_index_enum spi_n, const uint16 register_name, uint16 *dat, uint32 len) +{ + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)((register_name & 0xFF00)>>8); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (uint8)(register_name & 0x00FF); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + + while(len--) + { + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = 0; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + //while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_RXNE) == RESET); + *dat = ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = 0; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + //while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_RXNE) == RESET); + *dat = ((*dat << 8)| ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR); + dat++; + } + +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI 8bit ݴ ͬʱе +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ write_buffer ͵ݻַ +// ˵ read_buffer ʱյݵĴ洢ַ(Ҫ NULL) +// ˵ len +// ز void +// ʹʾ spi_transfer_8bit(SPI_1,buf,buf,1); +//------------------------------------------------------------------------------------------------------------------- +void spi_transfer_8bit (spi_index_enum spi_n,const uint8 *write_buffer, uint8 *read_buffer, uint32 len) +{ + while(len--) + { + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = *(write_buffer++); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + if(read_buffer != NULL) + { + //while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_RXNE) == RESET); + *read_buffer++ = ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + } + } +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI 16bit ݴ ͬʱе +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ write_buffer ͵ݻַ +// ˵ read_buffer ʱյݵĴ洢ַ(Ҫ NULL) +// ˵ len +// ز void +// ʹʾ spi_transfer_16bit(SPI_1,buf,buf,1); +//------------------------------------------------------------------------------------------------------------------- +void spi_transfer_16bit (spi_index_enum spi_n, const uint16 *write_buffer, uint16 *read_buffer, uint32 len) +{ + while(len--) + { + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (*write_buffer&0xFF00)>>8; + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + if(read_buffer != NULL) + { + //while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_RXNE) == RESET); + *read_buffer++ = ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + } + + ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR = (*write_buffer&0x00FF); + while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_BSY) != RESET); + if(read_buffer != NULL) + { + //while((((SPI_TypeDef *)(spi_index[spi_n]))->STATR & SPI_I2S_FLAG_RXNE) == RESET); + *read_buffer = ((SPI_TypeDef *)(spi_index[spi_n]))->DATAR; + } + write_buffer++; + read_buffer++; + } +} + +//------------------------------------------------------------------------------------------------------------------- +// SPI ӿڳʼ +// ˵ spi_n SPI ģ zf_driver_spi.h spi_index_enum ö嶨 +// ˵ mode SPI ģʽ zf_driver_spi.h spi_mode_enum ö嶨 +// ˵ baud SPI IJ ϵͳʱӵһ ʻᱻ +// ˵ sck_pin ѡ SCK zf_driver_spi.h spi_pin_enum ö嶨 +// ˵ mosi_pin ѡ MOSI zf_driver_spi.h spi_pin_enum ö嶨 +// ˵ miso_pin ѡ MISO zf_driver_spi.h spi_pin_enum ö嶨 +// ˵ cs_pin ѡ CS zf_driver_gpio.h gpio_pin_enum ö嶨 +// ز void +// ʹʾ spi_init(SPI_1, 0, 1*1000*1000, SPI1_SCK_A5, SPI1_MOSI_A7, SPI1_MISO_A6, A4); //ӲSPIʼ ģʽ0 Ϊ1Mhz +//------------------------------------------------------------------------------------------------------------------- +void spi_init(spi_index_enum spi_n, spi_mode_enum mode, uint32 baud, spi_pin_enum sck_pin, spi_pin_enum mosi_pin, spi_pin_enum miso_pin, gpio_pin_enum cs_pin) +{ + SPI_I2S_DeInit((SPI_TypeDef *)(spi_index[spi_n])); + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); // ʹ + + if(sck_pin == SPI1_MAP1_SCK_B3 && mosi_pin == SPI1_MAP1_MOSI_B5) + { + GPIO_PinRemapConfig(GPIO_Remap_SPI1, ENABLE); + } + else if(sck_pin == SPI3_MAP1_SCK_C10 && mosi_pin == SPI3_MAP1_MOSI_C12) + { + GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE); + } + + if(SPI_1 == spi_n) RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); // SPI1ʱʹ + else if(SPI_2 == spi_n) RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); // SPI2ʱʹ + else if(SPI_3 == spi_n) RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); // SPI3ʱʹ + + gpio_init(sck_pin & 0xFF, GPO, 1, SPEED_50MHZ|GPO_AF_PUSH_PULL); + gpio_init(mosi_pin & 0xFF, GPO, 1, SPEED_50MHZ|GPO_AF_PUSH_PULL); + if(miso_pin != SPI_MISO_NULL) + { + gpio_init(miso_pin & 0xFF, GPI, 1, SPEED_50MHZ|GPI_PULL_UP); + } + if(cs_pin != PIN_NULL) + { + gpio_init(cs_pin & 0xFF, GPO, 0, SPEED_50MHZ|GPO_PUSH_PULL); + } + + SPI_InitTypeDef SPI_InitStructure = {0}; + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; // SPIΪ˫˫ȫ˫ + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; // SPIģʽ:ΪSPI + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; // SPIݴС:SPIͽ8λ֡ṹ + + switch(mode) + { + case SPI_MODE0: + { + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; // ͬʱӵĿ״̬Ϊ͵ƽ + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; // ͬʱӵĵһأ½ݱ + }break; + case SPI_MODE1: + { + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; // ͬʱӵĿ״̬Ϊ͵ƽ + SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; // ͬʱӵĵڶأ½ݱ + }break; + case SPI_MODE2: + { + SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; // ͬʱӵĿ״̬Ϊߵƽ + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; // ͬʱӵĵһأ½ݱ + }break; + case SPI_MODE3: + { + SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; // ͬʱӵĿ״̬Ϊߵƽ + SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; // ͬʱӵĵڶأ½ݱ + }break; + } + + uint16 psc = 0; + psc = system_clock / baud; // Ƶֵ + if((system_clock % baud)== 0) + { + psc = psc - 1; + } + if(psc >= 128) psc = SPI_BaudRatePrescaler_256; // CLK_0.5625M + else if(psc >= 64) psc = SPI_BaudRatePrescaler_128; // CLK_1.125M + else if(psc >= 32) psc = SPI_BaudRatePrescaler_64; // CLK_2.25M + else if(psc >= 16) psc = SPI_BaudRatePrescaler_32; // CLK_4.5M + else if(psc >= 8) psc = SPI_BaudRatePrescaler_16; // CLK_9M + else if(psc >= 4) psc = SPI_BaudRatePrescaler_8; // CLK_18M + else if(psc >= 2) psc = SPI_BaudRatePrescaler_4; // CLK_36M + else if(psc >= 1) psc = SPI_BaudRatePrescaler_2; // CLK_72M + else zf_assert(0); + + SPI_InitStructure.SPI_BaudRatePrescaler = psc; // 岨ԤƵֵ + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; // ģʽʹNSS + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; // ָݴMSBλLSBλʼ:ݴMSBλʼ + SPI_InitStructure.SPI_CRCPolynomial = 7; // CRCֵĶʽ + SPI_Init((SPI_TypeDef *)(spi_index[spi_n]), &SPI_InitStructure); // SPI_InitStructָIJʼSPIxĴ + + SPI_Cmd(((SPI_TypeDef *)(spi_index[spi_n])), ENABLE); // ʹSPI +} diff --git a/libraries/zf_driver/zf_driver_spi.h b/libraries/zf_driver/zf_driver_spi.h new file mode 100644 index 0000000..57d52f0 --- /dev/null +++ b/libraries/zf_driver/zf_driver_spi.h @@ -0,0 +1,145 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_spi +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_spi_h +#define _zf_driver_spi_h + +#include "ch32v30x_spi.h" +#include "ch32v30x_rcc.h" +#include "ch32v30x_gpio.h" + +#include "zf_common_debug.h" +#include "zf_common_clock.h" + +#include "zf_driver_gpio.h" + +#define SPI_SPEED_PRIORITY // SPI ͨٶ + +// öٶ岻û޸ +typedef enum // öٴں +{ + SPI_1 = 0x00, + SPI_2 = 0x01, + SPI_3 = 0x02 +}spi_index_enum; + +// öٶ岻û޸ +typedef enum // öٴں +{ + //----------SPI1---------- + // ΪSPI1һӳţӳŻá + // 磺SPI1_MAP0_MAP_SCK_A5SPI1_MAP1_MAP_MISO_B4һʹá + // ֻSPI1_MAP0_MAP_SCK_A5 SPI1_MAP0_MAP_MISO_A6 SPI1_MAP0_MAP_MOSI_A7 ͬӳһʹ + // Ĭӳ + SPI1_MAP0_SCK_A5 = 0x0000 | A5, + SPI1_MAP0_MISO_A6 = 0x0000 | A6, + SPI1_MAP0_MOSI_A7 = 0x0000 | A7, + + // ΪSPI1һӳţӳŻá + // ӳ + SPI1_MAP1_SCK_B3 = 0x0100 | B3, + SPI1_MAP1_MISO_B4 = 0x0100 | B4, + SPI1_MAP1_MOSI_B5 = 0x0100 | B5, + + //----------SPI2-- -------- + + // ΪSPI2һӳţӳŻá + // Ĭӳ + SPI2_MAP0_SCK_B13 = 0x1000 | B13, + SPI2_MAP0_MISO_B14 = 0x1000 | B14, + SPI2_MAP0_MOSI_B15 = 0x1000 | B15, + + //----------SPI3-- -------- + + // ΪSPI3һӳţӳŻá + // Ĭӳ + SPI3_MAP0_SCK_B3 = 0x2000 | B3, + SPI3_MAP0_MISO_B4 = 0x2000 | B4, + SPI3_MAP0_MOSI_B5 = 0x2000 | B5, + + // ΪSPI3һӳţӳŻá + // ӳ + SPI3_MAP1_SCK_C10 = 0x2100 | C10, + SPI3_MAP1_MISO_C11 = 0x2100 | C11, + SPI3_MAP1_MOSI_C12 = 0x2100 | C12, + + // ҪMISOžô˶ + SPI_MISO_NULL = 0xFFFE, + + // ҪCSžô˶ + SPI_CS_NULL = 0xFF, +}spi_pin_enum; + + +typedef enum // ö SPI ģʽ öٶ岻û޸ +{ + SPI_MODE0, + SPI_MODE1, + SPI_MODE2, + SPI_MODE3, +}spi_mode_enum; + + + +void spi_write_8bit (spi_index_enum spi_n, const uint8 data); +void spi_write_8bit_array (spi_index_enum spi_n, const uint8 *data, uint32 len); + +void spi_write_16bit (spi_index_enum spi_n, const uint16 data); +void spi_write_16bit_array (spi_index_enum spi_n, const uint16 *data, uint32 len); + +void spi_write_8bit_register (spi_index_enum spi_n, const uint8 register_name, const uint8 data); +void spi_write_8bit_registers (spi_index_enum spi_n, const uint8 register_name, const uint8 *data, uint32 len); + +void spi_write_16bit_register (spi_index_enum spi_n, const uint16 register_name, const uint16 data); +void spi_write_16bit_registers (spi_index_enum spi_n, const uint16 register_name, const uint16 *data, uint32 len); + +uint8 spi_read_8bit (spi_index_enum spi_n); +void spi_read_8bit_array (spi_index_enum spi_n, uint8 *data, uint32 len); + +uint16 spi_read_16bit (spi_index_enum spi_n); +void spi_read_16bit_array (spi_index_enum spi_n, uint16 *data, uint32 len); + +uint8 spi_read_8bit_register (spi_index_enum spi_n, const uint8 register_name); +void spi_read_8bit_registers (spi_index_enum spi_n, const uint8 register_name, uint8 *data, uint32 len); + +uint16 spi_read_16bit_register (spi_index_enum spi_n, const uint16 register_name); +void spi_read_16bit_registers (spi_index_enum spi_n, const uint16 register_name, uint16 *data, uint32 len); + +void spi_transfer_8bit (spi_index_enum spi_n, const uint8 *write_buffer, uint8 *read_buffer, uint32 len); +void spi_transfer_16bit (spi_index_enum spi_n, const uint16 *write_buffer, uint16 *read_buffer, uint32 len); + +void spi_init (spi_index_enum spi_n, spi_mode_enum mode, uint32 baud, spi_pin_enum sck_pin, spi_pin_enum mosi_pin, spi_pin_enum miso_pin, gpio_pin_enum cs_pin); + +#endif diff --git a/libraries/zf_driver/zf_driver_timer.c b/libraries/zf_driver/zf_driver_timer.c new file mode 100644 index 0000000..ba11596 --- /dev/null +++ b/libraries/zf_driver/zf_driver_timer.c @@ -0,0 +1,289 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_timer +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#include "zf_driver_gpio.h" +#include "zf_driver_timer.h" + + +// ֹ޸ģڲʹ,û +static timer_function_enum timer_function_state[10] = +{ + TIMER_FUNCTION_INIT, TIMER_FUNCTION_INIT, + TIMER_FUNCTION_INIT, TIMER_FUNCTION_INIT, + TIMER_FUNCTION_INIT, TIMER_FUNCTION_INIT, + TIMER_FUNCTION_INIT, TIMER_FUNCTION_INIT, + TIMER_FUNCTION_INIT, TIMER_FUNCTION_INIT +}; + +// ֹ޸ģڲʹ,û +static timer_mode_enum timer_mode_state[10] = +{ + TIMER_SYSTEM_CLOCK, TIMER_SYSTEM_CLOCK, + TIMER_SYSTEM_CLOCK, TIMER_SYSTEM_CLOCK, + TIMER_SYSTEM_CLOCK, TIMER_SYSTEM_CLOCK, + TIMER_SYSTEM_CLOCK, TIMER_SYSTEM_CLOCK, + TIMER_SYSTEM_CLOCK, TIMER_SYSTEM_CLOCK +}; + +//------------------------------------------------------------------------------------------------------------------- +// TIMER ȷϹ״̬ ڲ +// ˵ index TIMER ģ +// ˵ mode ҪȷĹģ +// ز uint8 1-ʹ 0-ʹ +// ʹʾ zf_assert(timer_funciton_check(TIM_1, TIMER_FUNCTION_PWM); +//------------------------------------------------------------------------------------------------------------------- +uint8 timer_funciton_check (timer_index_enum index, timer_function_enum mode) +{ + uint8 return_state = 1; + if(TIMER_FUNCTION_INIT == timer_function_state[index]) + { + timer_function_state[index] = mode; + } + else if(timer_function_state[index] == mode) + { + return_state = 1; + } + else + { + return_state = 0; + } + return return_state; +} + +//------------------------------------------------------------------------------------------------------------------- +// ʱʱ߳ʼ +// ˵ timer_ch ʱͨ +// ز void +// עϢ ڲʹãû +//------------------------------------------------------------------------------------------------------------------- +void timer_clock_enable(timer_index_enum index) +{ + if(TIM_1 == index) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);//ʹܶʱ1ʱ + else if(TIM_2 == index) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);//ʹܶʱ2ʱ + else if(TIM_3 == index) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);//ʹܶʱ3ʱ + else if(TIM_4 == index) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);//ʹܶʱ4ʱ + else if(TIM_5 == index) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE);//ʹܶʱ5ʱ + else if(TIM_6 == index) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);//ʹܶʱ6ʱ + else if(TIM_7 == index) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM7, ENABLE);//ʹܶʱ7ʱ + else if(TIM_8 == index) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM8, ENABLE);//ʹܶʱ8ʱ + else if(TIM_9 == index) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9, ENABLE);//ʹܶʱ9ʱ + else if(TIM_10== index) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM10,ENABLE);//ʹܶʱ10ʱ +} + + + +//------------------------------------------------------------------------------------------------------------------- +// ʱʼ +// ˵ timer_ch ѡģͨ (ѡΧ TIMERN_enumöֵȷ) +// ز void +// ʹʾ timer_start(TIM_1, TIMER_US); //ʱ1 ʼÿһusһ +//------------------------------------------------------------------------------------------------------------------- +void timer_start(timer_index_enum index) +{ + TIM_TypeDef *tim_index = TIM1; + switch(index) + { + case TIM_1: tim_index = ((TIM_TypeDef *)TIM1_BASE); break; + case TIM_2: tim_index = ((TIM_TypeDef *)TIM2_BASE); break; + case TIM_3: tim_index = ((TIM_TypeDef *)TIM3_BASE); break; + case TIM_4: tim_index = ((TIM_TypeDef *)TIM4_BASE); break; + case TIM_5: tim_index = ((TIM_TypeDef *)TIM5_BASE); break; + case TIM_6: tim_index = ((TIM_TypeDef *)TIM6_BASE); break; + case TIM_7: tim_index = ((TIM_TypeDef *)TIM7_BASE); break; + case TIM_8: tim_index = ((TIM_TypeDef *)TIM8_BASE); break; + case TIM_9: tim_index = ((TIM_TypeDef *)TIM9_BASE); break; + case TIM_10: tim_index = ((TIM_TypeDef *)TIM10_BASE); break; + } + TIM_Cmd(tim_index, ENABLE); // ʹTIMx +} + + +//------------------------------------------------------------------------------------------------------------------- +// رռʱ +// ˵ timer_ch ѡģͨ (ѡΧ TIMERN_enumöֵȷ) +// ز void +// עϢ رնʱ־λ +//------------------------------------------------------------------------------------------------------------------- +void timer_stop(timer_index_enum index) +{ + TIM_TypeDef *tim_index = TIM1; + + switch(index) + { + case TIM_1: tim_index = ((TIM_TypeDef *)TIM1_BASE); break; + case TIM_2: tim_index = ((TIM_TypeDef *)TIM2_BASE); break; + case TIM_3: tim_index = ((TIM_TypeDef *)TIM3_BASE); break; + case TIM_4: tim_index = ((TIM_TypeDef *)TIM4_BASE); break; + case TIM_5: tim_index = ((TIM_TypeDef *)TIM5_BASE); break; + case TIM_6: tim_index = ((TIM_TypeDef *)TIM6_BASE); break; + case TIM_7: tim_index = ((TIM_TypeDef *)TIM7_BASE); break; + case TIM_8: tim_index = ((TIM_TypeDef *)TIM8_BASE); break; + case TIM_9: tim_index = ((TIM_TypeDef *)TIM9_BASE); break; + case TIM_10: tim_index = ((TIM_TypeDef *)TIM10_BASE); break; + } + + TIM_Cmd(tim_index, DISABLE); //ʧTIM +} + + +//------------------------------------------------------------------------------------------------------------------- +// ȡʱֵ +// ˵ timer_ch ѡģͨ (ѡΧ TIMERN_enumöֵȷ) +// ز uint32 ֵ +// ʹʾ timer_get(TIM_1) //ȡʱ1ļʱʱ +//------------------------------------------------------------------------------------------------------------------- +uint16 timer_get(timer_index_enum index) +{ + TIM_TypeDef *tim_index = TIM1; + uint16 return_value = 0; + + switch(index) + { + case TIM_1: tim_index = ((TIM_TypeDef *)TIM1_BASE); break; + case TIM_2: tim_index = ((TIM_TypeDef *)TIM2_BASE); break; + case TIM_3: tim_index = ((TIM_TypeDef *)TIM3_BASE); break; + case TIM_4: tim_index = ((TIM_TypeDef *)TIM4_BASE); break; + case TIM_5: tim_index = ((TIM_TypeDef *)TIM5_BASE); break; + case TIM_6: tim_index = ((TIM_TypeDef *)TIM6_BASE); break; + case TIM_7: tim_index = ((TIM_TypeDef *)TIM7_BASE); break; + case TIM_8: tim_index = ((TIM_TypeDef *)TIM8_BASE); break; + case TIM_9: tim_index = ((TIM_TypeDef *)TIM9_BASE); break; + case TIM_10: tim_index = ((TIM_TypeDef *)TIM10_BASE); break; + } + + + if(timer_mode_state[index] == TIMER_MS) + { + return_value = tim_index->CNT/3; + } + else + { + return_value = tim_index->CNT; + } + return return_value; +} + + + +//------------------------------------------------------------------------------------------------------------------- +// TIMER ʱ +// ˵ index TIMER ģ +// ز void +// ʹʾ timer_clear(TIM_1); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void timer_clear (timer_index_enum index) +{ + TIM_TypeDef *tim_index = TIM1; + + switch(index) + { + case TIM_1: tim_index = ((TIM_TypeDef *)TIM1_BASE); break; + case TIM_2: tim_index = ((TIM_TypeDef *)TIM2_BASE); break; + case TIM_3: tim_index = ((TIM_TypeDef *)TIM3_BASE); break; + case TIM_4: tim_index = ((TIM_TypeDef *)TIM4_BASE); break; + case TIM_5: tim_index = ((TIM_TypeDef *)TIM5_BASE); break; + case TIM_6: tim_index = ((TIM_TypeDef *)TIM6_BASE); break; + case TIM_7: tim_index = ((TIM_TypeDef *)TIM7_BASE); break; + case TIM_8: tim_index = ((TIM_TypeDef *)TIM8_BASE); break; + case TIM_9: tim_index = ((TIM_TypeDef *)TIM9_BASE); break; + case TIM_10: tim_index = ((TIM_TypeDef *)TIM10_BASE); break; + } + tim_index->CNT = 0; +} + +//------------------------------------------------------------------------------------------------------------------- +// TIMER ʱʼ +// ˵ index TIMER ģ +// ˵ mode ʱʽ +// ز void +// ʹʾ timer_init(TIM_1, TIMER_US); +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void timer_init(timer_index_enum index, timer_mode_enum mode) +{ + + // ˶Ϣ ʾλ + // ȥ鿴ʲôط Ĵ + // ǼǷظʹöʱ + // ʼ TIM1_PWM Ȼֳʼ TIM_1 ÷Dz + zf_assert(timer_funciton_check(index, TIMER_FUNCTION_TIMER)); + timer_function_state[index] = TIMER_FUNCTION_TIMER; + + TIM_TypeDef *tim_index = TIM1; + switch(index) + { + case TIM_1: tim_index = ((TIM_TypeDef *)TIM1_BASE); break; + case TIM_2: tim_index = ((TIM_TypeDef *)TIM2_BASE); break; + case TIM_3: tim_index = ((TIM_TypeDef *)TIM3_BASE); break; + case TIM_4: tim_index = ((TIM_TypeDef *)TIM4_BASE); break; + case TIM_5: tim_index = ((TIM_TypeDef *)TIM5_BASE); break; + case TIM_6: tim_index = ((TIM_TypeDef *)TIM6_BASE); break; + case TIM_7: tim_index = ((TIM_TypeDef *)TIM7_BASE); break; + case TIM_8: tim_index = ((TIM_TypeDef *)TIM8_BASE); break; + case TIM_9: tim_index = ((TIM_TypeDef *)TIM9_BASE); break; + case TIM_10: tim_index = ((TIM_TypeDef *)TIM10_BASE); break; + } + + + + timer_clock_enable(index); // ʱ + + timer_mode_state[index] = mode; + + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure = {0}; + if(mode == TIMER_US) + { + TIM_TimeBaseStructure.TIM_Period = 0xFFFF; // װԶװֵ + TIM_TimeBaseStructure.TIM_Prescaler = (system_clock/1000000)-1; // װԤƵ + } + else if(mode == TIMER_MS) + { + TIM_TimeBaseStructure.TIM_Period = 0xFFFF; // װԶװֵ + TIM_TimeBaseStructure.TIM_Prescaler = (system_clock/1000)/3-1; // װԤƵ + } + else + { + TIM_TimeBaseStructure.TIM_Period = 0xFFFF; // װԶװֵ + TIM_TimeBaseStructure.TIM_Prescaler = 0; // װԤƵ + } + TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1; // ʱӷָ:TDTS = Tck_tim + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; // TIMϼģʽ + TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; // ظΪ0 + TIM_TimeBaseInit(tim_index, &TIM_TimeBaseStructure); // ָIJʼTIMxʱλ + + TIM_Cmd(tim_index, ENABLE); // ʹTIMx +} + diff --git a/libraries/zf_driver/zf_driver_timer.h b/libraries/zf_driver/zf_driver_timer.h new file mode 100644 index 0000000..093682e --- /dev/null +++ b/libraries/zf_driver/zf_driver_timer.h @@ -0,0 +1,93 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_timer +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_timer_h +#define _zf_driver_timer_h + +#include "ch32v30x_rcc.h" +#include "ch32v30x_gpio.h" +#include "ch32v30x_tim.h" + +#include "zf_common_debug.h" +#include "zf_common_clock.h" + +//öٶ岻û޸ +typedef enum +{ + TIM_1, + TIM_2, + TIM_3, + TIM_4, + TIM_5, + TIM_6, + TIM_7, + TIM_8, + TIM_9, + TIM_10, +}timer_index_enum; + +typedef enum +{ + TIMER_SYSTEM_CLOCK, // ϵͳƵʼʱ 0xFFFF + TIMER_US, // ΢ʱ 0xFFFF + TIMER_MS, // ʱ 0xFFFF/2 +}timer_mode_enum; + +typedef enum +{ + TIMER_FUNCTION_INIT = 0, // δʼ + TIMER_FUNCTION_TIMER, // TIMER ʱ + TIMER_FUNCTION_PIT, // PIT + TIMER_FUNCTION_PWM, // PWM + TIMER_FUNCTION_ENCODER, // ENCODER + TIMER_FUNCTION_CAMERA, // CAMERA +}timer_function_enum; + + +uint8 timer_funciton_check (timer_index_enum index, timer_function_enum mode); +void timer_clock_enable (timer_index_enum index); + +void timer_start (timer_index_enum index); +void timer_stop (timer_index_enum index); +uint16 timer_get (timer_index_enum index); +void timer_clear (timer_index_enum index); + +void timer_init (timer_index_enum index, timer_mode_enum mode); + + + + + +#endif diff --git a/libraries/zf_driver/zf_driver_uart.c b/libraries/zf_driver/zf_driver_uart.c new file mode 100644 index 0000000..7d536bc --- /dev/null +++ b/libraries/zf_driver/zf_driver_uart.c @@ -0,0 +1,292 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_uart +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +#include "zf_driver_gpio.h" +#include "zf_driver_uart.h" + +// ֹ޸ģڲʹû +const uint8 uart_irq[] = {USART1_IRQn, USART2_IRQn, USART3_IRQn, UART4_IRQn, UART5_IRQn, UART6_IRQn, UART7_IRQn, UART8_IRQn}; +const uint32 uart_index[] = {USART1_BASE, USART2_BASE, USART3_BASE, UART4_BASE, UART5_BASE, UART6_BASE, UART7_BASE, UART8_BASE}; + +//------------------------------------------------------------------------------------------------------------------- +// ڷһֽ +// ˵ uartn ͨ +// ˵ dat +// ز void +// ʹʾ uart_write_byte(UART_1, 0x43); //10x43 +//------------------------------------------------------------------------------------------------------------------- +void uart_write_byte(uart_index_enum uartn, const uint8 dat) +{ + while((((USART_TypeDef*)uart_index[uartn])->STATR & USART_FLAG_TXE)==0); + ((USART_TypeDef*)uart_index[uartn])->DATAR = dat; +} + +//------------------------------------------------------------------------------------------------------------------- +// ڷ +// ˵ uartn ͨ +// ˵ buff Ҫ͵ַ +// ˵ len ݳ +// ز void +// ʹʾ uart_write_buffer(UART_1, buff, 10); //110buff顣 +//------------------------------------------------------------------------------------------------------------------- +void uart_write_buffer(uart_index_enum uartn, const uint8 *buff, uint32 len) +{ + zf_assert(buff != NULL); + while(len--) + uart_write_byte(uartn, *buff++); +} + + +//------------------------------------------------------------------------------------------------------------------- +// ڷַ +// ˵ uartn ͨ +// ˵ str ַ׵ַ +// ز void +// ʹʾ uart_putstr(UART_1, (uint8 *)"12345") //112345ַ +//------------------------------------------------------------------------------------------------------------------- +void uart_write_string(uart_index_enum uartn, const char *str) +{ + zf_assert(str != NULL); + while(*str) // һֱѭβ + { + uart_write_byte(uartn, *str++); + } +} + + + +//------------------------------------------------------------------------------------------------------------------- +// 򿪴ڽж +// ˵ uartn ͨ +// ˵ status ʹܻʧ +// ز void +// ʹʾ uart_rx_irq(UART_1, ENABLE); //򿪴1ж +//------------------------------------------------------------------------------------------------------------------- +void uart_rx_interrupt(uart_index_enum uartn, uint8 status) +{ + USART_ITConfig(((USART_TypeDef*)uart_index[uartn]), USART_IT_RXNE, status); + + // жȼ + interrupt_set_priority((uint32)((IRQn_Type)uart_irq[uartn]), 0); + + if(status) interrupt_enable((IRQn_Type)uart_irq[uartn]); + else interrupt_disable((IRQn_Type)uart_irq[uartn]); +} + +//------------------------------------------------------------------------------------------------------------------- +// 򿪴ڷж +// ˵ uartn ͨ +// ˵ status ʹܻʧ +// ز void +// ʹʾ uart_tx_irq(UART_1, DISABLE); //رմ1 ж +//------------------------------------------------------------------------------------------------------------------- +void uart_tx_interrupt(uart_index_enum uartn, uint8 status) +{ + USART_ITConfig(((USART_TypeDef*)uart_index[uartn]), USART_IT_TXE, status); + + // жȼ + interrupt_set_priority((uint32)((IRQn_Type)uart_irq[uartn]), 0); + + if(status) interrupt_enable((IRQn_Type)uart_irq[uartn]); + else interrupt_disable((IRQn_Type)uart_irq[uartn]); +} + + +//------------------------------------------------------------------------------------------------------------------- +// ȡڽյݣwhlieȴ +// ˵ uartn ģ(UART_1 - UART_8) +// ˵ *dat ݵĵַ +// ز void +// ʹʾ uint8 dat; uart_read_byte(USART_1,&dat); // մ1 dat +//------------------------------------------------------------------------------------------------------------------- +uint8 uart_read_byte(uart_index_enum uartn) +{ + while((((USART_TypeDef*)uart_index[uartn])->STATR & USART_FLAG_RXNE) == 0); + return (((USART_TypeDef*)uart_index[uartn])->DATAR & (uint16)0xFF); +} + +//------------------------------------------------------------------------------------------------------------------- +// ȡڽյݣѯգ +// ˵ uartn ģ(UART_1 - UART_8) +// ˵ *dat ݵĵַ +// ز uint8 1ճɹ 0δյ +// ʹʾ uint8 dat; uart_query_byte(USART_1,&dat); // մ1 dat +//------------------------------------------------------------------------------------------------------------------- +uint8 uart_query_byte(uart_index_enum uartn, uint8 *dat) +{ + if((((USART_TypeDef*)uart_index[uartn])->STATR & USART_FLAG_RXNE) != 0) + { + *dat = (((USART_TypeDef*)uart_index[uartn])->DATAR & 0xFF); + return 1; + } + return 0; +} + +//------------------------------------------------------------------------------------------------------------------- +// ڳʼ +// ˵ uartn ͨ +// ˵ baud +// ˵ tx_pin ڷź +// ˵ rx_pin ڽź +// ز void +// ʹʾ uart_init(UART_1, 115200, UART1_TX_A9, UART1_RX_A10); //1ʼź,TXΪA9,RXΪA10 +//------------------------------------------------------------------------------------------------------------------- +void uart_init(uart_index_enum uart_n, uint32 baud, uart_pin_enum tx_pin, uart_pin_enum rx_pin) +{ + // ˶Ϣ ʾλ + // ȥ鿴ʲôط Ĵ + // RXTXҪͬһӳţͬͻ + zf_assert((tx_pin & (uart_n << 12)) == (rx_pin & (uart_n << 12))); // tx_pin rx_pin uart_n ƥ + zf_assert((tx_pin >> 8) == (rx_pin >> 8)); // tx_pin rx_pin 鴫 + + gpio_init(tx_pin & 0xFF, GPO, 0, GPO_AF_PUSH_PULL); + gpio_init(rx_pin & 0xFF, GPI, 0, GPI_PULL_UP); + + // AFIO߿ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); + + switch(tx_pin & 0xFFFF) + { + case UART1_MAP1_TX_B6: + AFIO->PCFR2 &= ~(0x01<<26); + AFIO->PCFR1 &= ~(0x01<<2); + AFIO->PCFR1 |= (0x01<<2); + break; + case UART1_MAP2_TX_B15: + AFIO->PCFR2 &= ~(0x01<<26); + AFIO->PCFR2 |= (0x01<<26); + AFIO->PCFR1 &= ~(0x01<<2); + break; + case UART1_MAP3_TX_A6: + AFIO->PCFR2 &= ~(0x01<<26); + AFIO->PCFR2 |= (0x01<<26); + AFIO->PCFR1 &= ~(0x01<<2); + AFIO->PCFR1 |= (0x01<<2); + break; + + case UART2_MAP1_TX_D5: + AFIO->PCFR1 &= ~(0x01<<3); + AFIO->PCFR1 |= (0x01<<3); + break; + + case UART3_MAP1_TX_C10: + AFIO->PCFR1 &= ~(0x03<<4); + AFIO->PCFR1 |= (0x01<<4); + break; + + case UART3_MAP2_TX_D8: + AFIO->PCFR1 &= ~(0x03<<4); + AFIO->PCFR1 |= (0x03<<4); + break; + + case UART4_MAP1_TX_B0: + AFIO->PCFR2 &= ~(0x03<<16); + AFIO->PCFR2 |= (((tx_pin >> 8) & 0x03 ) << 16); + break; + + case UART4_MAP3_TX_E0: + AFIO->PCFR2 &= ~(0x03<<16); + AFIO->PCFR2 |= (((tx_pin >> 8) & 0x03 ) << 16); + break; + + case UART5_MAP1_TX_B4: + AFIO->PCFR2 &= ~(0x03<<18); + AFIO->PCFR2 |= (((tx_pin >> 8) & 0x03 ) << 18); + break; + + case UART5_MAP3_TX_E8: + AFIO->PCFR2 &= ~(0x03<<18); + AFIO->PCFR2 |= (((tx_pin >> 8) & 0x03 ) << 18); + break; + + case UART6_MAP1_TX_B8: + AFIO->PCFR2 &= ~(0x03<<20); + AFIO->PCFR2 |= (((tx_pin >> 8) & 0x03 ) << 20); + break; + + case UART6_MAP3_TX_E10: + AFIO->PCFR2 &= ~(0x03<<20); + AFIO->PCFR2 |= (((tx_pin >> 8) & 0x03 ) << 20); + break; + + case UART7_MAP1_TX_A6: + AFIO->PCFR2 &= ~(0x03<<22); + AFIO->PCFR2 |= (((tx_pin >> 8) & 0x03 ) << 22); + break; + + case UART7_MAP3_TX_E12: + AFIO->PCFR2 &= ~(0x03<<22); + AFIO->PCFR2 |= (((tx_pin >> 8) & 0x03 ) << 22); + break; + + case UART8_MAP1_TX_A14: + AFIO->PCFR2 &= ~(0x03<<24); + AFIO->PCFR2 |= (((tx_pin >> 8) & 0x03 ) << 24); + break; + + case UART8_MAP3_TX_E14: + AFIO->PCFR2 &= ~(0x03<<24); + AFIO->PCFR2 |= (((tx_pin >> 8) & 0x03 ) << 24); + break; + } + + + // ʹ + if(UART_1 == uart_n) RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); + else if(UART_2 == uart_n) RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); + else if(UART_3 == uart_n) RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); + else if(UART_4 == uart_n) RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE); + else if(UART_5 == uart_n) RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE); + else if(UART_6 == uart_n) RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART6, ENABLE); + else if(UART_7 == uart_n) RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART7, ENABLE); + else if(UART_8 == uart_n) RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART8, ENABLE); + + // ڲ + USART_InitTypeDef USART_InitStructure = {0}; + USART_InitStructure.USART_BaudRate = baud; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; + + // ʹܴ + USART_Init((USART_TypeDef*)uart_index[uart_n], &USART_InitStructure); + USART_Cmd((USART_TypeDef*)uart_index[uart_n], ENABLE); + +} + + + + diff --git a/libraries/zf_driver/zf_driver_uart.h b/libraries/zf_driver/zf_driver_uart.h new file mode 100644 index 0000000..13c9fca --- /dev/null +++ b/libraries/zf_driver/zf_driver_uart.h @@ -0,0 +1,231 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_uart +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_uart_h +#define _zf_driver_uart_h + +#include "ch32v30x.h" +#include "ch32v30x_gpio.h" +#include "ch32v30x_rcc.h" +#include "ch32v30x_usart.h" + +#include "zf_common_interrupt.h" +#include "zf_common_debug.h" +#include "zf_driver_gpio.h" + +// öٶ岻û޸ +// ʼʱ򣬱ʹͬһ磬UART1_MAP_TX_A9UART1_MAP_RX_A10һ +// +typedef enum // öٶ岻û޸ +{ + // MAP0 Ĭӳ + // MAP1 ӳ + // MAP2 ӳ + // MAP3 ȫӳ + + //----------UART1-----------// + // Ϊ1һӳţӳŻá + // 磺UART1_MAP0_TX_A9UART1_MAP1_TX_B6һʹá + + // Ĭӳ + UART1_MAP0_TX_A9 = 0x0000 | A9 , + UART1_MAP0_RX_A10 = 0x0000 | A10, + + // Ϊ1һӳţӳŻá + // ӳ + UART1_MAP1_TX_B6 = 0x0100 | B6 , + UART1_MAP1_RX_B7 = 0x0100 | B7 , + + // Ϊ1һӳţӳŻá + // ӳ + UART1_MAP2_TX_B15 = 0x0200 | B15, + UART1_MAP2_RX_A8 = 0x0200 | A8 , + + // Ϊ1һӳţӳŻá + // ȫӳ + UART1_MAP3_TX_A6 = 0x0300 | A6 , + UART1_MAP3_RX_A7 = 0x0300 | A7 , + + //----------UART2-----------// + + // Ϊ2һӳţӳŻá + // Ĭӳ + UART2_MAP0_TX_A2 = 0x1000 | A2 , + UART2_MAP0_RX_A3 = 0x1000 | A3 , + + // Ϊ2һӳţӳŻá + // ӳ + UART2_MAP1_TX_D5 = 0x1100 | D5 , + UART2_MAP1_RX_D6 = 0x1100 | D6 , + + //----------UART3--------------// + + // Ϊ3һӳţӳŻá + // Ĭӳ + UART3_MAP0_TX_B10 = 0x2000 | B10, // Ĭ + UART3_MAP0_RX_B11 = 0x2000 | B11, // Ĭ + + // Ϊ3һӳţӳŻá + // ӳ + UART3_MAP1_TX_C10 = 0x2100 | C10, + UART3_MAP1_RX_C11 = 0x2100 | C11, + + // Ϊ3һӳţӳŻá + // ȫӳ + UART3_MAP2_TX_D8 = 0x2300 | D8 , + UART3_MAP2_RX_D9 = 0x2300 | D9 , + + //----------UART4-----------// + + // Ϊ4һӳţӳŻá + // Ĭӳ + UART4_MAP0_TX_C10 = 0x3000 | C10, + UART4_MAP0_RX_C11 = 0x3000 | C11, + + // Ϊ4һӳţӳŻá + // ӳ + UART4_MAP1_TX_B0 = 0x3100 | B0 , + UART4_MAP1_RX_B1 = 0x3100 | B1 , + + // Ϊ4һӳţӳŻá + // ȫӳ + UART4_MAP3_TX_E0 = 0x3300 | E0 , + UART4_MAP3_RX_E1 = 0x3300 | E1 , + + //----------UART5-----------// + + // Ϊ5һӳţӳŻá + // Ĭӳ + UART5_MAP0_TX_C12 = 0x4000 | C12, + UART5_MAP0_RX_D2 = 0x4000 | D2, + + // Ϊ5һӳţӳŻá + // ӳ + UART5_MAP1_TX_B4 = 0x4100 | B4, + UART5_MAP1_RX_B5 = 0x4100 | B5, + + // Ϊ5һӳţӳŻá + // ȫӳ + UART5_MAP3_TX_E8 = 0x4300 | E8, + UART5_MAP3_RX_E9 = 0x4300 | E9, + + //----------UART6-----------// + + // Ϊ6һӳţӳŻá + // Ĭӳ + UART6_MAP0_TX_C0 = 0x5000 | C0 , + UART6_MAP0_RX_C1 = 0x5000 | C1 , + + // Ϊ6һӳţӳŻá + // ӳ + UART6_MAP1_TX_B8 = 0x5100 | B8 , + UART6_MAP1_RX_B9 = 0x5100 | B9 , + + // Ϊ6һӳţӳŻá + // ȫӳ + UART6_MAP3_TX_E10 = 0x5300 | E10, + UART6_MAP3_RX_E11 = 0x5300 | E11, + + //----------UART7-----------// + + // Ϊ7һӳţӳŻá + // Ĭӳ + UART7_MAP0_TX_C2 = 0x6000 | C2 , + UART7_MAP0_RX_C3 = 0x6000 | C3 , + + // Ϊ7һӳţӳŻá + // ӳ + UART7_MAP1_TX_A6 = 0x6100 | A6 , + UART7_MAP1_RX_A7 = 0x6100 | A7 , + + // Ϊ7һӳţӳŻá + // ȫӳ + UART7_MAP3_TX_E12 = 0x6300 | E12, + UART7_MAP3_RX_E13 = 0x6300 | E13, + + //----------UART8-----------// + + // Ϊ8һӳţӳŻá + // Ĭӳ + UART8_MAP0_TX_C4 = 0x7000 | C4 , + UART8_MAP0_RX_C5 = 0x7000 | C5 , + + // Ϊ8һӳţӳŻá + // ӳ + UART8_MAP1_TX_A14 = 0x7100 | A14, + UART8_MAP1_RX_A15 = 0x7100 | A15, + + // Ϊ8һӳţӳŻá + // ȫӳ + UART8_MAP3_TX_E14 = 0x7300 | E14, + UART8_MAP3_RX_E15 = 0x7300 | E15, + +}uart_pin_enum; + + +typedef enum// öٶ岻û޸ +{ + UART_1, + UART_2, + UART_3, + UART_4, + UART_5, + UART_6, + UART_7, + UART_8, +}uart_index_enum; + + + +extern const uint32 uart_index[]; + + + + +void uart_write_byte (uart_index_enum uart_n, const uint8 dat); +void uart_write_buffer (uart_index_enum uart_n, const uint8 *buff, uint32 len); +void uart_write_string (uart_index_enum uart_n, const char *str); + +uint8 uart_read_byte (uart_index_enum uartn); +uint8 uart_query_byte (uart_index_enum uartn, uint8 *dat); + +void uart_tx_interrupt (uart_index_enum uart_n, uint8 status); +void uart_rx_interrupt (uart_index_enum uart_n, uint8 status); + +void uart_init (uart_index_enum uart_n, uint32 baud, uart_pin_enum tx_pin, uart_pin_enum rx_pin); + + + +#endif diff --git a/libraries/zf_driver/zf_driver_usb_cdc.c b/libraries/zf_driver/zf_driver_usb_cdc.c new file mode 100644 index 0000000..d408300 --- /dev/null +++ b/libraries/zf_driver/zf_driver_usb_cdc.c @@ -0,0 +1,118 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_usb_cdc +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ +#include "ch32v30x.h" +#include "zf_driver_delay.h" +#include "zf_driver_usb_cdc.h" + + + +//------------------------------------------------------------------------------------------------------------------- +// USB_CDCһ +// ˵ *p Ҫ͵ָ +// ˵ length Ͷٸ( length ҪС64) +// ز void +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void cdc_send_pack(const uint8 *p, uint32 length) +{ + uint32 i = 0; + + for(i=0; iUEP2_TX_CTRL&USBHD_UEP_T_RES1)); + + // bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) + // 00: DATA0 or DATA1 then expecting ACK (ready) + // 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions + // 10: NAK (busy) + // 11: TALL (error) +} + + +//------------------------------------------------------------------------------------------------------------------- +// ͼݵλ +// ˵ *image ͼ +// ˵ length Ͷٸ +// ز void +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void camera_send_image_usb_cdc(const uint8 *image, uint32 length) +{ + uint8 send_buffer[4] = {0x00,0xff,0x01,0x01}; + cdc_send_pack(send_buffer, 4); + + while(length) + { + if(length >= 63) + { + cdc_send_pack(image, 63); + image += 63; + length -= 63; + } + else + { + cdc_send_pack(image, length); + length = 0; + } + } +} + + +//------------------------------------------------------------------------------------------------------------------- +// USB豸ȫ豸ʼ +// ˵ void +// ز void +// עϢ +//------------------------------------------------------------------------------------------------------------------- +void usb_cdc_init( void ) +{ + // ˵㻺ʼ + pEP0_RAM_Addr = EP0_DatabufHD; + pEP1_RAM_Addr = EP1_DatabufHD; + pEP2_RAM_Addr = EP2_DatabufHD; + // ʹusbʱ + USBOTG_RCC_Init(); + system_delay_ms(100); + // usb豸ʼ + USBDeviceInit(); + EXTEN->EXTEN_CTR |= EXTEN_USBD_PU_EN; + // ʹusbж + NVIC_EnableIRQ(OTG_FS_IRQn); +} diff --git a/libraries/zf_driver/zf_driver_usb_cdc.h b/libraries/zf_driver/zf_driver_usb_cdc.h new file mode 100644 index 0000000..d390580 --- /dev/null +++ b/libraries/zf_driver/zf_driver_usb_cdc.h @@ -0,0 +1,45 @@ +/********************************************************************************************************************* +* CH32V307VCT6 Opensourec Library CH32V307VCT6 Դ⣩һڹٷ SDK ӿڵĵԴ +* Copyright (c) 2022 SEEKFREE ɿƼ +* +* ļCH32V307VCT6 Դһ +* +* CH32V307VCT6 Դ +* Ըᷢ GPLGNU General Public License GNUͨù֤ +* GPL ĵ3棨 GPL3.0ѡģκκİ汾·/޸ +* +* Դķϣܷãδκεı֤ +* ûԻʺض;ı֤ +* ϸμ GPL +* +* ӦյԴͬʱյһ GPL ĸ +* ûУ +* +* ע +* Դʹ GPL3.0 Դ֤Э Ϊİ汾 +* Ӣİ libraries/doc ļµ GPL3_permission_statement.txt ļ +* ֤ libraries ļ ļµ LICENSE ļ +* ӭλʹò ޸ʱ뱣ɿƼİȨ +* +* ļ zf_driver_usb_cdc +* ˾ ɶɿƼ޹˾ +* 汾Ϣ 鿴 libraries/doc ļ version ļ 汾˵ +* MounRiver Studio V1.8.1 +* ƽ̨ CH32V307VCT6 +* https://seekfree.taobao.com/ +* +* ޸ļ¼ +* ע +* 2022-09-15 W first version +********************************************************************************************************************/ + +#ifndef _zf_driver_usb_cdc_h +#define _zf_driver_usb_cdc_h + +#include "ch32v30x_usbotg_device.h" + +void cdc_send_pack(const uint8 *p, uint32 length); +void camera_send_image_usb_cdc(const uint8 *image, uint32 length); +void usb_cdc_init( void ); + +#endif diff --git a/set_eide_env.py b/set_eide_env.py new file mode 100644 index 0000000..c5a7d25 --- /dev/null +++ b/set_eide_env.py @@ -0,0 +1,55 @@ +import fileinput +import os + +tempelate_file_path = '.\\template.code-workspace_t' +target_file_path = '.\\violet_firmware_zf.code-workspace' + +print("*************************************************************************************") + +while True: + print("*************************************************************************************") + mrs_riscv_gcc_path_str = input("请输入 MRS 工具链下 RISCV-GCC 路径 (例如 D:\\xpack-riscv-none-embed-gcc-8.3.0-2.3):\n") + print("获取到输入：%s" %mrs_riscv_gcc_path_str) + if not os.path.exists(mrs_riscv_gcc_path_str): + print("GCC 路径错误，请输入有效路径") + else: + print("输入正确") + break + + +while True: + print("*************************************************************************************") + mrs_openocd_path_str = input("请输入 MRS 工具链下 OpenOCD 路径 (例如 D:\\OpenOCD\\bin\\openocd.exe):\n") + print("获取到输入：%s" %mrs_openocd_path_str) + if not os.path.exists(mrs_openocd_path_str): + print("OpenOCD 路径错误，请输入有效路径") + else: + print("输入正确") + break + +mrs_riscv_gcc_path_str = mrs_riscv_gcc_path_str.replace("\\", "/") +mrs_openocd_path_str = mrs_openocd_path_str.replace("\\", "/") + +# 检查模板文件是否存在 +if not os.path.isfile(tempelate_file_path): + print(f"模板文件 {tempelate_file_path} 不存在") + exit(1) + +# 复制模板文件到工作区文件 +if os.path.exists(target_file_path): + print(f"工作区文件 {target_file_path} 已存在，将会被覆盖") + +if_continue = input("输入 y 以继续:\n") +if if_continue != 'y': + print("程序退出") + exit(1) + +with open(tempelate_file_path, "r") as f: + lines = f.readlines() + +with open(target_file_path, "w") as f: + for line in lines: + # 替换字符串 YOUR_WCH_OPENOCD_PATH 和 YOUR_WCH_GCC_PATH + f.write(line.replace("YOUR_WCH_OPENOCD_PATH", mrs_openocd_path_str).replace("YOUR_WCH_RISCV_GCC_PATH", mrs_riscv_gcc_path_str)) + +print("处理完成！") \ No newline at end of file diff --git a/template.code-workspace_t b/template.code-workspace_t new file mode 100644 index 0000000..4c1bc54 --- /dev/null +++ b/template.code-workspace_t @@ -0,0 +1,39 @@ +{ + "folders": [ + { + "path": "." + } + ], + "settings": { + "files.autoGuessEncoding": true, + "C_Cpp.default.configurationProvider": "cl.eide", + "C_Cpp.errorSquiggles": "disabled", + "files.associations": { + ".eideignore": "ignore", + "*.a51": "a51", + "*.h": "c", + "*.c": "c", + "*.hxx": "cpp", + "*.hpp": "cpp", + "*.c++": "cpp", + "*.cpp": "cpp", + "*.cxx": "cpp", + "*.cc": "cpp" + }, + "[yaml]": { + "editor.insertSpaces": true, + "editor.tabSize": 4, + "editor.autoIndent": "advanced" + }, + "workbench.colorCustomizations": { + "editor.background": "#031110a3", + "editor.lineHighlightBackground": "#1073cf06", + "editor.lineHighlightBorder": "#9fced11f", + "activityBar.background": "#4C2117", + "titleBar.activeBackground": "#6A2E21", + "titleBar.activeForeground": "#FDF9F8" + }, + "EIDE.RISCV.InstallDirectory": "YOUR_WCH_RISCV_GCC_PATH", + "EIDE.OpenOCD.ExePath": "YOUR_WCH_OPENOCD_PATH" + } +} \ No newline at end of file diff --git a/tools/download.cmd b/tools/download.cmd new file mode 100644 index 0000000..f5224d9 --- /dev/null +++ b/tools/download.cmd @@ -0,0 +1,6 @@ +set HEXFILE=%1 + +set "HEXFILE=%HEXFILE:\=/%" + +openocd -f ./tools/wch-riscv.cfg -c init -c halt -c "flash erase_sector wch_riscv 0 last " -c "program %HEXFILE%" -c "verify_image %HEXFILE%" -c wlink_reset_resume -c exit + diff --git a/tools/erase.cmd b/tools/erase.cmd new file mode 100644 index 0000000..27de884 --- /dev/null +++ b/tools/erase.cmd @@ -0,0 +1 @@ +openocd -f .\tools\wch-riscv.cfg -c "flash init; init; reset halt; flash erase_sector 0 1 last" \ No newline at end of file diff --git a/tools/wch-riscv.cfg b/tools/wch-riscv.cfg new file mode 100644 index 0000000..56a18d7 --- /dev/null +++ b/tools/wch-riscv.cfg @@ -0,0 +1,18 @@ +#interface wlink +adapter driver wlinke +adapter speed 6000 +transport select sdi + +wlink_set_address 0x00000000 +set _CHIPNAME wch_riscv +sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1 +set _FLASHNAME $_CHIPNAME.flash + +flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 + +echo "Ready for Remote Connections"