389 lines
13 KiB
C
389 lines
13 KiB
C
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/* add user code begin Header */
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/**
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**************************************************************************
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* @file at32f415_wk_config.c
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* @brief work bench config program
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* add user code end Header */
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#include "at32f415_wk_config.h"
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/* private includes ----------------------------------------------------------*/
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/* add user code begin private includes */
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/* add user code end private includes */
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/* private typedef -----------------------------------------------------------*/
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/* add user code begin private typedef */
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/* add user code end private typedef */
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/* private define ------------------------------------------------------------*/
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/* add user code begin private define */
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/* add user code end private define */
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/* private macro -------------------------------------------------------------*/
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/* add user code begin private macro */
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/* add user code end private macro */
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/* private variables ---------------------------------------------------------*/
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/* add user code begin private variables */
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/* add user code end private variables */
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/* private function prototypes --------------------------------------------*/
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/* add user code begin function prototypes */
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/* add user code end function prototypes */
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/* private user code ---------------------------------------------------------*/
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/* add user code begin 0 */
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/* add user code end 0 */
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/**
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* @brief system clock config program
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* @note the system clock is configured as follow:
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* system clock (sclk) = hick / 12 * pll_mult
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* system clock source = HICK_VALUE
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* - sclk = 144000000
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* - ahbdiv = 1
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* - ahbclk = 144000000
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* - apb1div = 2
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* - apb1clk = 72000000
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* - apb2div = 2
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* - apb2clk = 72000000
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* - pll_mult = 36
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* - flash_wtcyc = 4 cycle
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* @param none
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* @retval none
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*/
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void wk_system_clock_config(void)
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{
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/* reset crm */
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crm_reset();
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/* config flash psr register */
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flash_psr_set(FLASH_WAIT_CYCLE_4);
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/* enable lick */
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crm_clock_source_enable(CRM_CLOCK_SOURCE_LICK, TRUE);
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/* wait till lick is ready */
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while(crm_flag_get(CRM_LICK_STABLE_FLAG) != SET)
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{
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}
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/* enable hick */
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crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE);
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/* wait till hick is ready */
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while(crm_flag_get(CRM_HICK_STABLE_FLAG) != SET)
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{
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}
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/* config pll clock resource */
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crm_pll_config(CRM_PLL_SOURCE_HICK, CRM_PLL_MULT_36);
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/* enable pll */
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crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
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/* wait till pll is ready */
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while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
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{
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}
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/* config ahbclk */
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crm_ahb_div_set(CRM_AHB_DIV_1);
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/* config apb2clk, the maximum frequency of APB2 clock is 75 MHz */
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crm_apb2_div_set(CRM_APB2_DIV_2);
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/* config apb1clk, the maximum frequency of APB1 clock is 75 MHz */
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crm_apb1_div_set(CRM_APB1_DIV_2);
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/* enable auto step mode */
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crm_auto_step_mode_enable(TRUE);
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/* select pll as system clock source */
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crm_sysclk_switch(CRM_SCLK_PLL);
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/* wait till pll is used as system clock source */
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while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
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{
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}
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/* disable auto step mode */
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crm_auto_step_mode_enable(FALSE);
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/* update system_core_clock global variable */
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system_core_clock_update();
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}
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/**
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* @brief config periph clock
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* @param none
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* @retval none
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*/
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void wk_periph_clock_config(void)
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{
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/* enable iomux periph clock */
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crm_periph_clock_enable(CRM_IOMUX_PERIPH_CLOCK, TRUE);
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/* enable gpioa periph clock */
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crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
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/* enable gpiob periph clock */
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crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
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/* enable tmr1 periph clock */
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crm_periph_clock_enable(CRM_TMR1_PERIPH_CLOCK, TRUE);
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/* enable tmr3 periph clock */
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crm_periph_clock_enable(CRM_TMR3_PERIPH_CLOCK, TRUE);
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}
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/**
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* @brief nvic config
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* @param none
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* @retval none
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*/
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void wk_nvic_config(void)
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{
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nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
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}
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/**
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* @brief init tmr1 function.
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* @param none
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* @retval none
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*/
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void wk_tmr1_init(void)
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{
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/* add user code begin tmr1_init 0 */
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/* add user code end tmr1_init 0 */
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gpio_init_type gpio_init_struct;
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tmr_output_config_type tmr_output_struct;
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tmr_brkdt_config_type tmr_brkdt_struct;
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gpio_default_para_init(&gpio_init_struct);
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/* add user code begin tmr1_init 1 */
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/* add user code end tmr1_init 1 */
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/* configure the CH1 pin */
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gpio_init_struct.gpio_pins = GPIO_PINS_8;
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
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gpio_init(GPIOA, &gpio_init_struct);
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/* configure the CH2 pin */
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gpio_init_struct.gpio_pins = GPIO_PINS_9;
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
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gpio_init(GPIOA, &gpio_init_struct);
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/* configure the CH3 pin */
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gpio_init_struct.gpio_pins = GPIO_PINS_10;
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
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gpio_init(GPIOA, &gpio_init_struct);
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/* configure the CH4 pin */
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gpio_init_struct.gpio_pins = GPIO_PINS_11;
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
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gpio_init(GPIOA, &gpio_init_struct);
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/* configure counter settings */
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tmr_base_init(TMR1, 65535, 0);
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tmr_cnt_dir_set(TMR1, TMR_COUNT_UP);
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tmr_clock_source_div_set(TMR1, TMR_CLOCK_DIV1);
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tmr_repetition_counter_set(TMR1, 0);
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tmr_period_buffer_enable(TMR1, FALSE);
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/* configure primary mode settings */
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tmr_sub_sync_mode_set(TMR1, FALSE);
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tmr_primary_mode_select(TMR1, TMR_PRIMARY_SEL_RESET);
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/* configure channel 1 output settings */
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tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF;
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tmr_output_struct.oc_output_state = TRUE;
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tmr_output_struct.occ_output_state = FALSE;
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tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
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tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
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tmr_output_struct.oc_idle_state = FALSE;
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tmr_output_struct.occ_idle_state = FALSE;
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tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_1, &tmr_output_struct);
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tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_1, 0);
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tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_1, FALSE);
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/* configure channel 2 output settings */
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tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF;
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tmr_output_struct.oc_output_state = TRUE;
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tmr_output_struct.occ_output_state = FALSE;
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tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
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tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
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tmr_output_struct.oc_idle_state = FALSE;
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tmr_output_struct.occ_idle_state = FALSE;
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tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_2, &tmr_output_struct);
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tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_2, 0);
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tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_2, FALSE);
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/* configure channel 3 output settings */
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tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF;
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tmr_output_struct.oc_output_state = TRUE;
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tmr_output_struct.occ_output_state = FALSE;
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tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
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tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
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tmr_output_struct.oc_idle_state = FALSE;
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tmr_output_struct.occ_idle_state = FALSE;
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tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_3, &tmr_output_struct);
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tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_3, 0);
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tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_3, FALSE);
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/* configure channel 4 output settings */
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tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF;
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tmr_output_struct.oc_output_state = TRUE;
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tmr_output_struct.occ_output_state = FALSE;
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tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
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tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
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tmr_output_struct.oc_idle_state = FALSE;
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tmr_output_struct.occ_idle_state = FALSE;
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tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_4, &tmr_output_struct);
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tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_4, 0);
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tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_4, FALSE);
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/* configure break and dead-time settings */
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tmr_brkdt_struct.brk_enable = FALSE;
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tmr_brkdt_struct.auto_output_enable = FALSE;
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tmr_brkdt_struct.brk_polarity = TMR_BRK_INPUT_ACTIVE_LOW;
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tmr_brkdt_struct.fcsoen_state = FALSE;
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tmr_brkdt_struct.fcsodis_state = FALSE;
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tmr_brkdt_struct.wp_level = TMR_WP_OFF;
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tmr_brkdt_struct.deadtime = 0;
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tmr_brkdt_config(TMR1, &tmr_brkdt_struct);
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tmr_output_enable(TMR1, TRUE);
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tmr_counter_enable(TMR1, TRUE);
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/* add user code begin tmr1_init 2 */
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/* add user code end tmr1_init 2 */
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}
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/**
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* @brief init tmr3 function.
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* @param none
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* @retval none
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*/
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void wk_tmr3_init(void)
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{
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/* add user code begin tmr3_init 0 */
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/* add user code end tmr3_init 0 */
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gpio_init_type gpio_init_struct;
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tmr_output_config_type tmr_output_struct;
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gpio_default_para_init(&gpio_init_struct);
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/* add user code begin tmr3_init 1 */
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/* add user code end tmr3_init 1 */
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/* configure the CH3 pin */
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gpio_init_struct.gpio_pins = GPIO_PINS_0;
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
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gpio_init(GPIOB, &gpio_init_struct);
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/* configure the CH4 pin */
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gpio_init_struct.gpio_pins = GPIO_PINS_1;
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
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gpio_init(GPIOB, &gpio_init_struct);
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/* configure counter settings */
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tmr_base_init(TMR3, 65535, 0);
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|
tmr_cnt_dir_set(TMR3, TMR_COUNT_UP);
|
||
|
|
tmr_clock_source_div_set(TMR3, TMR_CLOCK_DIV1);
|
||
|
|
tmr_period_buffer_enable(TMR3, FALSE);
|
||
|
|
|
||
|
|
/* configure primary mode settings */
|
||
|
|
tmr_sub_sync_mode_set(TMR3, FALSE);
|
||
|
|
tmr_primary_mode_select(TMR3, TMR_PRIMARY_SEL_RESET);
|
||
|
|
|
||
|
|
/* configure channel 3 output settings */
|
||
|
|
tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF;
|
||
|
|
tmr_output_struct.oc_output_state = TRUE;
|
||
|
|
tmr_output_struct.occ_output_state = FALSE;
|
||
|
|
tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
|
||
|
|
tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
|
||
|
|
tmr_output_struct.oc_idle_state = FALSE;
|
||
|
|
tmr_output_struct.occ_idle_state = FALSE;
|
||
|
|
tmr_output_channel_config(TMR3, TMR_SELECT_CHANNEL_3, &tmr_output_struct);
|
||
|
|
tmr_channel_value_set(TMR3, TMR_SELECT_CHANNEL_3, 0);
|
||
|
|
tmr_output_channel_buffer_enable(TMR3, TMR_SELECT_CHANNEL_3, FALSE);
|
||
|
|
|
||
|
|
/* configure channel 4 output settings */
|
||
|
|
tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF;
|
||
|
|
tmr_output_struct.oc_output_state = TRUE;
|
||
|
|
tmr_output_struct.occ_output_state = FALSE;
|
||
|
|
tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
|
||
|
|
tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
|
||
|
|
tmr_output_struct.oc_idle_state = FALSE;
|
||
|
|
tmr_output_struct.occ_idle_state = FALSE;
|
||
|
|
tmr_output_channel_config(TMR3, TMR_SELECT_CHANNEL_4, &tmr_output_struct);
|
||
|
|
tmr_channel_value_set(TMR3, TMR_SELECT_CHANNEL_4, 0);
|
||
|
|
tmr_output_channel_buffer_enable(TMR3, TMR_SELECT_CHANNEL_4, FALSE);
|
||
|
|
|
||
|
|
|
||
|
|
tmr_counter_enable(TMR3, TRUE);
|
||
|
|
|
||
|
|
/* add user code begin tmr3_init 2 */
|
||
|
|
|
||
|
|
/* add user code end tmr3_init 2 */
|
||
|
|
}
|
||
|
|
|
||
|
|
/* add user code begin 1 */
|
||
|
|
|
||
|
|
/* add user code end 1 */
|